Error checking circuit

Abstract

The present disclosure provides an error checking circuit, comprising: a first generation circuit for generating a read command; and the control circuit is used for reading conventional data in the storage array based on the read command, generating corresponding second verification data based on the conventional data, comparing the second verification data with initial verification data corresponding to the conventional data, and if the second verification data is different from the initial verification data, sending the second verification data to the storage array. If yes, generating an error flag signal of the first state; the second generation circuit is used for receiving the error flag signal and generating a write command based on the error flag signal in the first state; the control circuit is further used for replacing the initial verification data with the second verification data based on the write command.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor, and in particular, to an error checking circuit. BACKGROUND

[0002] Dynamic Random Access Memory (DRAM) is widely used in modern electronic systems due to its high storage density and fast transmission speed. With the development of semiconductor technology, DRAM technology is becoming more and more advanced, and the integration of storage units is becoming higher and higher. At the same time, various applications also require higher performance, lower power consumption and higher reliability of DRAM.

[0003] The existing memory with error detection and correction function (ECC) still faces the problem of inaccurate data error detection and correction during data readout. There is an urgent need for a method that can improve the accuracy of data error detection and correction during data readout. SUMMARY

[0004] Embodiments of the present application provide an error checking circuit, which is at least beneficial to the accuracy of the data storage stage.

[0005] According to some embodiments of the present application, the embodiments of the present application provide an error checking circuit, which includes: a first generation circuit for generating a read command; a control circuit for reading regular data in a storage array based on the read command, and generating corresponding second check data based on the regular data, and for comparing the second check data with initial check data corresponding to the regular data, and if the second check data is different from the initial check data, generating an error flag signal of a first state; a second generation circuit for receiving the error flag signal and generating a write command based on the error flag signal of the first state; and the control circuit is further configured to replace the initial check data with the second check data based on the write command.

[0006] In some embodiments, the error checking circuit further includes an error tracking circuit configured to receive the error flag signal and perform a preset action triggered by the error flag signal of the first state, the preset action being determined by a first mode parameter.

[0007] In some embodiments, the preset action includes at least one of a first preset action, a second preset action and a third preset action, the first preset action being to accumulate the number of rows with errors, the second preset action being to accumulate the number of error bits of the initial check data, and the third preset action being to record the row address corresponding to the initial check data with the most errors and the number of error bits of the initial check data.

[0008] In some embodiments, the error checking circuit further comprises an address generating circuit configured to generate a target row address, and the control circuit is configured to read regular data in the target row address in the memory array based on the read command.

[0009] In some embodiments, the first generating circuit is further configured to generate a pre-charge command, and the control circuit is configured to write back regular data in the target row address and corresponding initial check data based on the pre-charge command.

[0010] In some embodiments, the address generating circuit is further configured to receive the pre-charge command and generate a new target row address.

[0011] In some embodiments, the first generating circuit is further configured to generate a first pre-charge command after generating the read command, and generate a second pre-charge command when the error flag signal is in a first state; the error checking circuit further comprises a gate, a first input end of the gate configured to receive the first pre-charge command, a second input end of the gate configured to receive the second pre-charge command, a control end of the gate configured to receive the error flag signal, and the gate is configured to output the first pre-charge command if the error flag signal in the second state is received, otherwise output the second pre-charge command, and an output signal of the gate is used as a pre-charge command.

[0012] In some embodiments, the second generating circuit is further configured to receive the read command, and the second generating circuit comprises a latch, a first input end of the latch configured to receive the read command, a second input end of the latch configured to receive the error flag signal, and a data output end of the latch configured to output an intermediate flag signal, and the second generating circuit is configured to output the write command if the intermediate flag signal is in a high level.

[0013] In some embodiments, the second generating circuit further comprises a first NOR gate, a first input end of the first NOR gate configured to receive the intermediate flag signal, a second input end of the first NOR gate configured to receive an initial write command, and an output end of the first NOR gate configured to output the write command, and the first generating circuit is further configured to generate the initial write command after generating the read command.

[0014] In some embodiments, the error checking circuit further comprises an enabling circuit configured to output an enabling signal in response to a preset command, and the first generating circuit is configured to output the read command based on the enabling signal, and the preset command is determined by a second mode parameter.

[0015] In some embodiments, the preset command comprises a first type of preset command and a second type of preset command, the first type of preset command is a refresh command, and the second type of preset command is a self-defined command.

[0016] The technical scheme provided by the embodiments of the present application has at least the following advantages: the second generation circuit 13 is arranged to generate the write command Wr based on the error flag signal Error flag, which is beneficial to saving the time and power consumption required for generating the write command Wr and executing the write command in the case where the initial check data does not have errors. BRIEF DESCRIPTION OF DRAWINGS

[0017] One or more embodiments are illustrated by way of example in the figures that form a part of this patent document, and in which like reference numbers typically indicate similar components, features, and steps, unless otherwise specified. The illustrations in the various drawings are not necessarily drawn to scale.

[0018] Figures 1 to 3 A circuit schematic diagram of the error check circuit provided by some embodiments of the present application;

[0019] Figure 4 A timing schematic diagram of the error check circuit provided by some embodiments of the present application. DETAILED DESCRIPTION

[0020] The embodiments of the present application will be described in detail with reference to the drawings. However, those skilled in the art can understand that, in the embodiments of the present application, many technical details are proposed in order to make the readers better understand the present application. However, the technical scheme claimed by the present application can be implemented even without these technical details and based on various changes and modifications of the following embodiments.

[0021] Figures 1 to 3 A circuit schematic diagram of the error check circuit provided by some embodiments of the present application; Figure 4 A timing schematic diagram of the error check circuit provided by some embodiments of the present application.

[0022] REFERENCE Figure 1 The error check circuit includes: a first generation circuit 10 configured to generate a read command Rd; a control circuit 11 configured to read regular data in a storage array 12 based on the read command Rd, generate corresponding second check data based on the regular data, and compare the second check data with initial check data corresponding to the regular data, and if the second check data is different from the initial check data, generate an error flag signal Error flag in a first state; and a second generation circuit 13 configured to receive the error flag signal Error flag and generate a write command Wr based on the error flag signal Error flag in the first state; and the control circuit 11 is further configured to replace the initial check data with the second check data based on the write command Wr.

[0023] The embodiments of the present application will be described in detail with reference to the drawings. However, those skilled in the art can understand that, in the embodiments of the present application, many technical details are proposed in order to make the readers better understand the present application. However, the technical scheme claimed by the present application can be implemented even without these technical details and based on various changes and modifications of the following embodiments.

[0024] In the embodiments of the present application, the first generating circuit 10 can generate the read command Rd under the triggering of the externally input enable signal, or can first generate an intermediate signal internally and then generate the read command Rd based on the intermediate signal. The intermediate signal includes but is not limited to the activation signal Act. The intermediate signal can be generated under the triggering of the externally input enable signal, or can be generated by the first generating circuit 10 according to an internal rule. The internal rule includes having a specific time interval, or being triggered by a specific signal generated internally. The above-mentioned "internal" refers to the inside of the first generating circuit 10.

[0025] Before writing data into the storage array 12, to ensure that the data read out from the storage is the same as the data written in, the control circuit 11 often generates check data based on the regular data to be written in. When an error occurs in the regular data during storage, the check data can be used to check and correct the error of the regular data, thereby ensuring the accuracy of the data read out from the storage. The storage includes the above-mentioned error checking circuit and the storage array.

[0026] In the embodiments of the present application, the check data generated before the regular data is written into the storage array 12 is referred to as "initial check data", and the check data generated after the regular data is read out is referred to as "second check data". Since the regular data can remain unchanged while the check data can be problematic during data storage, it is necessary to check the actual state of the "initial check data". That is, during the storage of the regular data and the initial check data, the regular data is read out and the second check data is generated, and the second check data and the initial check data are compared. If the second check data and the initial check data are different, it is considered that an error has occurred in the initial check data during storage, and the second check data needs to replace the initial check data.

[0027] It should be noted that the present application assumes that the regular data used to generate the second check data is accurate data. The regular data can be data that is read out directly without any checking and correction, or data that is read out and then checked and corrected by other types of check data, or data that is improved in accuracy by other means.

[0028] In the embodiments of the present application, the storage array 12 can be referred to as a core area, and the core area includes a plurality of storage banks. The error checking circuit of the control circuit 11 can be located in a peripheral area other than the core area. The initial check data is usually stored in the storage units in the core area. In addition, the read command generated by the error checking circuit is mainly used for error checking of the check data, so that the read conventional data and check data only exist in the control circuit 11 and are not output to the outside of the memory. The error checking of the present application can be ECC error checking and scrub (ECC Error Check and Scrub, ECS), that is, the above-mentioned check data can be ECC check data.

[0029] In the embodiments of the present application, the second generation circuit 13 is configured to generate the write command Wr based on the error flag signal Error flag, instead of directly generating the write command Wr by the first generation circuit 10 and outputting to the control circuit. This is advantageous in saving the time and power consumption required for generating the write command Wr and executing the write command in the case where no error occurs in the initial check data. Since there are more initial check data without error and less initial check data with error in theory, if the write command Wr is executed regardless of whether there is an error, the power consumption and time length will be greatly increased.

[0030] In some embodiments, the error checking circuit further includes an error tracking circuit 14 configured to receive the error flag signal Error flag and perform a preset action under the triggering of the error flag signal Error flag in the first state. The preset action is determined by the first mode parameter. In the embodiments of the present application, the error flag signal Error flag has at least a first state and a second state. The first state can be a high level, and the second state can be a low level. When the error tracking circuit 14 receives the error flag signal Error flag in the first state, it indicates that the initial check data at this time has an error. The error tracking circuit 14 can perform a preset action defined by the first mode parameter. Different preset actions are used to obtain different error information. After obtaining the error information, the error information can be internally processed to obtain the required information, or the error information can be sent to other devices for analysis and processing.

[0031] In some embodiments, the preset action includes at least one of a first preset action, a second preset action, and a third preset action. The first preset action is to accumulate the number of rows with errors. The second preset action is to accumulate the number of error bits of the initial check data. The third preset action is to record the row address of the initial check data with the most errors and the number of error bits of the initial check data.

[0032] When the first preset action is performed, the error tracking circuit 14 does not need to obtain additional information from the control circuit 11 again, because each time the error flag signal Error flag in the first state is received, it means that an error occurs in a row, and the error tracking circuit 14 only needs to accumulate the number of error flag signals Error flag in the first state received. Finally, the error tracking result can be sent to other devices for analysis of the proportion of the number of error rows to the total number of rows or other analysis actions. It should be noted that the same row address of different banks belongs to different rows.

[0033] When the second preset action is performed, the error tracking circuit 14 needs to obtain the number of error bits of the initial check data from the control circuit 11, so as to accumulate the number of error bits of all original check data, and the error ratio of the original check data can be obtained by subsequent analysis. There are many ways to obtain the number of error bits of the initial check data, including but not limited to: first, the control circuit 11 separately sends the number of error bits, that is, the error flag signal Error flag and the error position information are sent separately; second, when multiple error bits occur in the same original check data, multiple error flag signals Error flag are sent continuously, and the number of error flag signals Error flag is the same as the number of error bits. The error tracking circuit 14 accumulates the number of error bits of the original check data according to the number of error flag signals Error flag received.

[0034] It should be noted that the first preset action and the second preset action can be performed at the same time, for example, the first accumulation device only needs to accumulate the number of error rows by one when receiving one error flag signal Error flag, and shield other error flag signals Error flag in a specific time period. At the same time, the second accumulation device continuously accumulates the number of error bits of the original check data according to the number of error flag signals Error flag received. The above-mentioned specific time period refers to the time required to send the corresponding number of error flag signals Error flag when the original check data is completely wrong. Similarly, any two or any three of the above three preset actions can be performed together, and those skilled in the art can design the corresponding circuit and information transmission mode according to the needs.

[0035] In performing the third preset action, the error tracking circuit 14 can obtain the current row address (or target row address) corresponding to the original check data from the control circuit 11 or the address generation circuit 15. The error tracking circuit 14 can further include a first register for storing the row address, a second register for storing the maximum error bit number of the row address where the error has occurred, and a comparator for comparing the value of the second register and the error bit number of the original check data corresponding to the current row address. If the former is greater than or equal to the latter, the row address in the first register is kept unchanged. If the former is less than the latter, the current row address is obtained and written into the first register, i.e., the row address in the first register is updated.

[0036] In some embodiments, the error tracking circuit 14 further includes an address generation circuit 15 for generating a target row address Target Address, and the control circuit 11 reads the normal data in the target row address Target Address in the storage array 12 based on the read command Rd. That is, each read command Rd is used to read the normal data in different rows in a storage bank. The memory sequentially performs error checking and erasing on the original check data corresponding to the normal data stored in different rows of different storage banks.

[0037] In some embodiments, the first generation circuit 10 is further configured to generate a precharge command Precharge, and the control circuit 11 performs back writing on the normal data in the current target row address Target Address and the corresponding original check data based on the precharge command Precharge. In this way, it is beneficial to avoid data change of the storage cells storing the normal data and the original check data due to charge sharing and inherent charge leakage when the data is read out, and to ensure that the normal data in the target row address and the corresponding original check data can still be effectively stored in the absence of a write command Wr. It should be noted that if the original check data is not stored in the storage array 12 but in a register in the control circuit 11, only the normal data in the target row address can be back written.

[0038] In some embodiments, the address generation circuit 15 is further configured to receive a precharge command Precharge and generate a new target row address Target Address. When the first generation circuit 10 outputs the precharge command Precharge, it indicates that the check for the current initial check data has been completed, and thus the address generation circuit 15 can generate a new target row address Target Address based on the enable of the precharge command Precharge, so as to control the circuit 11 to read the normal data in the new target row address based on the new read command Rd received subsequently. In other embodiments, the address generation circuit 15 can also generate the new target row address and send it to the control circuit 11 in a timing manner, without receiving the precharge command Precharge as a trigger signal.

[0039] In some embodiments, the first generation circuit 10 is further configured to generate a first precharge command after generating the read command Rd, and generate a second precharge command based on the first precharge command when the error flag signal Error flag is in the first state; the error check circuit further comprises a gate, a first input end of the gate is configured to receive the first precharge command, a second input end of the gate is configured to receive the second precharge command, a control end of the gate is configured to receive the error flag signal Error flag, if the error flag signal in the second state is received, the first precharge command is output, otherwise the second precharge command is output, and an output signal of the gate is the above-mentioned precharge command.

[0040] Reference Figure 2 In some embodiments, the first generation circuit 10 is further configured to generate a first precharge command after generating the read command Rd, and generate a second precharge command based on the first precharge command when the error flag signal Error flag is in the first state; the error check circuit further comprises a gate, a first input end of the gate is configured to receive the first precharge command, a second input end of the gate is configured to receive the second precharge command, a control end of the gate is configured to receive the error flag signal Error flag, if the error flag signal in the second state is received, the first precharge command is output, otherwise the second precharge command is output, and an output signal of the gate is the above-mentioned precharge command.

[0041] The first generation circuit 10 further comprises an OR gate 104, a first input end of the OR gate 104 receives the initial write command, a second input end receives an inverted signal of the error flag signal Error flag-N, and an output end is connected with an input end of a fifth delay circuit 105, and an output end of the fifth delay circuit 105 is used to output a second pre-charge command precharge2; a gate 106, a first input end of the gate 106 receives the second pre-charge command precharge2, a second input end receives a first pre-charge command precharge1, and a control end receives the error flag signal Error flag, when the error flag signal Error flag is in a first state (high level, marked as H), it indicates that there is an error in the initial check data, at this time, rewriting is needed through the write command Wr, and therefore, the second pre-charge command precharge2 after the initial write command OrigWr needs to be output as a pre-charge command to perform a write back after rewriting; when the error flag signal Error flag is in a second state (low level, marked as L), it indicates that there is no error in the initial check data, at this time, the first pre-charge command precharge1 before the initial write command OrigWr needs to be output as a pre-charge command to perform a write back as soon as possible.

[0042] It should be noted that in some embodiments, the purpose of setting the OR gate is to control the output end of the OR gate to remain unchanged at a high level when the error flag signal Error flag is in the first state, so that the second pre-charge command is not generated, and the power consumption of the first generation circuit 10 is further reduced; in other embodiments, the OR gate can be replaced by an AND gate to control the output end of the OR gate to remain unchanged at a low level when the error flag signal Error flag is in the first state, so as to further reduce the power consumption; or, the output end of the fourth delay circuit 1032 is directly connected with the input end of the fifth delay circuit 105, and the second pre-charge command precharge2 is always generated.

[0043] In some embodiments, the first generation circuit 10 further comprises a first delay circuit 101 and a second delay circuit 102, the first delay circuit 101 generates an activation command Act after receiving an enable signal Enable and after a first delay time corresponding to the first delay circuit 101, and the control circuit 11 is further used to receive the activation command Act to activate a word line corresponding to a current target row address. The second delay circuit 102 is used to receive the activation command Act and generate a read command Rd after a second delay time corresponding to the second delay circuit 102. In some embodiments, the first delay circuit 101 and the second delay circuit 102 are respectively connected with the first delay circuit 101 and the second delay circuit 102. Figure 3The second generating circuit 13 is also configured to receive a read command Rd, and the second generating circuit 13 comprises a latch 13a, a first input end of the latch 13a is configured to receive the read command Rd, a second input end of the latch 13a is configured to receive the error flag signal Error flag, and a data output end of the latch 13a is configured to output an intermediate flag signal Middle flag. When the intermediate flag signal Middle flag is at a high level, the write command Rd is output. The latch 13a can be a latch composed of an NOR gate. In other embodiments, the second generating circuit can also output the delayed error flag signal as the write command.

[0044] In some embodiments, further referring to Figure 3 The second generating circuit 13a further comprises a first NOR gate 131, a first input end of the first NOR gate 131 is configured to receive the intermediate flag signal Middle flag, a second input end of the first NOR gate 131 is configured to receive an original write command OrigWr, and an output end of the first NOR gate 131 is configured to output the write command Wr. The first generating circuit 10 is further configured to generate the original write command OrigWr after generating the read command Rd. It can be understood that the original write command OrigWr at a high level can be used to set the write command Wr to low, so as to avoid the write command Wr from being at a high level for too long.

[0045] In some embodiments, the latch 13a further comprises a second NOR gate 132 and a third NOR gate 133. A first input end of the second NOR gate 132 is configured to receive the error flag signal Error flag, a second input end of the second NOR gate 132 is connected to an output end of the third NOR gate 133, a first input end of the third NOR gate 133 is connected to an output end of the second NOR gate 132, a second input end of the third NOR gate 133 is configured to receive the read command Rd, and an output end of the second NOR gate 132 is configured to output the intermediate flag signal Middle flag. It can be understood that the read command Rd and the write command Wr mentioned above are both pulse signals. Before the error flag signal Error flag jumps to a high level, the read command Rd has already jumped to a low level, and the read command Rd also functions to set the write command Wr to low.

[0046] In some embodiments, the error checking circuit further comprises an enabling circuit 16 configured to output an enabling signal Enable in response to a preset command. The first generating circuit 10 is configured to output the read command Rd based on the enabling signal Enable. The preset command is determined by the second mode parameter MR2. That is, the preset command can include multiple types, and the enabling circuit 16 determines the type of the specific response signal according to the content of the second mode parameter MR2.

[0047] The preset commands include first-type preset commands and second-type preset commands, the first-type preset commands are refresh commands, and the second-type preset commands are custom commands. The refresh commands at least include a self-refresh command Self-refresh and a global refresh command Refab. The self-refresh command Self-refresh is used for power saving, and the memory does not need to be continuously sent the refresh command by the memory controller. After receiving the self-refresh command Self-refresh, the memory generates an internal command for refreshing by using an internal oscillator. The global refresh command Refab refers to refreshing all banks in the memory at one time. The custom command is usually one of multi-purpose commands (MPC). The multi-purpose command is a command without an explicit function definition, and a designer can select a suitable command (for example, 00001100) as a trigger signal of the enable circuit.

[0048] In some embodiments, with reference to Figure 1 , the first generation circuit 10 is further configured to receive a first reset signal Reset1, and in a case where all output signals of the first generation circuit 10 are high active, the first reset signal Reset1 is used to pull down all output signals of the first generation circuit 10, such as the activate command Act, the read command Rd, the first precharge command precharge1, the initial write command OrigWr, the second precharge command precharge2, and the precharge command Precharge. Figure 1 and Figure 3 , the second generation circuit 13 is further configured to receive a second reset signal Reset2, the second reset signal Reset2 is connected to a third output end of the third NOR gate 133, and is used to pull down the write command Wr output by the second generation circuit 13. Figure 1 , the error tracking circuit 14 is further configured to receive a third reset signal Reset3, the third reset signal Reset3 is used to reset the first mode parameter MR1 stored in the error tracking circuit 14, so as to wait for a new first mode parameter MR1, or is used to reset an output result of the error tracking circuit 14, so as to update the output information. The address generation circuit 15 is further configured to receive a fourth reset signal Reset4, the fourth reset signal Reset4 is used to reset a current target row address in the address generation circuit 15, so that the current target row address returns to an initial state and reenters a loop. The enable circuit 16 is further configured to receive a fifth reset signal Reset5, the fifth reset signal Reset5 is used to reset the second mode parameter MR2 stored in the enable circuit 16, so as to wait for a new second mode parameter MR2, or is used to pull down the enable signal Enable output by the enable circuit 16.

[0049] Reference Figure 4 In the embodiment of the present application, if the error flag signal Error flag has a high level state, the second generating circuit 13 generates the corresponding write command Wr, and if the error flag signal Error flag is in a low level state, the corresponding write command Wr is not generated (the write command is not generated this time is indicated by a dashed line), and the control circuit 11 receives the high level precharge command precharge after receiving the high level read command Rd.

[0050] Those skilled in the art can understand that the above-mentioned embodiments are specific embodiments for implementing the present application, and in actual application, various changes can be made in form and details without departing from the spirit and scope of the present application. Any person skilled in the art can make changes and modifications without departing from the spirit and scope of the present application, therefore the protection scope of the present application should be limited by the scope defined in the claims.

Claims

1. An error checking circuit, characterized by The method comprises: generating a read command by a first generating circuit; reading normal data in a memory array based on the read command by a control circuit, generating corresponding second check data based on the normal data, and comparing the second check data with initial check data corresponding to the normal data, and generating an error flag signal in a first state if the second check data is different from the initial check data; generating a write command based on the error flag signal in the first state by a second generating circuit; replacing the initial check data with the second check data based on the write command by the control circuit.

2. The error checking circuit of claim 1, wherein, The method further comprises: receiving the error flag signal by an error tracking circuit, and performing a preset action under the triggering of the error flag signal in the first state, the preset action being determined by a first mode parameter.

3. The error checking circuit of claim 2, wherein, The preset action comprises at least one of a first preset action, a second preset action, and a third preset action, the first preset action being to accumulate the number of rows with errors, the second preset action being to accumulate the number of error bits of the initial check data, and the third preset action being to record the row address corresponding to the initial check data with the most errors and the number of error bits of the initial check data.

4. The error checking circuit of claim 1, wherein, The method further comprises: generating a target row address by an address generating circuit, and reading normal data in the target row address in the memory array based on the read command by the control circuit.

5. The error checking circuit of claim 4, wherein, The first generating circuit is further configured to generate a pre-charge command, and the control circuit is configured to perform a write-back on the normal data in the current target row address and the corresponding initial check data based on the pre-charge command.

6. The error checking circuit of claim 5, wherein, The address generating circuit is further configured to receive the pre-charge command and generate a new target row address.

7. The error checking circuit of claim 5, wherein, The first generating circuit is further configured to generate a first pre-charge command after generating the read command, and generate a second pre-charge command based on the first pre-charge command when the error flag signal is in the first state. The error checking circuit further comprises: a gate, a first input end of the gate being configured to receive the first pre-charge command, a second input end of the gate being configured to receive the second pre-charge command, a control end of the gate being configured to receive the error flag signal, the gate outputting the first pre-charge command if the error flag signal in the second state is received, otherwise outputting the second pre-charge command, and an output signal of the gate being used as a pre-charge command.

8. The error checking circuit of claim 1, wherein, The second generating circuit is further configured to receive the read command, and the second generating circuit comprises a latch, a first input end of the latch being configured to receive the read command, a second input end of the latch being configured to receive the error flag signal, and a data output end of the latch being configured to output an intermediate flag signal, the latch outputting the write command if the intermediate flag signal is in a high level.

9. The error checking circuit of claim 8, wherein, The second generating circuit further comprises a first NOR gate, a first input end of the first NOR gate being configured to receive the intermediate flag signal, a second input end of the first NOR gate being configured to receive an initial write command, and an output end of the first NOR gate outputting the write command, the first generating circuit being further configured to generate the initial write command after generating the read command.

10. The error checking circuit of claim 1, wherein, The method further comprises: An enabling circuit outputs an enabling signal in response to a preset command, the first generating circuit outputs the read command based on the enabling signal, and the preset command is determined by a second mode parameter.

11. The error checking circuit of claim 10, wherein, The preset command includes a first type of preset command and a second type of preset command, the first type of preset command is a refresh command, and the second type of preset command is a self-defined command.

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