High PSRR band-gap reference voltage source without operational amplifier
By using an op-amp-free high PSRR bandgap reference voltage source structure, and replacing the op-amp with a Cascode current mirror, negative feedback, and voltage clamping module, the problem of op-amp offset affecting accuracy is solved. This achieves a reference voltage source with high PSRR and low power consumption under high voltage, adapting to a wide power supply voltage range and meeting the requirements of high accuracy and dynamic stability.
Patent Information
- Application Number
- CN202511770201.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-28
- Publication Date
- 2026-02-06
AI Technical Summary
In existing reference voltage source structures, operational amplifier offset affects accuracy, and high-gain operational amplifiers increase complexity and power consumption under high voltage conditions, making it difficult to maintain good output accuracy and PSRR performance under high voltage.
By employing a Cascode current mirror module, a negative feedback module, a voltage clamping module, and a bandgap core and reference output module to replace operational amplifiers, an op-amp-free high PSRR bandgap reference voltage source is constructed. The Cascode current mirror module provides high-precision bias current, the negative feedback module provides dynamic stability, the voltage clamping module achieves static voltage matching, and the bandgap core generates a stable reference voltage that is independent of power supply voltage, process, and temperature.
Without increasing complexity and power consumption, it achieves good output accuracy and high PSRR performance under high voltage, adapts to a wider RF range, reduces power consumption, and improves the dynamic stability and power supply noise suppression of the circuit.
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Figure CN121478062A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of voltage source technology, and particularly to the field of high PSRR bandgap reference voltage source technology. Background Technology
[0002] A reference voltage source is a precise and stable voltage source used as a reference in a circuit. For analog systems, the performance of the reference voltage source directly affects the accuracy and performance of the entire system. Reference voltage sources are widely used in various analog and mixed-signal circuits. For example, it is a key circuit unit in voltage regulators. It is also an indispensable component in DC-DC converters. Furthermore, reference voltage sources are used in analog-to-digital or digital-to-analog converters to provide a reference voltage for converting analog voltages to digital voltages. Reference voltage sources are also required in various instruments requiring high accuracy, such as voltmeters, ohmmeters, and ammeters.
[0003] Currently, the commonly used reference voltage source is the Brokaw structure. However, due to the presence of operational amplifiers, the offset of the operational amplifiers can greatly affect the accuracy of the reference voltage. Therefore, this structure often requires high-gain operational amplifiers. High-gain operational amplifiers can not only improve the accuracy of the model, but also help to achieve a high power supply rejection ratio. However, with the increase of operational amplifiers, the structure of the operation becomes relatively complex under high voltage conditions, and the power consumption increases.
[0004] In view of the above, this application is hereby submitted. Summary of the Invention
[0005] This invention provides an op-amp-free high PSRR bandgap reference voltage source. It has a relatively simple structure without the need for an op-amp, and can still have good output accuracy and good PSRR performance under high voltage conditions.
[0006] To achieve the above objectives, the present invention is implemented through the following technical solution:
[0007] An op-amp-free high PSRR bandgap reference voltage source is provided, including a Cascode current mirror module, a negative feedback module, a voltage clamping module, and a bandgap core and reference output module;
[0008] The Cascode current mirror module is used to provide a high-precision and high-stability bias current.
[0009] The negative feedback module is used to provide dynamic stability and ensure that the operating point is resistant to disturbances;
[0010] The voltage clamping module is used to achieve static voltage matching, replacing the core clamping function of the operational amplifier;
[0011] The bandgap core and reference output module are used to generate a stable reference voltage that is independent of power supply voltage, process, and temperature.
[0012] The Cascode current mirror module includes a fifth resistor, a fourth MOSFET, a fifth MOSFET, a sixth MOSFET, and a seventh MOSFET;
[0013] The negative feedback module includes a first MOSFET, a second MOSFET, and an eighth MOSFET;
[0014] The voltage clamping module includes a third MOS transistor;
[0015] The bandgap core and reference output module includes a first resistor, a second resistor, a third resistor, a fourth resistor, a first transistor, a second transistor, and a capacitor;
[0016] Among them, the first, second, third, fourth, fifth, sixth, and seventh MOSFETs are PMOS transistors; the eighth MOSFET is an NMOS transistor.
[0017] In the Cascode module, the drain of the fourth MOS transistor is connected to VDD, the gate of the fourth MOS transistor is connected to the gate of the sixth MOS transistor and the source of the fifth MOS transistor, and the source of the fourth MOS transistor is connected to the drain of the fifth MOS transistor.
[0018] The gate of the fifth MOSFET is connected to the gate of the seventh MOSFET and the other end of the fifth resistor, respectively, and the source of the fifth MOSFET is also connected to one end of the fifth resistor.
[0019] The drain of the sixth MOSFET is connected to VDD, the source of the sixth MOSFET is connected to the drain of the seventh MOSFET, the gate of the seventh MOSFET is also connected to the other end of the fifth resistor, and the source of the seventh MOSFET is connected to the drain of the first MOSFET and the drain of the second MOSFET in the negative feedback module, and the drain of the third MOSFET in the voltage clamping module.
[0020] In the negative feedback module, the drain of the first MOS transistor is also connected to the drain of the second MOS transistor and the drain of the third MOS transistor in the voltage clamping module, respectively. The gate of the first MOS transistor is connected to the source of the first MOS transistor and the gate of the second MOS transistor, respectively. The source of the first MOS transistor is also connected to the collector of the first transistor in the bandgap core and reference output module.
[0021] The drain of the second MOS transistor is also connected to the drain of the third MOS transistor in the voltage clamping module, and the gate of the second MOS transistor is also connected to the source of the first MOS transistor. The source of the second MOS transistor is connected to the gate of the third MOS transistor in the voltage clamping module, the gate of the eighth MOS transistor, the bandgap core, and the collector of the second transistor in the reference output module.
[0022] The drain of the eighth MOS transistor is connected to the other end of the fifth resistor in the Cascode current mirror module, the gate of the fifth MOS transistor, and the gate of the seventh MOS transistor. The gate of the eighth MOS transistor is also connected to the gate of the third MOS transistor in the voltage clamping module. The source of the eighth MOS transistor is connected to VREF, one end of the fourth resistor in the bandgap core and reference output module, the collector of the first transistor, and the collector of the second transistor.
[0023] In the voltage clamping module, the source of the third MOS transistor is grounded;
[0024] In the bandgap core and reference output module, one end of the capacitor is connected to VREF and the other end is grounded; the fourth resistor is connected in series with the third resistor, one end of the third resistor is grounded, and one end of the fourth resistor is also connected to VREF, the base of the first transistor, and the base of the second transistor.
[0025] The base of the first transistor is also connected to one end of the fourth resistor, VREF, and the base of the second transistor; the emitter of the first transistor is connected to one end of the second resistor.
[0026] The emitter of the second transistor is connected to the other end of the second resistor;
[0027] The other end of the second resistor is also connected to one end of the first resistor, and the other end of the first resistor is grounded.
[0028] Compared with the prior art, the present invention achieves the following technical effects:
[0029] This invention improves the compression point without changing the process, enabling the circuit to operate over a wider radio frequency acceptance range. Attached Figure Description
[0030] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the description will be briefly introduced below. Obviously, the drawings described below are one embodiment of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort:
[0031] Figure 1 This is a schematic diagram of the circuit structure of the high PSRR bandgap reference voltage source without op-amp in this embodiment;
[0032] Figure 2 This is a schematic diagram of the DC sweep simulation of the reference voltage source in this embodiment;
[0033] Figure 3 This is a simulation diagram illustrating the stability of the reference voltage source in this embodiment;
[0034] Figure 4This is a simulation diagram of the power supply rejection ratio of the reference voltage source in this embodiment. Detailed Implementation
[0035] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, further illustrates the solution proposed by the present invention. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, used only to facilitate and clearly illustrate the embodiments of the present invention. Please refer to the drawings to make the objectives, features, and advantages of the present invention more apparent and understandable. It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and are not intended to limit the implementation conditions of the present invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effects and objectives achieved by the present invention, should still fall within the scope of the technical content disclosed in the present invention.
[0036] Figure 1 A schematic diagram of the circuit structure of the high PSRR bandgap reference voltage source without op-amp in this embodiment is shown. Figure 1 As shown, the op-amp-less high PSRR bandgap reference voltage source of this embodiment includes a Cascode current mirror module 10, a negative feedback module 20, a voltage clamping module 30, and a bandgap core and reference output module 40. Point A is the source of the first MOSFET, point B is the source of the second MOSFET, point C is the source of the eighth MOSFET, and point D is the drain of the third MOSFET.
[0037] The Cascode current mirror module 10 provides high-precision and high-stability bias current; the negative feedback module 20 provides dynamic stability, ensuring the operating point is resistant to disturbances; the voltage clamping module 30 achieves static voltage matching, replacing the core clamping function of the operational amplifier; the bandgap core and reference output module 40 generates a stable reference voltage independent of power supply voltage, process, and temperature; the Cascode current mirror module 10 includes a fifth resistor R5, a fourth MOSFET M4, a fifth MOSFET M5, a sixth MOSFET M6, and a seventh MOSFET M7; the negative feedback module 20 includes a first MOSFET M1, a second MOSFET M2, and an eighth MOSFET M8; the voltage clamping module 30 includes a third MOSFET M1... 3; The bandgap core and reference output module 40 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first transistor Q1, a second transistor Q2, and a capacitor; wherein, the first MOSFET M1, the second MOSFET M2, the third MOSFET M3, the fourth MOSFET M4, the fifth MOSFET M5, the sixth MOSFET M6, and the seventh MOSFET M7 are PMOS; the eighth MOSFET M8 is NMOS; in the Cascode module 10, the drain of the fourth MOSFET M4 is connected to VDD, the gate of the fourth MOSFET M4 is connected to the gate of the sixth MOSFET M6 and the source of the fifth MOSFET M5, and the source of the fourth MOSFET M4 is connected to the drain of the fifth MOSFET M5. Connections: The gate of the fifth MOSFET M5 is connected to the gate of the seventh MOSFET M7 and the other end of the fifth resistor R5, respectively. The source of the fifth MOSFET M5 is also connected to one end of the fifth resistor R5. The drain of the sixth MOSFET M6 is connected to VDD. The source of the sixth MOSFET M6 is connected to the drain of the seventh MOSFET M7. The gate of the seventh MOSFET M7 is also connected to the other end of the fifth resistor R5. The source of the seventh MOSFET M7 is connected to the drain of the first MOSFET M1 and the drain of the second MOSFET M2 in the negative feedback module 20, and the drain of the third MOSFET M3 in the voltage clamping module 30, respectively. In the negative feedback module 20, the drain of the first MOSFET M1 is also connected to the drain of the second MOSFET M2, respectively. The drain of the third MOS transistor M3 in the voltage clamping module 30 is connected. The gate of the first MOS transistor M1 is connected to the source of the first MOS transistor M1 and the gate of the second MOS transistor M2. The source of the first MOS transistor M1 is also connected to the collector of the first transistor Q1 in the bandgap core and reference output module 40. The drain of the second MOS transistor M2 is also connected to the drain of the third MOS transistor M3 in the voltage clamping module 30. The gate of the second MOS transistor M2 is also connected to the source of the first MOS transistor M1. The source of the second MOS transistor M2 is connected to the gate of the third MOS transistor M3 in the voltage clamping module 30, the gate of the eighth MOS transistor M8, the bandgap core and the collector of the second transistor Q2 in the reference output module 40.The drain of the eighth MOSFET M8 is connected to the other end of the fifth resistor R5 in the Cascode current mirror module 10, the gate of the fifth MOSFET M5, and the gate of the seventh MOSFET M7. The gate of the eighth MOSFET M8 is also connected to the gate of the third MOSFET M3 in the voltage clamping module 30. The source of the eighth MOSFET M8 is connected to VREF, one end of the fourth resistor R4 in the bandgap core and reference output module 40, the collector of the first transistor Q1, and the collector of the second transistor Q2. In the voltage clamping module 30, the source of the third MOSFET M3 is grounded. The bandgap core and reference output module 40 are connected to the reference output module 40. In the quasi-output module 40, one end of the capacitor is connected to VREF, and the other end is grounded; the fourth resistor R4 is connected in series with the third resistor R3, one end of the third resistor R3 is grounded, and one end of the fourth resistor R4 is also connected to VREF; the collector of the first transistor Q1 is also connected to one end of the fourth resistor R4, VREF, and the collector of the second transistor Q2; the emitter of the first transistor Q1 is connected to one end of the second resistor R2; the emitter of the second transistor Q2 is connected to the other end of the second resistor R2; the other end of the second resistor R2 is also connected to one end of the first resistor R1, and the other end of the first resistor R1 is grounded.
[0038] In this embodiment, the bandgap reference voltage source features dynamic servo feedback, stable bias function, and hardware-level static clamping. The specific principle is as follows:
[0039] First, M1, M2, M8, Q1, and Q2 form a negative feedback circuit: when a disturbance occurs in the circuit, the potential at point A rises, and the potential at point B falls accordingly. M8 acts as a source follower, and the potential at point C also falls as point B falls, thereby causing the potential at the gate of Q1 to fall, which in turn causes the potential at point A to fall, thus forming negative feedback. This enables the circuit to achieve dynamic adjustment, thereby stabilizing and improving PSRR capability.
[0040] Secondly, M4, M5, M6, and M7 form a cascode current mirror, which not only improves the output impedance but also reduces the impact of voltage changes on VDD on the current mirror, thereby ensuring accurate current replication and improving the overall circuit's PSRR performance.
[0041] Furthermore, the potential clamping functions of VA (potential at point A) and VB (potential at point B) are mainly implemented by M3, through... Figure 1 From the circuit shown, we can determine that IC (the current flowing through point C) and IA (the current flowing through point A) are respectively:
[0042] IC = VREF / R8 + R7
[0043] IA = VREF - Vbe / R4 + R1
[0044] Thus, IA=IC can be achieved by adjusting the resistance values of R1 and R4, and R7 and R8.
[0045] Subsequently, the width (W) of M6 and M7 is set to N times the width of M4 and M5, respectively. Since IA = IC, the current flowing through M6 is N times IA. At this time, the source potentials of M1, M2, and M3 are all connected at point D, and M2 and M3 have the same dimensions. The current mirror makes IA = IB and IE = (N-2) * IA, which can be calculated using the following formula:
[0046]
[0047] in, Where is the electron mobility, COX is the gate oxide capacitance per unit area, W / L is the width-to-length ratio, VGS1 is the gate-to-source voltage of the first MOSFET, and VTH is the threshold voltage of the first MOSFET.
[0048] When the W / L (width / length) of M3 is N-2 times the size of M1, since the S terminals of both M3 and M1 are connected to point D, the Vgs3 of M3 = the Vgs1 of M1, and thus VA = VB, thereby achieving the potential clamping function.
[0049] Figure 2 This is a DC sweep simulation diagram of the reference voltage source in this embodiment, showing the relationship between the output reference voltage VREF and the power supply voltage VDD. In the simulation, the horizontal axis represents the power supply voltage VDD (unit: V), and the vertical axis represents the output reference voltage VREF (unit: V). As can be seen from the figure, when VDD sweeps within the range of 3V to 20V, VREF remains basically stable with minimal fluctuations. This indicates that the reference voltage source has excellent output voltage stability over a wide power supply voltage range, can adapt to high-voltage operating environments, and meets practical application requirements.
[0050] Figure 3 This is a simulation diagram illustrating the stability of the reference voltage source in this embodiment, used to evaluate the loop stability of the circuit. In the simulation diagram, the horizontal axis represents frequency (unit: Hz), and the vertical axis includes two curves: the first curve represents phase margin (unit: °), and the second curve represents gain (unit: dB). The simulation results show that the gain is approximately 64 dB and the phase margin is approximately 79.6°. This indicates that the loop has high gain and sufficient phase margin, ensuring the circuit remains stable during dynamic operation, exhibiting strong disturbance rejection capability, and meeting the design requirements of a high-precision reference source.
[0051] Figure 4This is a simulation diagram of the power supply rejection ratio (PSRR) of the reference voltage source in this embodiment, used to measure the circuit's ability to suppress power supply noise. In the simulation, the horizontal axis represents frequency (unit: Hz), and the vertical axis represents the PSRR value (unit: dB). The simulation results show that the PSRR is as high as approximately 132 dB in the low-frequency range, which demonstrates the circuit's excellent power supply noise suppression performance. This helps to provide a clean reference voltage in mixed-signal systems and reduce the impact of power supply fluctuations on accuracy. This result verifies the advantages of the op-amp-less structure in maintaining a high PSRR, simplifying the design and reducing power consumption compared to traditional op-amp structures.
[0052] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0053] Although the present invention has been described in detail through the preferred embodiments above, it should be understood that the above description should not be considered as a limitation of the present invention. Various modifications and substitutions to the present invention will be apparent to those skilled in the art after reading the above description. Therefore, the scope of protection of the present invention should be defined by the appended claims.
Claims
1. A high-PSRR bandgap reference voltage source without operational amplifier, characterized in that, it comprises a Cascode current mirror module, a negative feedback module, a voltage clamping module, and a bandgap core and reference output module; the Cascode current mirror module is configured to provide high-precision and high-stability bias current; the negative feedback module is configured to provide dynamic stability and ensure the working point against disturbance; the voltage clamping module is configured to realize static voltage matching and replace the core clamping function of the operational amplifier; the bandgap core and reference output module is configured to generate stable reference voltage independent of power supply voltage, process and temperature; the Cascode current mirror module comprises a fifth resistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, and a seventh MOS transistor; the negative feedback module comprises a first MOS transistor, a second MOS transistor, and an eighth MOS transistor; the voltage clamping module comprises a third MOS transistor; the bandgap core and reference output module comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a first triode, a second triode, and a capacitor; wherein the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, the sixth MOS transistor, and the seventh MOS transistor are PMOS, and the eighth MOS transistor is NMOS; in the Cascode module, the drain of the fourth MOS transistor is connected with VDD, the gate of the fourth MOS transistor is connected with the gate of the sixth MOS transistor and the source of the fifth MOS transistor respectively, and the source of the fourth MOS transistor is connected with the drain of the fifth MOS transistor; the gate of the fifth MOS transistor is connected with the gate of the seventh MOS transistor and the other end of the fifth resistor respectively, and the source of the fifth MOS transistor is also connected with one end of the fifth resistor; the drain of the sixth MOS transistor is connected with VDD, the source of the sixth MOS transistor is connected with the drain of the seventh MOS transistor, the gate of the seventh MOS transistor is also connected with the other end of the fifth resistor, and the source of the seventh MOS transistor is connected with the drain of the first MOS transistor in the negative feedback module, the drain of the second MOS transistor in the negative feedback module, and the drain of the third MOS transistor in the voltage clamping module respectively; in the negative feedback module, the drain of the first MOS transistor is also connected with the drain of the second MOS transistor and the drain of the third MOS transistor in the voltage clamping module respectively, the gate of the first MOS transistor is connected with the source of the first MOS transistor and the gate of the second MOS transistor respectively, and the source of the first MOS transistor is also connected with the collector of the first triode in the bandgap core and reference output module; the drain of the second MOS transistor is also connected with the drain of the third MOS transistor in the voltage clamping module, the gate of the second MOS transistor is also connected with the source of the first MOS transistor, and the source of the second MOS transistor is connected with the gate of the third MOS transistor in the voltage clamping module, the gate of the eighth MOS transistor, and the collector of the second triode in the bandgap core and reference output module respectively. The drain of the eighth MOS is connected with the other end of the fifth resistor in the Cascode current mirror module, the gate of the fifth MOS, and the gate of the seventh MOS, respectively. The gate of the eighth MOS is also connected with the gate of the third MOS in the voltage clamping module. The source of the eighth MOS is connected with VREF, one end of the fourth resistor in the band gap core and reference output module, the collector of the first transistor, and the collector of the second transistor, respectively. In the voltage clamping module, the source of the third MOS is grounded. In the band gap core and reference output module, one end of the capacitor is connected with VREF, and the other end is grounded. The fourth resistor is connected with the third resistor in series. One end of the third resistor is grounded. One end of the fourth resistor is also connected with VREF, the base of the first transistor, and the base of the second transistor. The base of the first transistor is also connected with one end of the fourth resistor, VREF, and the base of the second transistor. The emitter of the first transistor is connected with one end of the second resistor. The emitter of the second transistor is connected with the other end of the second resistor. The other end of the second resistor is also connected with one end of the first resistor. The other end of the first resistor is grounded.