Embedded electronic device and nonvolatile data storage system thereof

Abstract

The invention relates to an embedded electronic device and a nonvolatile data storage system thereof, and belongs to the field of data storage of embedded electronic devices. The system comprises a processor, an FPGA and a nonvolatile memory, and the processor is in communication connection with the FPGA and used for issuing a read-write instruction to the FPGA; the FPGA is connected with the nonvolatile memory through a data line and is used for reading and writing data into the nonvolatile memory; two, three or more than four storage areas are arranged in the nonvolatile memory, the FPGA is used for selecting the storage area to be written according to a set rule when data are written into the nonvolatile memory every time, and the set rule is that the storage area selected this time is different from the storage area written last time. The device comprises a power supply circuit and the nonvolatile data storage system, wherein the power supply circuit is used for supplying power to the nonvolatile data storage system. According to the invention, the device can obtain the non-volatile data with timeliness before power failure after the device is restarted due to abnormal power failure, and the integrity of system data is ensured.

Description

Technical Field

[0001] This invention belongs to the field of data storage in embedded electronic devices, and specifically relates to an embedded electronic device and its non-volatile data storage system. Background Technology

[0002] Non-volatile data in embedded electronic devices refers to data that needs to be preserved after the device loses power, such as PLC operating status data. Currently, the main methods for preserving non-volatile data are as follows:

[0003] 1) Storing non-volatile data in the device's flash memory or EEPROM memory. This method may fail due to power outages during data writing, potentially damaging data already stored in memory and affecting system integrity. Furthermore, flash memory has a limited write endurance, making it unsuitable for scenarios requiring frequent data updates (tens of times per second).

[0004] 2) Non-volatile data is still stored in volatile memory, but battery backup is used for the volatile memory. This method relies on battery life, may be greatly affected by operating conditions, and data will be lost if the device is not powered on again before the battery is depleted.

[0005] To address this, Chinese invention patent application CN110334041A discloses a non-volatile, high-capacity, high-speed data storage device for a digital signal processor (DSP). This device includes an FPGA, an eMMC memory chip, flash memory, and an SPI interface. The FPGA is connected to the eMMC memory chip via a high-speed serial interface, and to the DSP via an SRIO high-speed communication interface. The FPGA and flash memory are connected via an SPI interface. When storing non-volatile data in the DSP, the DSP sends data to the FPGA via the SRIO high-speed communication interface, and the FPGA then sends the data to the eMMC memory chip via the high-speed serial interface. When reading data, data is sent from the eMMC memory chip to the FPGA via the high-speed serial interface, and the FPGA then sends the data to the DSP via the SRIO high-speed communication interface. Although this storage device uses non-volatile eMMC memory to store non-volatile data, power interruptions can still occur during data writing, potentially causing operation failure and corrupting data already stored in the eMMC memory chip, thus affecting system integrity. Summary of the Invention

[0006] The purpose of this invention is to provide an embedded electronic device and its non-volatile data storage system to solve the problem that existing storage devices fail to operate due to power outages, thereby damaging the data already stored in the memory and affecting the integrity of the system.

[0007] The present invention provides a non-volatile data storage system for embedded electronic devices to solve the above-mentioned technical problems. The system includes a processor, an FPGA, and a non-volatile memory. The processor is communicatively connected to the FPGA and is used to issue read / write commands to the FPGA. The FPGA is connected to the non-volatile memory via a data line and is used to read and write data to the non-volatile memory. The non-volatile memory has two, three, or four or more storage areas. Each time data is written to the non-volatile memory, the FPGA selects the storage area to be written to according to a set rule, wherein the set rule is that the selected storage area is different from the storage area written to previously.

[0008] Furthermore, the setting rules also include: sorting each storage area, selecting the storage area according to the sorted order each time data is written, and if the previous data was written in the last storage area, then the current data is selected starting from the first storage area, and so on, writing data in each storage area in a loop.

[0009] Furthermore, the processor and FPGA are integrated on a single SOC chip. Both the processor and the FPGA can directly access the memory of the embedded electronic device. The system includes an uncache memory area shared by the FPGA and allocated by the processor. The processor is used to read and write data from the uncache memory area and issue read and write instructions to the FPGA. The FPGA is used to receive the read and write instructions issued by the processor. When a read instruction is received, data is read from non-volatile memory into the uncache memory area. When a write instruction is received, data is moved from the uncache memory area into non-volatile memory.

[0010] Furthermore, the uncache memory region includes at least two storage areas, one of which is used for write operations and the remaining storage area is used for read operations.

[0011] Furthermore, the processor is used to encapsulate data according to a set data frame format and write it into the uncache memory area, and the FPGA is used to read the data frame from the uncache memory area, calculate the CRC check code, and append it to the data frame.

[0012] The beneficial effects of the system of this invention are as follows: after the processor updates the data, it writes the data to the non-volatile memory through the FPGA to prevent the loss of running data when the device loses power. This application adopts a fault-tolerant mechanism for possible data transmission errors each time data is written to the non-volatile memory. That is, the storage area written each time is different. In this way, even if an abnormal power failure occurs when writing data to the current storage area, causing the data in the current storage area to be abnormal, the latest correct data can be selected from the most recently stored data in other storage areas. This ensures that the device can obtain the time-sensitive non-volatile data before the power failure after the abnormal power failure restarts, thus ensuring the integrity of the system data.

[0013] The embedded electronic device provided by this invention to solve the above-mentioned technical problems includes a power supply circuit and a non-volatile data storage system. The power supply circuit includes a power supply for powering the non-volatile data storage system. The non-volatile data storage system includes a processor, an FPGA, and a non-volatile memory. The processor is communicatively connected to the FPGA and is used to issue read and write commands to the FPGA. The FPGA is connected to the non-volatile memory via a data line and is used to read and write data to the non-volatile memory. The non-volatile memory has two, three, or four or more storage areas. The FPGA is used to select the storage area to be written to each time it writes data to the non-volatile memory according to a set rule, wherein the set rule is that the storage area selected this time is different from the storage area written in the previous time.

[0014] Furthermore, the setting rules also include: sorting each storage area, selecting the storage area according to the sorted order each time data is written, and if the previous data was written in the last storage area, then the current data is selected starting from the first storage area, and so on, writing data in each storage area in a loop.

[0015] Furthermore, the processor and FPGA are integrated on a single SOC chip. Both the processor and the FPGA can directly access the memory of the embedded electronic device. The non-volatile data storage system includes an uncache memory area shared with the FPGA, which is allocated by the processor. The processor is used to read and write data from the uncache memory area and issue read and write instructions to the FPGA. The FPGA is used to receive the read and write instructions issued by the processor. When a read instruction is received, data is read from the non-volatile memory into the uncache memory area. When a write instruction is received, data is moved from the uncache memory area into the non-volatile memory.

[0016] Furthermore, the processor is used to encapsulate data according to a set data frame format and write it into the uncache memory area, and the FPGA is used to read the data frame from the uncache memory area, calculate the CRC check code, and append it to the data frame.

[0017] Furthermore, the power supply circuit also includes a capacitor, one end of which is connected to the power supply connection line between the power supply and the non-volatile data storage system, and the other end of which is grounded.

[0018] The beneficial effects of the device of the present invention are as follows: after the processor updates the data, it writes the data to the non-volatile memory through the FPGA to prevent the loss of running data when the device loses power. In this application, a fault-tolerant mechanism is adopted for possible data transmission errors each time data is written to the non-volatile memory. That is, the storage area written each time is different. In this way, even if an abnormal power failure occurs when writing data to the current storage area, causing the data in the current storage area to be abnormal, the latest correct data can be selected from the most recently stored data in other storage areas. This ensures that the device can obtain the time-sensitive non-volatile data before the power failure after the abnormal power failure restarts, thus ensuring the integrity of the system data. Attached Figure Description

[0019] Figure 1 This is an architecture diagram of the non-volatile data storage system of the embedded electronic device according to an embodiment of the present invention;

[0020] Figure 2 This is the data frame format for non-volatile data in this embodiment of the invention;

[0021] Figure 3 This is a flowchart of a processor writing non-volatile data according to an embodiment of the present invention;

[0022] Figure 4 This is a flowchart of a processor reading non-volatile data according to an embodiment of the present invention. Detailed Implementation

[0023] The specific embodiments of the present invention will be further described below with reference to the accompanying drawings.

[0024] The basic idea of ​​this invention is as follows: Although existing technologies utilize non-volatile memory to store processor operating data, the data is often stored in a single storage area. When the device experiences an abnormal power outage, the storage area where data is being written may be corrupted, resulting in data loss. To address this issue, this application sets up multiple storage areas in the non-volatile memory. During data writing, data is written alternately to different storage areas. In this way, each storage area stores time-sensitive non-volatile data. Even if the currently written storage area is corrupted during a power outage, the most recently stored correct data with time sensitivity can be retrieved from other storage areas. This ensures that the device can retrieve the time-sensitive non-volatile data from before the power outage after an abnormal power outage and restart, thus guaranteeing the integrity of the system data.

[0025] An embodiment of a non-volatile data storage system for an embedded electronic device

[0026] Based on the above basic ideas, such as Figure 1 As shown, the non-volatile data storage system of the embedded electronic device of the present invention includes a processor, an FPGA (Field-Orogrammable Gate Array), and non-volatile memory. The processor is communicatively connected to the FPGA and is used to issue read and write commands to the FPGA. The FPGA is connected to the non-volatile memory via a data line and is used to read and write data to the non-volatile memory. The non-volatile memory has two, three, or four or more storage areas. Each time data is written to the non-volatile memory, the FPGA selects the storage area to be written to according to a set rule, which is that the selected storage area is different from the storage area written to in the previous write. Among them, the FPGA, as the key bridge between the CPU and the non-volatile memory, plays a core role in data transmission and coordination. It maintains close communication with the non-volatile memory through the SPI bus to ensure accurate data transmission. During the processor driver initialization phase, the non-volatile memory is indirectly initialized by configuring the registers provided by the FPGA, laying a solid foundation for subsequent data operations. The number of storage areas in the non-volatile memory should not be too many, generally set to 2 to 5.

[0027] Preferably, to improve the reliability of acquiring time-sensitive non-volatile data prior to power failure, this invention further improves the setting rules. Specifically, each storage area stores time-sensitive non-volatile data. This is achieved by sorting the storage areas and selecting them according to their order each time data is written. If data was previously written to the last storage area, the selection process starts from the first storage area, and so on, writing data cyclically through all storage areas. For example, if the non-volatile memory has four reserved storage areas: storage area 1, storage area 2, storage area 3, and storage area 4, and the order of data writing is storage area 1, storage area 2, storage area 3, and storage area 4, then if the previous write was to storage area 4, the next write will be to storage area 1, the next write will be to storage area 2, and so on, cyclically writing data through all four storage areas.

[0028] For embedded devices where the processor and FPGA are integrated on a single System-on-a-Chip (SoC), such as devices using the ZYNQ7000 chip, both the processor and FPGA can directly access the embedded device's memory. The processor is responsible for allocating a shared uncache memory area (uncache memory refers to memory that can directly store data without caching) with the FPGA. This shared uncache memory area will be referred to as shared memory. The processor reads and writes data from the shared memory and issues read / write commands to the FPGA. The FPGA receives these commands from the CPU and is responsible for moving data from non-volatile memory to the shared memory, or vice versa. Using shared memory to implement data caching allows for the pre-packaging of non-volatile data to be stored, ensuring timely storage in the non-volatile memory when the FPGA can read or write data. The processor in this context is the CPU.

[0029] Preferably, the shared memory includes at least two storage areas, one of which is dedicated to write operations and the remaining storage areas are used for read operations.

[0030] For non-volatile data that needs to be stored, data encapsulation processing is required during storage. Regarding the format of the encapsulated data frames, the processor strictly adheres to specific standards, such as... Figure 2As shown, each data frame consists of four parts, from the beginning: a data length area, a sequence number area, a data area, and a check area. The data length area is used to write the length of the data, i.e., to identify the length of the data being written; the sequence number area is used to write the sequence number, which identifies the order of the data; the data area is used to store the actual data content; and the check area is used to store the calculated checksum. In this embodiment, the checksum is calculated by the FPGA after the data transfer is complete and appended to the check area. The checksum used in this embodiment is a CRC checksum.

[0031] In this embodiment, the FPGA calculates the checksum because if the CPU communicates directly with the non-volatile memory via the SPI bus, the CRC checksum calculation would consume a significant amount of CPU resources, impacting performance, especially at high data update frequencies (e.g., once every 15ms). Therefore, the storage system in this embodiment, when frequently updating small batches (32KB) of data, can ensure the accuracy and integrity of the system's non-volatile data after power failure without consuming excessive CPU processing time, thus guaranteeing consistency after the device is powered on again.

[0032] Based on the aforementioned non-volatile data storage system, the processor's data read / write process is as follows: Figure 3 , 4 As shown. For write operations, as... Figure 3 As shown, the processor first checks if the FPGA is currently in a busy state (i.e., whether it is performing read / write operations with non-volatile memory). When the FPGA is busy, its busy flag in its status register is set to 1. By checking if the busy flag in the FPGA's status register is 1, it can be determined that the FPGA is performing a data read / write operation. If it is busy, the current write operation fails; otherwise, the processor copies the data, which includes the data length area, sequence number area, and data area, to the write operation storage area of ​​the shared memory and sends a write command to the FPGA, instructing the FPGA to move the data to the non-volatile memory. After receiving the write command from the CPU, the FPGA sets the busy flag in its status register to 1. Subsequently, the FPGA efficiently moves the data from the write operation storage area to the designated storage area of ​​the non-volatile memory via the SPI bus. To ensure data integrity and accuracy, the FPGA calculates a CRC checksum after the data is moved and adds it to the checksum area of ​​the data frame. Once the data write operation is complete, the FPGA sets the busy flag to 0 and sets the completion flag to 1, notifying the processor that the data has been successfully written.

[0033] For read operations, such as Figure 4As shown, the processor first checks if the FPGA is currently busy. If busy, it periodically checks until the FPGA exits the busy state. Then, the processor sends a read command to the FPGA, waiting for the FPGA to read data from the non-volatile memory and move it to the read operation storage area of ​​the shared memory. Upon receiving the read command, the FPGA sets the busy flag in its status register to 1. Subsequently, the FPGA requests data from the specified storage area of ​​the non-volatile memory and quickly writes the read data to the read operation storage area of ​​the shared memory. To ensure data continuity and consistency, the FPGA sets the busy flag to 0 and the completion flag to 1 after the data is written. This allows the processor to promptly retrieve the required data from the shared memory. After retrieving the data from the shared memory, the processor verifies the CRC of the data stored in each storage area of ​​the non-volatile memory and selects the latest and correct data block based on the sequence number to return to the application. It should be noted that since the device typically only needs to read data from the non-volatile memory upon power-up, CRC checks are not performed frequently, thus avoiding unnecessary performance overhead.

[0034] Preferably, the non-volatile memory in this embodiment is NVRAM (Non-Volatile Random Access Memory). NVRAM internally integrates RAM and FLASH areas, supporting two data storage modes: hard STORE (data is moved from RAM to FLASH when power is lost) and soft STORE (data is moved from RAM to FLASH when an instruction is received). The driver should enable hard STORE during initialization. When the FPGA transmits data to the NVRAM, it first stores the data in the RAM area, and then refreshes the RAM data to the FLASH area upon receiving a soft STORE instruction or upon power loss. When the FPGA reads data from the NVRAM, it first moves the data from the FLASH area to the RAM area, and then sends the data back to the FPGA via the SPI bus.

[0035] Preferably, to meet the storage requirement of a maximum of 32KB of non-volatile data, this embodiment allocates a shared uncache memory space of 32KB*5 for the processor and FPGA. One memory space (32KB) is dedicated to write operations, while the remaining four memory spaces (32KB*4) are used for read operations. Simultaneously, a corresponding 32KB*4 storage area is reserved in NVRAM; during data writing, data is cyclically overwritten in these four storage areas. Regarding the data frame format, such as... Figure 2As shown, each data frame begins with two bytes to identify the length of the data being written; the next two bytes store a sequence number to identify the data order; followed by a 32KB minus 8-byte data area to store the actual data content; and the last four bytes are appended by the FPGA with a CRC checksum after data transfer is complete. Using CRC checksum, erroneous data blocks during transmission can be detected promptly when reading data. By cyclically overwriting the four storage areas of the non-volatile memory, the latest correct data can be selected from the four most recently stored data (one data per storage area). Therefore, the fault tolerance mechanism of this invention allows for the reading of time-sensitive data even after a data transmission failure.

[0036] An embodiment of an embedded electronic device

[0037] Based on the above basic ideas, the embedded electronic device in this embodiment includes a power supply circuit and a non-volatile data storage system. The power supply circuit includes a power supply, which is used to power the non-volatile data storage system. The non-volatile data storage system adopts the non-volatile data storage system in the above embodiment, which will not be described in detail here.

[0038] To ensure that data such as the device's current operating status can be saved to non-volatile memory after a sudden power outage, this embodiment adds a capacitor to the power supply circuit of the non-volatile data storage system. Specifically, one end of the capacitor is connected to the power supply line between the power supply and the non-volatile data storage system, and the other end is grounded. By setting this capacitor, it is ensured that the device can complete one data storage operation after detecting a power failure.

[0039] In application scenarios where frequent updates of non-volatile data are required, the embedded electronic device and its non-volatile data storage system of the present invention, through the collaborative work of FPGA, non-volatile memory and processor, can ensure that the device can obtain timely non-volatile data before the power failure after an abnormal power failure and restart without occupying too much processor processing time.

Claims

1. A non-volatile data storage system for an embedded electronic device, characterized in that, The system includes a processor, an FPGA, and a non-volatile memory. The processor is communicatively connected to the FPGA and is used to issue read and write commands to the FPGA. The FPGA is connected to the non-volatile memory via a data line and is used to read and write data to the non-volatile memory. The non-volatile memory has two, three, or four or more storage areas. Each time the FPGA writes data to the non-volatile memory, it selects the storage area to be written to according to a set rule, wherein the set rule is that the storage area selected this time is different from the storage area written in the previous time.

2. The non-volatile data storage system for embedded electronic devices according to claim 1, characterized in that, The setting rules also include: sorting each storage area, selecting the storage area according to the sorted order each time data is written, and if the previous data was written in the last storage area, then the current data is selected starting from the first storage area, and so on, writing data in each storage area in a loop.

3. The non-volatile data storage system for an embedded electronic device according to claim 1, characterized in that, The processor and FPGA are integrated on a single SOC chip. Both the processor and the FPGA can directly access the memory of the embedded electronic device. The system includes an uncache memory area shared by the FPGA and allocated by the processor. The processor is used to read and write data from the uncache memory area and issue read and write instructions to the FPGA. The FPGA is used to receive read and write instructions issued by the processor. When a read instruction is received, data is read from non-volatile memory into the uncache memory area. When a write instruction is received, data is moved from the uncache memory area into non-volatile memory.

4. The non-volatile data storage system for an embedded electronic device according to claim 3, characterized in that, The uncache memory region includes at least two storage areas, one of which is used for write operations and the remaining storage area is used for read operations.

5. The non-volatile data storage system for an embedded electronic device according to claim 3, characterized in that, The processor is used to encapsulate data according to a set data frame format and write it into the uncache memory area. The FPGA is used to read the data frame from the uncache memory area, calculate the CRC check code, and append it to the data frame.

6. An embedded electronic device, characterized in that, The device includes a power supply circuit and a non-volatile data storage system. The power supply circuit includes a power supply for powering the non-volatile data storage system. The non-volatile data storage system includes a processor, an FPGA, and a non-volatile memory. The processor is communicatively connected to the FPGA and is used to issue read and write commands to the FPGA. The FPGA is connected to the non-volatile memory via a data line and is used to read and write data to the non-volatile memory. The non-volatile memory has two, three, or four or more storage areas. Each time the FPGA writes data to the non-volatile memory, it selects the storage area to be written to according to a set rule, wherein the set rule is that the selected storage area is different from the storage area written to in the previous write operation.

7. The embedded electronic device according to claim 6, characterized in that, The setting rules also include: sorting each storage area, selecting the storage area according to the sorted order each time data is written, and if the previous data was written in the last storage area, then the current data is selected starting from the first storage area, and so on, writing data in each storage area in a loop.

8. The embedded electronic device according to claim 6, characterized in that, The processor and FPGA are integrated on a single SOC chip. Both the processor and the FPGA can directly access the memory of the embedded electronic device. The non-volatile data storage system includes an uncache memory area shared by the FPGA and allocated by the processor. The processor is used to read and write data from the uncache memory area and issue read and write instructions to the FPGA. The FPGA is used to receive read and write instructions issued by the processor. When a read instruction is received, data is read from the non-volatile memory into the uncache memory area. When a write instruction is received, data is moved from the uncache memory area into the non-volatile memory.

9. The embedded electronic device according to claim 8, characterized in that, The processor is used to encapsulate data according to a set data frame format and write it into the uncache memory area. The FPGA is used to read the data frame from the uncache memory area, calculate the CRC check code, and append it to the data frame.

10. The embedded electronic device according to any one of claims 6 to 9, characterized in that, The power supply circuit also includes a capacitor, one end of which is connected to the power supply connection line between the power supply and the non-volatile data storage system, and the other end of which is grounded.

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