Chip verification method, system and device and storage medium

Abstract

The embodiment of the invention provides a chip verification method, system and device and a storage medium, a chip comprises a core particle group, the core particle group is formed by coupling a plurality of core particles, and the method comprises the following steps: based on a core particle verification environment, performing a verification test on a to-be-tested designed core particle; after the core particles pass the verification test, a core particle group verification environment is generated, the core particle group verification environment comprises a plurality of core particle verification sub-environments, and the core particle verification sub-environments are obtained based on instantiation of the core particle verification environment; and based on the core particle group verification environment, carrying out verification test on a to-be-tested designed core particle group. According to the chip verification method in the embodiment of the invention, complete verification of the core particle group can be realized.

Description

Technical Field

[0001] This application relates to the field of chip technology, specifically to a chip verification method, system, device, and storage medium. Background Technology

[0002] In chip manufacturing, complete electronic system functions (CPU cores, cache, I / O interfaces, etc.) are typically integrated onto a single silicon die. These are then packaged to form chips, such as GPUs (Graphics Processing Units), GPGPUs (General-purpose computing on graphics processing units), and CPUs (Central Processing Units). With technological advancements, to meet higher computing power demands, chiplets have emerged, integrating multiple chips together based on specific architectures and packaging techniques. This technology overcomes the bottlenecks of single-chip design and process limitations, providing significantly stronger computing resources.

[0003] However, how to implement verification testing of chip assemblies during the chip design phase is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] In view of this, embodiments of this application provide a chip verification method, system, device, and storage medium to achieve verification testing of chip assemblies.

[0005] To achieve the above objectives, the embodiments of this application provide the following technical solutions.

[0006] In a first aspect, embodiments of this application provide a chip verification method, wherein the chip includes a chip assembly, the chip assembly being composed of multiple chips coupled together, and the method includes: Based on the chip verification environment, the chip of the design under test is verified and tested. After the core passes the verification test, a core group verification environment is generated, wherein the core group verification environment includes multiple core verification sub-environments, and the core verification sub-environments are instantiated based on the core verification environment; Based on the chip assembly verification environment, the chip assembly of the design under test is verified and tested.

[0007] Optionally, the generated core assembly verification environment includes: Generate the initial core assembly verification environment; The chip verification environment is instantiated to the initial chip group verification environment to form a chip verification sub-environment within the initial chip group verification environment. Configure a bus interaction module for the core particle verification sub-environment, and use the initial core particle group verification environment configured with the bus interaction module as the core particle group verification environment. The bus interaction module is used to verify the data interaction between multiple core particles within the test core particle group.

[0008] Optionally, in the step of instantiating the chip verification environment to the initial chip group verification environment, the chip verification environment instantiated in the initial chip group verification environment corresponds one-to-one with multiple chips in the chip group.

[0009] Optionally, in the step of configuring the bus interaction module for the chip verification sub-environment, the bus interaction module includes: a reference model interaction processing unit and a design under test interaction processing unit; The design under test (DUT) interaction processing unit is used to: acquire interaction request information from the chip transmitter in the DUT, and send the interaction request information to the chip receiver based on the indication of the interaction request information. The chip transmitter is the chip that generates and sends the interaction request information, and the chip receiver is the chip that receives the interaction request information. The interaction request information includes indication information from the chip transmitter and the chip receiver. The reference model interaction processing unit is used to: obtain reference interaction request information of the corresponding chip verification sub-environment of the chip transmitter, and send the reference interaction request information to the chip verification sub-environment corresponding to the chip receiver based on the indication of the interaction request information, wherein the reference interaction request information includes the chip verification sub-environment of the corresponding chip transmitter and the indication information of the chip verification sub-environment of the corresponding chip receiver.

[0010] Optionally, after generating the initial chip group verification environment, and before instantiating the chip verification environment to the initial chip group verification environment, the method further includes: A reference model interaction module is configured within the core verification sub-environment. The reference model interaction module is used to interact with the reference model to obtain the reference interaction request information.

[0011] Optionally, in the step of configuring the reference model interaction module within the chip verification sub-environment, the reference model interaction module includes a reference model interaction input component and a reference model interaction output component; the reference model interaction input component is used to send the reference interaction request information to the reference model, and the reference model interaction output component is used to obtain the reference interaction request information from the reference model.

[0012] Optionally, the chip verification environment includes: a reference model and a test analysis module; the verification test of the chip of the design under test based on the chip verification environment includes: The test analysis module sends test stimuli to the core of the design under test and its corresponding reference model; The test analysis module obtains the output information corresponding to the test stimulus from the core and the corresponding reference model; The test analysis module determines whether the output information obtained by the core particle and its corresponding reference model matches; wherein, when the output information of the core particle and its corresponding reference model match, the output information of the core particle is accurate, and the core particle passes the verification test.

[0013] Optionally, the verification test of the chip to be tested based on the chip verification environment further includes: The test analysis module determines whether there is return data in the output information; if so, the test analysis module writes the return data back to the sender of the output information and determines whether the return information obtained from the chip and the corresponding reference model match. Specifically, when the returned information of the core particle and its corresponding reference model match, the returned information of the core particle is accurate, and the core particle passes the verification test.

[0014] Secondly, embodiments of this application also provide a chip verification system, wherein the chip includes a chip assembly, the chip assembly being composed of multiple chips coupled together, and the chip verification system includes: A chip verification environment is used to verify and test the chips of the design under test. A chip group verification environment, comprising multiple chip verification sub-environments, which are instantiated based on the chip verification environment and used to verify and test the chip group of the design under test.

[0015] Optionally, the core assembly verification environment is configured with a bus interaction module, which is used to verify the data interaction between multiple cores within the test core assembly.

[0016] Optionally, the bus interaction module includes: a reference model interaction processing unit and a design under test interaction processing unit; The design under test (DUT) interaction processing unit is used to: acquire interaction request information from the chip transmitter in the DUT, and send the interaction request information to the chip receiver based on the indication of the interaction request information. The chip transmitter is the chip that generates and sends the interaction request information, and the chip receiver is the chip that receives the interaction request information. The interaction request information includes indication information from the chip transmitter and the chip receiver. The reference model interaction processing unit is used to: obtain reference interaction request information of the corresponding chip verification sub-environment of the chip transmitter, and send the reference interaction request information to the chip verification sub-environment corresponding to the chip receiver based on the indication of the interaction request information, wherein the reference interaction request information includes the chip verification sub-environment of the corresponding chip transmitter and the indication information of the chip verification sub-environment of the corresponding chip receiver.

[0017] Optionally, the chip verification sub-environment is configured with a reference model interaction module, which is used to interact with the reference model to obtain the reference interaction request information. The reference model interaction module includes a reference model interaction input component and a reference model interaction output component; the reference model interaction input component is used to send the reference interaction request information to the reference model, and the reference model interaction output component is used to obtain the reference interaction request information from the reference model.

[0018] Optionally, the chip verification environment includes: a reference model and a test analysis module; The test analysis module includes: a scoreboard, an input verification component, an output verification component, a return data verification component, a reference model request processing unit, and a design under test request processing unit; The input verification component is used to send test stimuli to the cores in the design under test (DUT) and send the same test stimuli to the reference model. The output verification component is used to receive the output information of the cores in the DUT and send it to the DUT request processing unit and the scoring board. The reference model sends the generated output information to the reference model request processing unit and the scoring board. The scoring board is used to compare the output information after receiving the output information from the cores in the DUT and the reference model to verify whether the logic of the DUT is accurate.

[0019] Optionally, the reference model request processing unit is further configured to determine whether there is return data in the output information after obtaining the output information corresponding to the test stimulus; if so, write the return data back to the reference model and the scoring board. The design under test request processing unit is also used to determine whether there is return data in the output information after obtaining the output information corresponding to the test stimulus; if so, write the return data back to the core and the scoring board in the design under test. The scoring board is also used to compare the returned information after receiving the return information from the reference model request processing unit and the design under test request processing unit, so as to verify whether the logic of the design under test is accurate.

[0020] Thirdly, this application also provides a chip verification device, which is equipped with the chip verification system provided in this application.

[0021] Fourthly, embodiments of this application also provide a storage medium storing loading data of the chip verification system provided in embodiments of this application.

[0022] The chip verification method, system, device, and storage medium provided in this application embodiment include a chip group comprising multiple coupled chips. The method includes: performing verification tests on chips designed under test based on a chip verification environment; generating a chip group verification environment after the chips pass the verification tests, wherein the chip group verification environment includes multiple chip verification sub-environments instantiated based on the chip verification environment; and performing verification tests on the chip group designed under test based on the chip group verification environment.

[0023] As can be seen, the chip verification method in this application embodiment verifies and tests the chips of the design under test through a chip verification environment, and further verifies and tests the chip group using a chip group verification environment instantiated based on the chip verification environment. While realizing the verification and testing of the chip group, it also verifies and tests the chips in the chip group, thereby realizing the complete verification of the chip group. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0025] Figure 1 This is a structural example diagram of a core assembly; Figure 2 A schematic diagram of an optional process for the chip verification method provided in an embodiment of this application; Figure 3 An optional structural diagram of the chip verification environment provided in the embodiments of this application; Figure 4 A schematic diagram of an optional process for step S100 provided in an embodiment of this application; Figure 5 Another optional flowchart of step S100 provided in the embodiments of this application; Figure 6 Another optional flowchart of step S100 provided in the embodiments of this application; Figure 7A schematic diagram of an optional process for step S110 provided in an embodiment of this application; Figure 8 An optional structural diagram of the chip assembly verification environment provided in the embodiments of this application; Figure 9 Another optional flowchart of step S110 provided in the embodiments of this application; Figure 10 This is an optional structural diagram of the chip verification system provided in an embodiment of this application. Detailed Implementation

[0026] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0027] In one alternative implementation, Figure 1 An exemplary structural diagram of a core assembly is shown. (Reference) Figure 1 The core group may include multiple cores (Core0, Core1, ..., CoreN) coupled via a bus (shown as Intersection Bus in the figure). Each core can be a single GPU core, a single GPGPU core, a single CPU core, a single memory core, etc. Furthermore, within the core group, the multiple cores can be homogeneous; for example, multiple single GPGPU cores can constitute a GPGPU core group, thus forming a single GPGPU device to implement GPGPU functionality. In other examples, the multiple cores can also be heterogeneous, and the functions corresponding to the cores can be the same or different; this application does not impose specific limitations here.

[0028] Among the existing chip verification methods, there are only chip verification environments for individual chips, and no verification and testing schemes for chip groups. Therefore, how to achieve complete verification and testing of chip groups during the chip design stage has become an urgent problem to be solved by those skilled in the art.

[0029] The inventors believe that it is possible to build a verification environment for the chip assembly based on the chip verification environment, thereby realizing the verification testing of the chip assembly.

[0030] In view of this, embodiments of this application provide a chip verification method, system, device, and storage medium. The chip includes a chip group, which is composed of multiple chips coupled together. The method includes: performing verification tests on the chips of the design under test based on a chip verification environment; generating a chip group verification environment after the chips pass the verification tests, wherein the chip group verification environment includes multiple chip verification sub-environments, which are instantiated based on the chip verification environment; and performing verification tests on the chip group of the design under test based on the chip group verification environment.

[0031] As can be seen, the chip verification method in this application embodiment verifies and tests the chips of the design under test through a chip verification environment, and further verifies and tests the chip group using a chip group verification environment instantiated based on the chip verification environment. While realizing the verification and testing of the chip group, it also verifies and tests the chips in the chip group, thereby realizing the complete verification of the chip group.

[0032] The chip verification scheme provided in the embodiments of this application will now be described in detail.

[0033] In one alternative implementation, refer to Figure 2 The illustrated schematic diagram shows an optional process for chip verification. The chip verification method provided in this application embodiment may include: Step S100: Based on the chip verification environment, perform verification tests on the chip of the design under test; Understandably, the design under test is first validated by performing verification tests on the core of the design under test in order to achieve full validation of the design under test.

[0034] In the specific implementation, refer to Figure 3 The diagram shows an optional architecture for a chip verification environment, which may include a reference model (Ref_Model) and a test analysis module.

[0035] The reference model is the logic model of the corresponding core in the design under test. It is used to provide the same logic as the core, so as to determine whether the output information of the core is accurate based on the output information of the reference model, and then to infer whether the logic inside the core is accurate.

[0036] The test analysis module provides test stimuli and test result analysis in the chip verification environment. In optional implementations, the test analysis module may include: a scoreboard, an input verification component (Req_in UVC), an output verification component (Req_out UVC), a return data verification component (Rtn_data UVC), a reference model request processing unit (Req_handler Ref), and a design-under-test request processing unit (Req_handler Dut).

[0037] In specific examples, refer to Figure 4 The illustrated optional flow diagram for step S100 shows that the chip in the design under test can be a DUT Core. The verification test of the chip in this step may include: Step S101: The test analysis module sends test stimuli to the core of the design under test and its corresponding reference model; The test stimulus is an excitation signal used to verify the core. By sending the test stimulus, the core of the design under test and the corresponding reference model of the core can react based on the test stimulus, and then feed back the corresponding output information.

[0038] In a specific example, Req_in UVC can send test stimuli to the DUT Core and the same test stimuli to the Ref Model. A monitor can be configured in Req_in UVC to control the sending of test stimuli to the Ref Model.

[0039] Step S102: The test analysis module obtains the output information corresponding to the test stimulus from the core and the corresponding reference model; By acquiring the output information of the core and the corresponding output information of the reference model, the matching of the output information can be verified.

[0040] In this specific example, the DUT Core and Ref Model generate corresponding output information based on the test stimuli. The Reqout UVC can receive the output information from the DUT Core and send it to the Req_handler Dut and the Scoreboard. The RefModel then sends the generated output information to the Req_handler Ref and the Scoreboard.

[0041] Step S103: The test analysis module determines whether the output information obtained from the core and the corresponding reference model match; By determining whether the output information obtained from the core and its corresponding reference model matches, we can determine whether the output information of the core is accurate, and then inversely determine whether the logic within the core is accurate, thus determining whether the core passes the verification test.

[0042] It is understood that when the output information of a core component matches that of its corresponding reference model, the core component's output information is considered accurate, and consequently, the logic within the core component is accurate, thus the core component passes the verification test. Here, "output information matching" means that the information result indicated in the output information is consistent with the information content.

[0043] In a specific example, after receiving the output information from the DUT Core and Ref Model, the Scoreboard can compare the output information to verify whether the logic of the design under test is accurate.

[0044] In further optional examples, this step can also further process and provide feedback on the content of the output information. For details, refer to... Figure 5 Another optional flowchart for step S100 may be provided, which may further include: Step S104: The test analysis module determines whether there is returned data in the output information; The returned data is used to indicate the data information that needs to be returned. Specifically, when output information is emitted from the core, the corresponding returned data is used to return to the core; when input information is emitted from the reference model, the corresponding returned data is used to return to the reference model.

[0045] If so, then step S105 is executed to write the returned data back to the sender of the output information; otherwise, the process is handled according to the normal procedure.

[0046] In a specific example, the Req_handler Ref and Req_handler Dut of the chip verification environment can execute this step for the reference model and the design under test, respectively, after obtaining the output information corresponding to the test stimulus. Specifically, Req_handler Ref and Req_handler Dut can determine whether there is returned data in the output information; if so, step S105 is executed.

[0047] It should be noted that steps S104 and S103 can be understood as parallel processing steps, used to perform different processing on the output information at the same time, so as to realize data verification testing while ensuring the data processing flow.

[0048] Step S105: The test analysis module writes the returned data back to the sender of the output information; In the specific implementation, Req_handler Ref can write the returned data back to the Ref Model, while Req_handlerDut writes the returned data back to the DUT Core.

[0049] In a further optional implementation, the chip verification environment can further evaluate the returned data to determine whether the returned information obtained from the chip and its corresponding reference model matches. Specifically, refer to... Figure 6 Another optional flowchart for step S100 is shown below. In step S104, if the output information contains return data, the following steps can be performed simultaneously with step S105: Step S106: The test analysis module determines whether the returned information obtained from the core chip and the corresponding reference model match; By determining whether the returned information obtained from the core and its corresponding reference model match, we can determine whether the core's returned information is accurate. This allows us to infer whether the logic within the core is accurate and whether the core passes the verification test.

[0050] It is understood that when the returned information of the core and its corresponding reference model matches, the returned information of the core is considered accurate, and correspondingly, the logic within the core is accurate, and the core passes the verification test. Here, "return information matching" means that the information result indicated in the returned information is consistent with the information content.

[0051] In the specific implementation, Req_handler Ref and Req_handler Dut can write the returned data back to Scoreboard respectively. After receiving the returned information from Req_handler Ref and Req_handler Dut, Scoreboard compares the returned information to verify whether the logic of the design under test is accurate.

[0052] It should be noted that when step S106 exists, both the conditions in step S103 and the conditions in step S106 must be met simultaneously to arrive at the conclusion that the chip has passed the verification. In other words, the chip can be considered to have passed the verification test only when both the judgment result in step S103 and the judgment result in step S106 are yes.

[0053] After the core passes the verification test, the subsequent step S110 can be performed.

[0054] refer to Figure 2 Continue with step S110: Generate the chip assembly verification environment; The chip group verification environment includes multiple chip verification sub-environments, which are instantiated based on the chip verification environment. Instantiating the chip verification environment based on the chip verification sub-environments reduces the complexity of constructing the chip group verification environment, thereby lowering costs.

[0055] In the optional implementation, refer to Figure 7 The optional flowchart of step S110 is shown below. Step S110 may include: Step S111: Generate the initial core assembly verification environment; The initial chip group verification environment can be understood as the initial framework of the chip group verification environment, which is used to provide a foundation for the subsequent instantiation of the chip verification environment.

[0056] Step S112: Instantiate the chip verification environment to the initial chip group verification environment to form a chip verification sub-environment within the initial chip group verification environment; After generating the initial chip group verification environment, the instantiation process in this step can be executed to form a chip verification sub-environment within the initial chip group verification environment.

[0057] It should be noted that the core group is composed of multiple cores coupled together. Correspondingly, the initial core group verification environment can instantiate a core verification environment corresponding to the multiple cores. That is, the core verification environment instantiated in the initial core group verification environment corresponds one-to-one with the multiple cores in the core group, thereby realizing the correspondence between the core and the core verification sub-environment in the subsequently formed core group verification environment, and thus realizing the corresponding verification and complete verification of the multiple cores configured in the core group.

[0058] Step S113: Configure the bus interaction module for the chip verification sub-environment, and use the initial chip group verification environment configured with the bus interaction module as the chip group verification environment; The bus interaction module is used to verify the data interaction between multiple cores within the test core group.

[0059] In the optional implementation, refer to Figure 8The illustrated optional structure diagram of the chip group verification environment shows that the bus interaction module may include: a reference model interaction processing unit (Interconnection Bus Handler Ref) and a design-under-test (DUT) interaction processing unit (Interconnection Bus Handler DUT). The reference model interaction processing unit is used to verify the interaction information of reference interaction requests from reference models in multiple chip verification sub-environments, while the DUT interaction processing unit is used to verify the interaction information of interaction requests from the design-under-test. The reference model interaction processing unit can be configured among the chip verification sub-environments, and the DUT interaction processing unit can be configured among the chip verification sub-environments or connected to the design-under-test.

[0060] In a specific implementation, the design under test (DUT) interaction processing unit can obtain the interaction request information from the chip transmitter in the DUT, and send the interaction request information to the chip receiver based on the indication of the interaction request information. The chip transmitter is the chip that generates and sends the interaction request information, and the chip receiver is the chip that receives the interaction request information (an exemplary chip in the figure is labeled Core0 inst). The interaction request information includes indication information from the chip transmitter and the chip receiver, which may be, for example, a chip identifier (ID).

[0061] The reference model interaction processing unit can obtain reference interaction request information of the corresponding chip verification sub-environment of the chip transmitter, and send the reference interaction request information to the corresponding chip verification sub-environment of the chip receiver based on the indication of the interaction request information. The reference interaction request information includes the chip verification sub-environment of the corresponding chip transmitter and the indication information of the chip verification sub-environment of the corresponding chip receiver. The indication information may be, for example, a chip verification sub-environment identifier (ID).

[0062] The reference interaction request information is sent by the reference model in the corresponding chip verification sub-environment of the chip sender, and the reference interaction request information is sent to the reference model within the chip verification sub-environment of the chip receiver.

[0063] In further optional examples, refer to Figure 9 The illustrated alternative flowchart for step S110 also allows for configuring a reference model interaction module for the chip verification sub-environment. Specifically, after step S111 and before step S112, the following may be further included: Step S114: Configure the reference model interaction module within the chip verification sub-environment; The reference model interaction module is used to interact with the reference model and obtain the reference interaction request information.

[0064] In an optional implementation, the reference model interaction module may include a reference model interaction input component (Interconnection_req_in UVC) and a reference model interaction output component (Interconnection_req_outUVC); the reference model interaction input component is used to send the reference interaction request information to the reference model, and the reference model interaction output component is used to obtain the reference interaction request information from the reference model.

[0065] After generating the core assembly verification environment, the subsequent step S120 can be performed.

[0066] refer to Figure 2 Continue with step S120: Based on the chip assembly verification environment, perform verification testing on the chip assembly of the design to be tested.

[0067] After generating the chip assembly verification environment, the chip assembly of the design under test can be verified and tested.

[0068] It is understandable that the core verification sub-environment can be used to verify and test the cores within the core group, and the corresponding bus interaction module can be used to verify and test the information interaction within the core group.

[0069] In a further embodiment, this application provides a chip verification system, referring to... Figure 10 The diagram shows an optional structure of a chip verification system. The chip verification system targets a chip assembly, which is composed of multiple coupled chips. Figure 10 As shown, the chip verification system includes: a chip verification environment 200, which is used to verify and test the chips of the design under test; and a chip group verification environment 210, which includes multiple chip verification sub-environments, which are instantiated based on the chip verification environment and are used to verify and test the chip group of the design under test.

[0070] This involves multiple cores, multiple core verification environments, and multiple corresponding core verification sub-environments. Furthermore, there is a one-to-one correspondence between cores and their verification environments, as well as between cores and their verification sub-environments.

[0071] Optionally, the core assembly verification environment is configured with a bus interaction module, which is used to verify the data interaction between multiple cores within the test core assembly.

[0072] Optionally, the bus interaction module includes: a reference model interaction processing unit and a design under test interaction processing unit; The design under test (DUT) interaction processing unit is used to: acquire interaction request information from the chip transmitter in the DUT, and send the interaction request information to the chip receiver based on the indication of the interaction request information. The chip transmitter is the chip that generates and sends the interaction request information, and the chip receiver is the chip that receives the interaction request information. The interaction request information includes indication information from the chip transmitter and the chip receiver. The reference model interaction processing unit is used to: obtain reference interaction request information of the corresponding chip verification sub-environment of the chip transmitter, and send the reference interaction request information to the chip verification sub-environment corresponding to the chip receiver based on the indication of the interaction request information, wherein the reference interaction request information includes the chip verification sub-environment of the corresponding chip transmitter and the indication information of the chip verification sub-environment of the corresponding chip receiver.

[0073] Optionally, the chip verification sub-environment is configured with a reference model interaction module, which is used to interact with the reference model to obtain the reference interaction request information. The reference model interaction module includes a reference model interaction input component and a reference model interaction output component; the reference model interaction input component is used to send the reference interaction request information to the reference model, and the reference model interaction output component is used to obtain the reference interaction request information from the reference model.

[0074] Optionally, the chip verification environment includes: a reference model and a test analysis module; The test analysis module includes: a scoreboard, an input verification component, an output verification component, a return data verification component, a reference model request processing unit, and a design under test request processing unit; The input verification component is used to send test stimuli to the cores in the design under test (DUT) and send the same test stimuli to the reference model. The output verification component is used to receive the output information of the cores in the DUT and send it to the DUT request processing unit and the scoring board. The reference model sends the generated output information to the reference model request processing unit and the scoring board. The scoring board is used to compare the output information after receiving the output information from the cores in the DUT and the reference model to verify whether the logic of the DUT is accurate.

[0075] Optionally, the reference model request processing unit is further configured to determine whether there is return data in the output information after obtaining the output information corresponding to the test stimulus; if so, write the return data back to the reference model and the scoring board. The design under test request processing unit is also used to determine whether there is return data in the output information after obtaining the output information corresponding to the test stimulus; if so, write the return data back to the core and the scoring board in the design under test. The scoring board is also used to compare the returned information after receiving the return information from the reference model request processing unit and the design under test request processing unit, so as to verify whether the logic of the design under test is accurate.

[0076] This application also provides a chip verification device, which is equipped with the chip verification system provided in this application.

[0077] This application embodiment also provides a storage medium storing loading information of the chip verification system provided in this application embodiment. It is understood that, based on the loading information of the chip verification system, the chip verification system can be loaded into an electronic device that meets the hardware configuration requirements, thereby enabling the electronic device to function as a chip verification device and execute the corresponding chip verification process.

[0078] The foregoing describes multiple embodiment schemes provided by the embodiments of this application. The optional methods described in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending to a variety of possible embodiment schemes. These can all be considered as the embodiment schemes disclosed and published by the embodiments of this application.

[0079] While the embodiments disclosed above are described in this application, this application is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A chip verification method, characterized in that, The chip includes a chip assembly, the chip assembly being composed of multiple chips coupled together, the method comprising: Based on the chip verification environment, the chip of the design under test is verified and tested. After the core passes the verification test, a core group verification environment is generated, wherein the core group verification environment includes multiple core verification sub-environments, and the core verification sub-environments are instantiated based on the core verification environment; Based on the chip assembly verification environment, the chip assembly of the design under test is verified and tested.

2. The chip verification method according to claim 1, characterized in that, The generated core assembly verification environment includes: Generate the initial core assembly verification environment; The chip verification environment is instantiated to the initial chip group verification environment to form a chip verification sub-environment within the initial chip group verification environment. Configure a bus interaction module for the core particle verification sub-environment, and use the initial core particle group verification environment configured with the bus interaction module as the core particle group verification environment. The bus interaction module is used to verify the data interaction between multiple core particles within the test core particle group.

3. The chip verification method according to claim 2, characterized in that, In the step of instantiating the chip verification environment to the initial chip group verification environment, the chip verification environment instantiated in the initial chip group verification environment corresponds one-to-one with multiple chips in the chip group.

4. The chip verification method according to claim 2, characterized in that, In the step of configuring the bus interaction module for the chip verification sub-environment, the bus interaction module includes: a reference model interaction processing unit and a design under test interaction processing unit; The design under test (DUT) interaction processing unit is used to: acquire interaction request information from the chip transmitter in the DUT, and send the interaction request information to the chip receiver based on the indication of the interaction request information. The chip transmitter is the chip that generates and sends the interaction request information, and the chip receiver is the chip that receives the interaction request information. The interaction request information includes indication information from the chip transmitter and the chip receiver. The reference model interaction processing unit is used to: obtain reference interaction request information of the corresponding chip verification sub-environment of the chip transmitter, and send the reference interaction request information to the chip verification sub-environment corresponding to the chip receiver based on the indication of the interaction request information, wherein the reference interaction request information includes the chip verification sub-environment of the corresponding chip transmitter and the indication information of the chip verification sub-environment of the corresponding chip receiver.

5. The chip verification method according to claim 4, characterized in that, After generating the initial chip group verification environment, and before instantiating the chip verification environment to the initial chip group verification environment, the method further includes: A reference model interaction module is configured within the core verification sub-environment. The reference model interaction module is used to interact with the reference model to obtain the reference interaction request information.

6. The chip verification method according to claim 5, characterized in that, In the step of configuring the reference model interaction module in the core verification sub-environment, the reference model interaction module includes a reference model interaction input component and a reference model interaction output component. The reference model interaction input component is used to send the reference interaction request information to the reference model, and the reference model interaction output component is used to obtain the reference interaction request information from the reference model.

7. The chip verification method according to claim 1, characterized in that, The chip verification environment includes a reference model and a test analysis module; the verification test of the chip to be tested based on the chip verification environment includes: The test analysis module sends test stimuli to the core of the design under test and its corresponding reference model; The test analysis module obtains the output information corresponding to the test stimulus from the core and the corresponding reference model; The test analysis module determines whether the output information obtained by the core particle and its corresponding reference model matches; wherein, when the output information of the core particle and its corresponding reference model match, the output information of the core particle is accurate, and the core particle passes the verification test.

8. The chip verification method according to claim 7, characterized in that, The verification testing of the core component of the design under test based on the core component verification environment also includes: The test analysis module determines whether there is return data in the output information; if so, the test analysis module writes the return data back to the sender of the output information and determines whether the return information obtained from the chip and the corresponding reference model match. Specifically, when the returned information of the core particle and its corresponding reference model match, the returned information of the core particle is accurate, and the core particle passes the verification test.

9. A chip verification system, characterized in that, The chip includes a chip assembly, which is composed of multiple chips coupled together. The chip verification system includes: A chip verification environment is used to verify and test the chips of the design under test. A chip group verification environment, comprising multiple chip verification sub-environments, which are instantiated based on the chip verification environment and used to verify and test the chip group of the design under test.

10. The chip verification system according to claim 9, characterized in that, The core assembly verification environment is equipped with a bus interaction module, which is used to verify the data interaction between multiple cores within the test core assembly.

11. The chip verification system according to claim 10, characterized in that, The bus interaction module includes: a reference model interaction processing unit and a design-under-test interaction processing unit; The design under test (DUT) interaction processing unit is used to: acquire interaction request information from the chip transmitter in the DUT, and send the interaction request information to the chip receiver based on the indication of the interaction request information. The chip transmitter is the chip that generates and sends the interaction request information, and the chip receiver is the chip that receives the interaction request information. The interaction request information includes indication information from the chip transmitter and the chip receiver. The reference model interaction processing unit is used to: obtain reference interaction request information of the corresponding chip verification sub-environment of the chip transmitter, and send the reference interaction request information to the chip verification sub-environment corresponding to the chip receiver based on the indication of the interaction request information, wherein the reference interaction request information includes the chip verification sub-environment of the corresponding chip transmitter and the indication information of the chip verification sub-environment of the corresponding chip receiver.

12. The chip verification system according to claim 11, characterized in that, The core verification sub-environment is equipped with a reference model interaction module, which is used to interact with the reference model to obtain the reference interaction request information. The reference model interaction module includes a reference model interaction input component and a reference model interaction output component; the reference model interaction input component is used to send the reference interaction request information to the reference model, and the reference model interaction output component is used to obtain the reference interaction request information from the reference model.

13. The chip verification system according to claim 9, characterized in that, The chip verification environment includes: a reference model and a test analysis module; The test analysis module includes: a scoreboard, an input verification component, an output verification component, a return data verification component, a reference model request processing unit, and a design under test request processing unit; The input verification component is used to send test stimuli to the cores in the design under test (DUT) and send the same test stimuli to the reference model. The output verification component is used to receive the output information of the cores in the DUT and send it to the DUT request processing unit and the scoring board. The reference model sends the generated output information to the reference model request processing unit and the scoring board. The scoring board is used to compare the output information after receiving the output information from the cores in the DUT and the reference model to verify whether the logic of the DUT is accurate.

14. The chip verification system according to claim 13, characterized in that, The reference model request processing unit is further configured to determine whether there is return data in the output information after obtaining the output information corresponding to the test stimulus; if so, write the return data back to the reference model and the scoring board. The design under test request processing unit is also used to determine whether there is return data in the output information after obtaining the output information corresponding to the test stimulus; if so, write the return data back to the core and the scoring board in the design under test. The scoring board is also used to compare the returned information after receiving the return information from the reference model request processing unit and the design under test request processing unit, so as to verify whether the logic of the design under test is accurate.

15. A chip verification device, characterized in that, The chip verification device is equipped with a chip verification system as described in any one of claims 9-14.

16. A storage medium, characterized in that, The storage medium stores loading data for the chip verification system as described in any one of claims 9-14.

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