Cutting method of VCSEL laser chip and VCSEL laser chip
By forming a recessed area on the passivation layer and spin-coating a protective adhesive layer, the problem of insufficient adhesive adhesion during VCSEL chip dicing was solved, chip yield was improved, and efficient industrial production was achieved.
Patent Information
- Application Number
- CN202511774190.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-28
- Publication Date
- 2026-03-06
AI Technical Summary
In existing technologies, the adhesion between the protective adhesive and the chip surface is insufficient during the laser cutting process of VCSEL chips. This leads to the corrosion solution penetrating and damaging the functional layer of the chip during side etching, resulting in low product yield and failing to meet the requirements of industrial mass production.
Multiple recessed areas are formed on the passivation layer, and a protective adhesive layer is spin-coated on them so that the protective adhesive at least partially penetrates into the recessed areas. The substrate is exposed by vertical laser cutting, and the protective adhesive layer is retained on the sidewalls after cutting.
It improves the yield of VCSEL chips, prevents side corrosion abnormalities, and meets the yield requirements of over 90% for industrial mass production.
Smart Images
Figure CN121618312A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor laser technology, and in particular to a method for cutting a VCSEL laser chip and a VCSEL laser chip. Background Technology
[0002] In the manufacturing of Vertical-Cavity Surface-Emitting Laser (VCSEL) chips, laser cutting is a critical wafer separation process, but it generates sidewall residue that needs to be removed using a phosphoric acid mixed solution side etching process. The conventional processing flow includes film lamination, protective adhesive coating, baking, laser cutting, film expansion, side etching, and cleaning. Among these, the quality of the protective adhesive coating is crucial for chip surface protection. Especially in VCSEL chip manufacturing for data communication applications, existing technologies suffer from insufficient adhesion between the protective adhesive and the chip surface. The high temperatures of laser cutting can also damage this bond, leading to corrosion solution penetration during side etching, damaging the chip's functional layers. This results in a product yield of only 20%-30%, far below the industrial-scale production requirement of ≥90%, becoming a key bottleneck for the large-scale application of VCSEL chips in the data communication field.
[0003] Therefore, improving the dynamic characteristics of VCSEL is a pressing problem that needs to be solved. Summary of the Invention
[0004] Therefore, it is necessary to provide a method for cutting VCSEL laser chips and a VCSEL laser chip to address the above-mentioned technical problems.
[0005] In a first aspect, this application provides a method for cutting a VCSEL laser chip, the method comprising: A VCSEL laser chip is provided, the VCSEL laser chip comprising a substrate, a bottom mirror structure and an active layer stacked sequentially, a plurality of top mirror structures spaced apart on the active layer and a passivation layer in a channel between adjacent top mirror structures; The passivation layer is roughened to form multiple recessed areas on the passivation layer; A protective adhesive layer is spin-coated onto the roughened passivation layer, and the protective adhesive layer at least partially penetrates into the recessed area; A VCSEL laser chip coated with the protective adhesive layer is cut using a laser along a direction perpendicular to the channel to expose the substrate; wherein the protective adhesive layer is at least partially retained on the sidewalls of the cut VCSEL laser chip.
[0006] In one possible embodiment, the passivation layer is roughened to form a plurality of recessed regions on the passivation layer, including: The surface of the passivation layer is etched to form multiple recessed regions of varying depths on the passivation layer.
[0007] In one possible embodiment, the passivation layer is roughened to form a plurality of recessed regions on the passivation layer, including: The surface of the passivation layer is etched to form multiple recessed regions of equal depth on the passivation layer.
[0008] In one possible embodiment, the passivation layer is roughened to form a plurality of recessed regions on the passivation layer, including: The passivation layer is etched in the region near the top mirror structure to form multiple recessed regions of varying depths within the region.
[0009] In one possible embodiment, the passivation layer is etched in the region near the top mirror structure to form a plurality of recessed regions of varying depths within the region, including: The passivation layer is etched in the region near the top mirror structure to form a plurality of recessed regions of varying depths in the region, the depth of the recessed regions decreasing in the direction away from the top mirror structure.
[0010] In one possible embodiment, the passivation layer is etched in the region near the top mirror structure to form a plurality of recessed regions of varying depths within the region, including: The passivation layer is etched in the region near the top mirror structure to form a plurality of recessed regions of varying depths in the region, the depth of the recessed regions decreasing in the direction away from the top mirror structure.
[0011] In one possible embodiment, the number of recessed regions is three.
[0012] In one possible embodiment, the passivation layer is roughened to form a plurality of recessed regions on the passivation layer, including: The passivation layer is etched in the region near the top mirror structure to form a plurality of recessed regions of equal depth in the region.
[0013] In one possible embodiment, the gaps between adjacent recessed regions are unequal.
[0014] Secondly, this application also provides a VCSEL laser chip, the VCSEL laser chip comprising: Substrate; A bottom reflector structure is disposed on the substrate; An active layer is disposed on the bottom reflective mirror structure; Multiple top reflector structures are spaced apart on the active layer; A passivation layer is disposed in a channel between adjacent top reflector structures, wherein a plurality of recessed areas are formed on the passivation layer; A protective adhesive layer is disposed on the passivation layer and the protective adhesive layer is at least partially penetrated into the recessed area; In this process, after the VCSEL laser chip coated with the protective adhesive layer is cut using a laser along a direction perpendicular to the channel and the substrate is exposed, the protective adhesive layer is retained at least partially on the sidewalls of the cut VCSEL laser chip.
[0015] The aforementioned VCSEL laser chip cutting method and VCSEL laser chip, by roughening the passivation layer within the channel between the top reflector structures, increases the contact area between the passivation layer and the protective adhesive during resist coating. This makes it less likely for the heat generated by the laser during subsequent laser cutting to cause separation between the chip surface and the protective adhesive surface. Furthermore, because the roughened surface also has a certain depth in the vertical direction, the protective adhesive spin-coated vertically can also prevent lateral heat from further penetrating into the chip's interior. Thus, during side etching, the side etching solution will not seep into the chip surface through the detachment area caused by laser ablation, thereby avoiding side etching abnormalities and improving chip yield. Attached Figure Description
[0016] Figure 1 This is a schematic diagram of the structure of a VCSEL laser chip in one embodiment of this application; Figure 2 for Figure 1 The diagram shows the structure of the VCSEL laser chip after the formation of the protective adhesive layer. Figure 3 This is a schematic diagram of the structure of a recessed region in a VCSEL laser chip according to an embodiment of this application. Figure 4 This is a schematic diagram of another recessed region in the VCSEL laser chip in the embodiments of this application. Figure 5 This is a schematic diagram of another recessed region in the VCSEL laser chip in the embodiments of this application. Figure 6 This is a flowchart illustrating a method for cutting a VCSEL laser chip according to an embodiment of this application. Figure 7 for Figure 6 The diagram shows the structure of the VCSEL laser chip provided in the VCSEL laser chip cutting method. Figure 8 for Figure 6 The diagram shows the structure of a VCSEL laser chip after laser cutting, as illustrated in the VCSEL laser chip cutting method.
[0017] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0018] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0019] It is understood that the terms "first," "second," etc., used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first client may be referred to as a second client, and similarly, a second client may be referred to as a first client.
[0020] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. "Multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. "Several" means at least one, such as one, two, etc., unless otherwise explicitly specified.
[0021] like Figure 1-2 As shown, this application provides a VCSEL laser chip, including a substrate 10; a bottom mirror structure 110, an active layer 120, a top mirror structure 130, a passivation layer 140, and a protective adhesive layer 150 disposed on the substrate 10.
[0022] Among them, there are multiple top reflector structures 130, and the multiple top reflector structures 130 are spaced apart on the active layer 120.
[0023] Understandably, several oxide confinement layers 131 are formed in the top reflector structure 130.
[0024] In this specific embodiment, the bottom reflector structure 110 and the top reflector structure 130 define the resonant cavity structure of the vertical cavity surface-emitting laser of this application; that is, the region between the bottom reflector structure 110 and the top reflector structure 130 is the resonant cavity. The resonant cavity is used to generate standing waves, which are waves formed by two coherent waves propagating in opposite directions along the same straight line and superimposing on each other. Specifically, when the two waves are in phase, their amplitudes are added together to form antinodes (i.e., wave crests). When the two waves are out of phase, their amplitudes are subtracted to form nodes (i.e., wave troughs). Therefore, the positions of the wave crests and troughs of the standing wave are fixed.
[0025] In one embodiment, the bottom reflector structure 110 may include a periodically stacked DBR structure, that is, a plurality of reflectors with an optical thickness of one-quarter of the lasing wavelength, the plurality of reflectors being arranged alternately according to high and low refractive indices.
[0026] It is understood that the composition, stacking cycle number, etc., of the DBR structure of the bottom reflector structure 110 and the DBR structure of the top reflector structure 130 may be the same or different, and this embodiment does not impose any limitations. The materials of the top reflector structure 130 and the bottom reflector structure 110 can be electrically insulating dielectric materials, such as silicon nitride, silicon oxide, aluminum oxide, or titanium oxide. The materials of the top reflector structure 130 and the bottom reflector structure 110 can also be semiconductor materials, such as GaAs and AlGaAs.
[0027] The substrate 10 is made of materials including, but not limited to, GaAs, InP, and Si. The bottom mirror structure 110 and the top mirror structure 130 may include films with periodically varying refractive indices to achieve efficient reflection or transmission of light within a specific wavelength range. These films can be made of semiconductor materials, dielectric materials, or metal-dielectric hybrid materials. For example, the bottom mirror structure 110 may be an N-type semiconductor layer, and the top mirror structure 130 may be a P-type semiconductor layer. Alternatively, the bottom mirror structure 110 may be a P-type semiconductor layer, and the top mirror structure 130 may be an N-type semiconductor layer. Optionally, the materials of the N-type and P-type semiconductor layers may be, but are not limited to, GaAs, AlGaAs, etc. This is not a limitation; as long as the resonant cavity can be defined, it falls within the scope of this embodiment.
[0028] The active layer 120 may include one, two, three, or four active regions. Each active region may contain one or more multi-quantum-well structures. The multi-quantum-well structures are used to generate photons through stimulated emission, and the emitted photons are continuously reflected in the resonant cavity defined by the bottom mirror structure 110 and the top mirror structure 130, and are continuously amplified during the reflection process, thereby ultimately emitting laser light at a specific wavelength with sufficient energy.
[0029] The multiple quantum well structure is where laser gain amplification occurs. The center of the multiple quantum well structure can be aligned with the location of the strongest light field to achieve a greater amplification effect. Furthermore, when multiple multiple quantum well structures are included, their confinement factors within the same light field segment are within the same preset range; that is, the confinement factors of each multiple quantum well structure are maintained at the same level, ensuring that each multiple quantum well structure contributes similarly to the light emission. Understandably, similar light emission contributions mean more uniform current injection into each multiple quantum well structure, which helps reduce the device's threshold current, thereby reducing power consumption and extending its lifespan. Moreover, when each multiple quantum well structure contributes similarly to the light emission, the distribution of charge carriers within each multiple quantum well structure will be more uniform, which helps reduce carrier recombination losses, thereby improving the overall luminous efficiency of the device.
[0030] In this embodiment, the passivation layer 140 is disposed in the channel between adjacent top reflector structures 130.
[0031] Of course, in actual use, a passivation layer / protective layer can also be provided on the top reflector structure 130, and no specific limitation is made here.
[0032] Alternatively, the passivation layer 140 can be made of aluminum oxide or aluminum nitride.
[0033] In one possible embodiment, a plurality of recessed regions 141 are formed on the passivation layer 140.
[0034] It is understandable that by forming multiple recessed regions 141 on the passivation layer 140, the contact area between the passivation layer 140 and the protective adhesive layer 150 can be increased when the protective adhesive layer 150 is subsequently applied to the passivation layer 140. This makes it less likely that the heat generated by the laser during subsequent laser cutting will cause the chip surface to separate from the protective adhesive surface. In addition, since the recessed regions 141 also have a certain depth in the vertical direction, the protective adhesive within the recessed regions 141 can also prevent lateral heat from further penetrating into the inside of the chip. Thus, during side etching, the side etching solution will not seep into the chip surface through the detachment area caused by laser burning, thereby avoiding abnormal side etching.
[0035] Optionally, continue to refer to Figure 2 As shown, the depression depths of each depression region 141 are equal.
[0036] As another implementation method, such as Figure 3 As shown, the depth of each recessed region 141 is different.
[0037] In one possible embodiment, the recessed region 141 may be uniformly distributed on the passivation layer 140, or it may be formed in a region close to the top reflector structure 130.
[0038] Optionally, such as Figure 4 As shown, the depth of the recessed region 141 decreases in the direction away from the top reflector structure 130.
[0039] Of course, in actual use, the depth of the recessed area 141 can also be reduced in a direction away from the top reflector structure 130.
[0040] In one possible embodiment, the number of recessed regions 141 is three.
[0041] Of course, the number of recessed regions 141 can also be greater than 3. No specific limitation is made here.
[0042] In one possible embodiment, the gaps between adjacent recessed regions 141 are unequal.
[0043] In one possible embodiment, the shape of the recessed region 141 may be an inverted triangle (e.g., Figure 4 (as shown), or it can be a rectangle (such as...) Figure 5 (As shown), it can also be other shapes, but no specific limitation is made here.
[0044] In this embodiment, the protective adhesive layer 150 is disposed on the passivation layer 140 and the protective adhesive layer 150 at least partially penetrates into the recessed region 141.
[0045] For example, the protective adhesive layer 150 can also completely fill the recessed area 141.
[0046] It is understood that after the VCSEL laser chip coated with the protective adhesive layer 150 is cut with a laser along a direction perpendicular to the channel and the substrate 10 is exposed, the sidewalls of the cut VCSEL laser chip retain at least part of the protective adhesive layer 150.
[0047] like Figure 6 As shown in the figure, this application embodiment also provides a method for cutting a VCSEL laser chip, which specifically includes the following steps: Step S201: Provide a VCSEL laser chip.
[0048] For example, such as Figure 7 As shown, the VCSEL laser chip includes a substrate 10, a bottom mirror structure 110 and an active layer 120 stacked sequentially, a plurality of top mirror structures 130 spaced apart on the active layer 120 and a passivation layer 140 located in a channel between adjacent top mirror structures 130.
[0049] Step S202: The passivation layer is roughened to form multiple recessed areas on the passivation layer.
[0050] For example, the passivation layer 140 is roughened by etching to form multiple recessed regions 141, such as... Figure 1 As shown.
[0051] Optionally, the etching method can be dry etching or wet etching, without specific limitations.
[0052] As one implementation, step S202 includes: etching the surface of the passivation layer to form a plurality of recessed regions with different depths on the passivation layer.
[0053] It is understandable that by forming multiple recessed areas of varying depths on the passivation layer, the protective adhesive can be embedded into the recessed areas to varying depths during subsequent coating, providing different levels of interlocking force. This makes it less likely for the heat generated by the laser during subsequent laser cutting to cause the chip surface to separate from the protective adhesive surface.
[0054] In another implementation, step S202 includes: etching the surface of the passivation layer to form a plurality of recessed regions of equal depth on the passivation layer.
[0055] It is understandable that by forming multiple recessed areas of equal depth on the passivation layer, the protective adhesive can be uniformly embedded in the recessed areas during subsequent coating, so that the heat generated by the laser during subsequent laser cutting will not easily cause the chip surface to separate from the protective adhesive surface.
[0056] As another implementation, step S202 includes: etching the area of the passivation layer near the top mirror structure to form a plurality of recessed areas of varying depths in the area.
[0057] Optionally, the passivation layer near the top mirror structure is etched to form a plurality of recessed regions with different depths in the region, including: etching the passivation layer near the top mirror structure to form a plurality of recessed regions with different depths in the region, wherein the depth of the recessed regions decreases along the direction away from the top mirror structure.
[0058] It is understandable that by etching only the area close to the top reflector structure, and the deeper the recess, the deeper the protective adhesive is applied in the vertical direction. This makes it less likely for the heat generated by the laser during subsequent laser cutting to separate the chip surface from the protective adhesive surface. In addition, since the protective adhesive also has a certain depth in the vertical direction, the protective adhesive obtained by spin coating in the vertical direction can also prevent the heat from the lateral direction from penetrating further into the inside of the chip.
[0059] In another embodiment, etching is performed on the area of the passivation layer near the top mirror structure to form a plurality of recessed regions of varying depths in the area, including: etching the area of the passivation layer near the top mirror structure to form a plurality of recessed regions of varying depths in the area, wherein the depth of the recessed regions decreases in a direction away from the top mirror structure.
[0060] Optionally, the number of recessed areas is three.
[0061] In another implementation, step S202 includes: etching the area of the passivation layer near the top mirror structure to form a plurality of recessed areas of equal depth in the area.
[0062] In this embodiment, the gaps between adjacent recessed areas are unequal.
[0063] Step S203: A protective adhesive layer is spin-coated onto the roughened passivation layer, and the protective adhesive layer at least partially penetrates into the recessed area.
[0064] Optionally, the height of the protective adhesive layer is higher than the height of the top reflector structure.
[0065] Step S204: Use a laser to cut the VCSEL laser chip coated with the protective adhesive layer along a direction perpendicular to the channel to expose the substrate.
[0066] In this case, the protective adhesive layer is at least partially retained on the sidewalls of the cut VCSEL laser chip, such as... Figure 8 As shown.
[0067] Alternatively, the VCSEL laser chip coated with the protective adhesive layer can be cut along a position perpendicular to the center of the channel to expose the substrate.
[0068] Understandably, in this embodiment, by roughening the passivation layer within the channel between the top reflector structures, the increased contact area between the passivation layer and the protective adhesive at the etching location during resist coating makes it less likely for the heat generated by the laser during subsequent laser cutting to separate the chip surface from the protective adhesive surface. Furthermore, since the roughened surface also has a certain depth in the vertical direction, the protective adhesive spin-coated in the vertical direction can also prevent lateral heat from further penetrating into the chip's interior. Thus, during side etching, the side etching solution will not seep into the chip surface through the detachment area caused by laser ablation, thereby avoiding side etching abnormalities and improving chip yield.
[0069] In one embodiment, this application also provides a light emitting component, which includes at least one VCSEL laser chip.
[0070] In one embodiment, this application also provides an optical module including at least one optical emitting component as described above.
[0071] The foregoing disclosure provides illustrations and descriptions, but is not intended to be exhaustive or to limit the embodiments to the precise forms disclosed. Modifications and variations may be made in light of the foregoing disclosure or may be derived from practice of the embodiments. Furthermore, any embodiments described herein may be combined unless the foregoing disclosure expressly provides for reasons why one or more embodiments may not be combined.
[0072] Even though specific combinations of features are listed in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of the various embodiments. In fact, many of these features can be combined in ways not specifically listed in the claims and / or disclosed in the specification. Although each dependent claim listed below may directly depend on only one claim, the disclosure of the various embodiments includes each dependent claim combined with each other claim in the claim set. As used herein, the phrase “at least one of” in the list of items refers to any combination of these items, including a single member. As an example, “at least one of: a, b, or c” is intended to cover a, b, c, ab, ac, bc, and abc, as well as any combination having multiple identical items.
[0073] When a component or one or more components (e.g., a laser emitter or one or more laser emitters) is described or required (within a single claim or across multiple claims) to perform or be configured to perform multiple operations, this language is intended to broadly cover a wide range of architectures and environments. For example, unless explicitly required otherwise (e.g., by using “first component” and “second component” or other language distinguishing components in the claims), this language is intended to cover a single component performing or configured to perform all operations, a group of components jointly performing or configured to perform all operations, a first component performing or configured to perform a first operation and a second component performing or configured to perform a second operation, or any combination of components performing or configured to perform operations. For example, when a claim takes the form “one or more components are configured to: perform X; perform Y; and perform Z,” the claim should be interpreted as meaning “one or more components are configured to perform X; one or more (possibly different) components are configured to perform Y; and one or more (possibly different) components are configured to perform Z.”
[0074] The elements, actions, or instructions used herein should not be construed as critical or necessary unless explicitly stated otherwise. Furthermore, as used herein, the articles “a” and “one” are intended to include one or more items and may be used interchangeably with “one or more.” Further, as used herein, the article “the” is intended to include one or more items referenced in combination with the article “the” and may be used interchangeably with “the one or more.” Additionally, as used herein, the term “set” is intended to include one or more items (e.g., related items, unrelated items, or a combination of related and unrelated items) and may be used interchangeably with “one or more.” Where only one item is intended, the phrase “only one” or similar language is used. Furthermore, as used herein, the terms “having,” “containing,” “with,” etc., are intended to be open-ended terms. Further, unless explicitly stated otherwise, the phrase “based on” is intended to mean “at least partially based on.” Furthermore, as used herein, unless otherwise expressly stated (e.g., when used in combination with “any one” or “only one of”), the term “or” is intended to be inclusive when used in series and can be used interchangeably with “and / or”. Further, for ease of description, spatially relative terms such as “below,” “lower,” “above,” “upper,” etc., may be used herein to describe the relationship of an element or feature to another element(s) or feature(s) illustrated in the accompanying drawings. In addition to the orientations depicted in the accompanying drawings, spatially relative terms are intended to cover different orientations of devices, apparatuses, and / or elements in use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatially relative descriptors used herein shall be interpreted accordingly.
Claims
1. A method for cutting a VCSEL laser chip, characterized in that, The method comprises: providing a VCSEL laser chip, the VCSEL laser chip comprising a substrate, a bottom mirror structure and an active layer arranged in sequence, and a plurality of top mirror structures arranged in intervals on the active layer and a passivation layer arranged in the channels between adjacent top mirror structures; roughening the passivation layer to form a plurality of recessed regions on the passivation layer; spinning a protective glue layer on the roughened passivation layer, the protective glue layer at least partially penetrating into the recessed regions; cutting the VCSEL laser chip coated with the protective glue layer along a direction perpendicular to the channel direction by using a laser to expose the substrate; wherein the side wall of the cut VCSEL laser chip at least partially retains the protective glue layer.
2. The method of claim 1, wherein the plurality of VCSEL laser chips are arranged in a two-dimensional array. The roughening of the passivation layer to form a plurality of recessed regions on the passivation layer comprises: etching the surface of the passivation layer to form a plurality of recessed regions with different recessed depths on the passivation layer.
3. The method of claim 1, wherein the plurality of VCSEL laser chips are arranged in a two-dimensional array. The roughening of the passivation layer to form a plurality of recessed regions on the passivation layer comprises: etching the surface of the passivation layer to form a plurality of recessed regions with equal recessed depths on the passivation layer.
4. The method of claim 1, wherein the plurality of VCSEL laser chips are arranged in a two-dimensional array. The roughening of the passivation layer to form a plurality of recessed regions on the passivation layer comprises: etching the region of the passivation layer close to the top mirror structure to form a plurality of recessed regions with different recessed depths in the region.
5. The method of claim 4, wherein the laser beam is a VCSEL laser beam. The etching of the region of the passivation layer close to the top mirror structure to form a plurality of recessed regions with different recessed depths in the region comprises: etching the region of the passivation layer close to the top mirror structure to form a plurality of recessed regions with different recessed depths in the region, the recessed depths of the recessed regions decreasing in a direction away from the top mirror structure.
6. The method of claim 4, wherein the laser beam is a VCSEL laser beam. The etching of the region of the passivation layer close to the top mirror structure to form a plurality of recessed regions with different recessed depths in the region comprises: etching the region of the passivation layer close to the top mirror structure to form a plurality of recessed regions with different recessed depths in the region, the recessed depths of the recessed regions decreasing in a direction away from the top mirror structure.
7. The cutting method of the VCSEL laser chip according to any one of claims 4-6, wherein: the number of the recessed regions is 3.
8. The method of claim 1, wherein, The roughening of the passivation layer to form a plurality of recessed regions on the passivation layer comprises: etching the region of the passivation layer close to the top mirror structure to form a plurality of recessed regions with equal recessed depths in the region.
9. The method of claim 1-6, wherein, The gap between adjacent recessed regions is not equal.
10. A VCSEL laser chip, characterized in that The VCSEL laser chip comprises: a substrate; a bottom mirror structure arranged on the substrate; an active layer arranged on the bottom mirror structure; a plurality of top mirror structures arranged in intervals on the active layer; a passivation layer arranged in the channels between adjacent top mirror structures. A passivation layer is arranged in the channel between adjacent top mirror structures, wherein a plurality of recessed regions are formed on the passivation layer; A protective adhesive layer is arranged on the passivation layer and at least partially penetrates into the recessed regions; After the VCSEL laser chip coated with the protective adhesive layer is cut by laser along a direction perpendicular to the channel direction and the substrate is exposed, the sidewall of the cut VCSEL laser chip at least partially retains the protective adhesive layer.