Method for forming interconnection structure
By forming grooves in the sacrificial layer and dielectric layer and forming metal interconnect layers in the grooves, and then removing the sacrificial layer and metal interconnect layers by wet etching, the problem of high-density and high aspect ratio metal interconnect structures that are difficult to form by traditional processes is solved, simplifying the process steps and improving efficiency.
Patent Information
- Application Number
- CN202411166219.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-23
- Publication Date
- 2026-03-06
AI Technical Summary
Traditional double damask processes are difficult to meet the requirements for device size reduction when manufacturing high-density and high aspect ratio metal interconnect structures, and the etching and chemical mechanical polishing processes are complex.
A semi-damascene process is used to form grooves in the sacrificial layer and dielectric layer, and a metal interconnect layer is formed in the grooves. The sacrificial layer and metal interconnect layer are removed by wet etching, avoiding dry etching and chemical mechanical polishing, thus simplifying the process steps.
It enables the formation of high-density and high aspect ratio metal interconnect layers, simplifies the process flow, and reduces process complexity.
Smart Images
Figure CN121620184A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a method for forming an interconnect structure. Background Technology
[0002] With the continuous development of semiconductor technology, the size of semiconductor devices is becoming smaller and smaller. Currently, the double damascene process is commonly used to form interconnect structures. The double damascene process generally includes the following steps: First, a dielectric material is deposited on the metal interconnect layer; then, a photoresist pattern is formed on the dielectric layer using photolithography to define the positions of vias and interconnect trenches; next, the photoresist pattern is transferred into the dielectric layer to form the actual vias and trenches; then, a metal interconnect layer is deposited in the vias and trenches and on the conductive layer, and chemical mechanical polishing is performed to remove excess metal interconnect layer, making the metal interconnect layer flush with the surface of the dielectric layer, i.e., only the metal interconnect layer inside the vias and trenches is retained. However, as device size shrinks, the spacing between metal interconnect layers is becoming increasingly tight, and the traditional double damascene process can no longer meet the requirements. Therefore, in the manufacturing process of interconnect structures, a semi-damascene process is used to fabricate metal interconnect layers. However, to achieve high density and a large metal line depth-to-width ratio structure, the requirements for metal interconnect layer etching are also higher. Summary of the Invention
[0003] The purpose of this invention is to provide a method for forming an interconnect structure that eliminates the need for etching and chemical mechanical polishing of the metal interconnect layer during the formation of the metal interconnect layer, thereby simplifying the process.
[0004] To achieve the above objectives, the present invention provides a method for interconnecting structures, comprising:
[0005] A substrate is provided on which a first dielectric layer and a first sacrificial layer are sequentially formed, wherein a first groove is formed in the first sacrificial layer and the first dielectric layer, and the first groove penetrates the first sacrificial layer and extends into the first dielectric layer.
[0006] A first metal interconnect layer is formed in the first groove and on the first sacrificial layer, wherein the first metal interconnect layer in the first groove is separated from the first metal interconnect layer on the first sacrificial layer;
[0007] Remove the first sacrificial layer and the first metal interconnect layer on the first sacrificial layer, and expose the first dielectric layer and the first metal interconnect layer in the first groove;
[0008] A second dielectric layer and a second sacrificial layer are sequentially formed on the first dielectric layer. The second dielectric layer and the second sacrificial layer have a second groove, which exposes the top surface of the first metal interconnect layer.
[0009] A second metal interconnect layer is formed in the second groove and on the second sacrificial layer. The second metal interconnect layer in the second groove is separated from the second metal interconnect layer on the second sacrificial layer, and the second metal interconnect layer in the second groove is electrically connected to the first metal interconnect layer.
[0010] Remove the second sacrificial layer and the second metal interconnect layer on the second sacrificial layer.
[0011] Optionally, the width of the opening of the first groove is smaller than the width of the bottom of the first groove.
[0012] Optionally, the first groove includes a connected upper part and a lower part of the first groove, the upper part of the first groove penetrates the first sacrificial layer, and the lower part of the second groove penetrates a portion of the thickness of the first dielectric layer, wherein the cross-sectional shape of the upper part of the first groove is trapezoidal and the cross-sectional shape of the lower part of the first groove is square.
[0013] Optionally, the method for forming the first groove in the first dielectric layer and the first sacrificial layer includes:
[0014] A patterned first photoresist layer is formed on the first sacrificial layer. The patterned first photoresist layer has a first opening with a trapezoidal cross-sectional shape, and the first opening exposes a portion of the first sacrificial layer.
[0015] Using the patterned first photoresist layer as a mask, the first sacrificial layer at the bottom of the first opening is etched using a dry etching process to form the upper part of the first groove, and the upper part of the first groove exposes part of the first dielectric layer.
[0016] The exposed first dielectric layer is etched using a dry etching process to form the lower part of the first groove;
[0017] Remove the patterned first photoresist layer.
[0018] Optionally, when the first metal interconnect layer is formed in the first groove and on the first sacrificial layer, the top surface of the first metal interconnect layer in the first groove is lower than the top surface of the first sacrificial layer.
[0019] Optionally, the width of the opening of the second groove is smaller than the width of the bottom of the second groove.
[0020] Optionally, the second groove includes a connected upper part and a lower part of the second groove, the upper part of the second groove penetrates the second sacrificial layer, and the lower part of the second groove penetrates a portion of the thickness of the second dielectric layer, wherein the cross-sectional shape of the upper part of the second groove is trapezoidal and the cross-sectional shape of the lower part of the second groove is square.
[0021] Optionally, the method of forming the second groove in the second dielectric layer and the second sacrificial layer includes:
[0022] A patterned second photoresist layer is formed on the second sacrificial layer, the patterned second photoresist layer having a second opening, the cross-sectional shape of the second opening being trapezoidal, and the second opening exposing the second sacrificial layer on the first metal interconnect layer;
[0023] Using the patterned second photoresist layer as a mask, the second sacrificial layer at the bottom of the second opening is dry etched to form the upper part of the second groove, and the upper part of the second groove exposes part of the second dielectric layer.
[0024] The exposed second dielectric layer is etched using a dry etching process to form the lower part of the second groove;
[0025] Remove the patterned second photoresist layer.
[0026] Optionally, when the second metal interconnect layer is formed in the second groove and on the second sacrificial layer, the top surface of the second metal interconnect layer in the second groove is lower than the top surface of the second sacrificial layer, and the second dielectric layer has an air gap formed in the second dielectric layer between the metal interconnect layers.
[0027] Optionally, both the first sacrificial layer and the second sacrificial layer are made of silicon oxide; both the first and second sacrificial layers are removed using a wet etching process, and the etching solution used in the wet etching process includes hydrofluoric acid.
[0028] In the method for forming the interconnect structure provided by the present invention, a first groove is first formed in the first sacrificial layer and the first dielectric layer; then, a first metal interconnect layer is formed in the first groove and on the first sacrificial layer. The first metal interconnect layer in the first groove is separated from the first metal interconnect layer on the first sacrificial layer. Since the first metal interconnect layer in the first groove is separated from the first metal interconnect layer on the first sacrificial layer, the first sacrificial layer and the first metal interconnect layer on the first sacrificial layer can be removed together, thereby achieving the goal of retaining only the first metal interconnect layer in the first groove. Subsequently, a second dielectric layer and a second sacrificial layer are sequentially formed on the first dielectric layer, and a second groove is formed in the second dielectric layer and the second sacrificial layer. Next, a second metal interconnect layer is formed in the second groove and on the second sacrificial layer. The second metal interconnect layer in the second groove is separated from the second metal interconnect layer on the second sacrificial layer. Since the second metal interconnect layer in the second groove is separated from the second metal interconnect layer on the second sacrificial layer, the second sacrificial layer and the second metal interconnect layer on the second sacrificial layer can be removed together, thereby retaining only the second metal interconnect layer in the second groove. In this way, there is no need to perform dry etching and chemical mechanical polishing processes on the first metal interconnect layer and the second metal interconnect layer, which simplifies the process steps and is conducive to forming a metal interconnect layer with high density and high aspect ratio. Attached Figure Description
[0029] Figure 1 This is a schematic diagram of a method for forming an interconnect structure provided in an embodiment of the present invention;
[0030] Figures 2 to 13 This is a schematic diagram of the structure formed in the method for forming the interconnect structure provided in the embodiments of the present invention;
[0031] The reference numerals in the attached figures are explained as follows:
[0032] 100 - Substrate; 110 - First dielectric layer; 120 - First sacrificial layer; 121 - Patterned first photoresist layer; 121a - First opening; 130 - First trench; 130a - Upper part of the first trench; 130b - Lower part of the first trench; 140 - First metal interconnect layer; 140a - Air gap; 150 - Second dielectric layer; 160 - Second sacrificial layer; 161 - Patterned second photoresist layer; 161a - Second opening; 170 - Second trench; 170a - Upper part of the second trench; 170b - Lower part of the second trench; 180 - Second metal interconnect layer. Detailed Implementation
[0033] The method for forming the interconnect structure proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.
[0034] Figure 1 This is a schematic diagram of a method for forming an interconnect structure provided in an embodiment of the present invention. Figure 1 As shown, the method for forming the interconnect structure includes:
[0035] Step S1: Provide a substrate on which a first dielectric layer and a first sacrificial layer are sequentially formed. A first groove is formed in the first sacrificial layer and the first dielectric layer. The first groove penetrates the first sacrificial layer and extends into the first dielectric layer.
[0036] Step S2: A first metal interconnect layer is formed in the first groove and on the first sacrificial layer, wherein the first metal interconnect layer in the first groove is separated from the first metal interconnect layer on the first sacrificial layer;
[0037] Step S3: Remove the first sacrificial layer and the first metal interconnect layer on the first sacrificial layer, and expose the first dielectric layer and the first metal interconnect layer in the first groove;
[0038] Step S4: A second dielectric layer and a second sacrificial layer are sequentially formed on the first dielectric layer. The second dielectric layer and the second sacrificial layer have a second groove. The width of the opening of the second groove is smaller than the width of the bottom of the second opening, and the second groove exposes the top surface of the first metal interconnect layer.
[0039] Step S5: A second metal interconnect layer is formed in the second groove and on the second sacrificial layer. The second metal interconnect layer in the second groove is separated from the second metal interconnect layer on the second sacrificial layer, and the second metal interconnect layer in the second groove is electrically connected to the first metal interconnect layer.
[0040] Step S6: Remove the second sacrificial layer and the second metal interconnect layer on the second sacrificial layer.
[0041] Figures 2 to 13 This is a schematic diagram of the structure formed in the method for forming the interconnect structure provided in the embodiments of the present invention; the following will be illustrated in conjunction with the appendix. Figures 2 to 13 The method for forming the interconnect structure provided in this embodiment will be described in more detail.
[0042] refer to Figure 2As shown, in step S1, a substrate 100 is provided, which serves as an operating platform for the semiconductor device structure formed in subsequent processes. The material of the substrate 100 is selected from monocrystalline silicon, polycrystalline silicon, or amorphous silicon; the material of the substrate 100 may also be selected from compounds such as silicon, germanium, gallium arsenide, or germanium-silicon; the substrate 100 may also be other semiconductor materials. Exemplarily, in this embodiment, the substrate 100 is a silicon substrate.
[0043] like Figure 2 As shown, a first dielectric layer 110 and a first sacrificial layer 120 are formed on the substrate 100. The first sacrificial layer 120 covers the first dielectric layer 110, and the first dielectric layer 110 covers the substrate 100. A device structure, such as a transistor, may be formed between the substrate 100 and the first dielectric layer 110. In this embodiment, to better illustrate the inventive points of the present invention, the description and illustration of the device structure between the substrate 100 and the first dielectric layer 110 are omitted.
[0044] As an example, the material of the first dielectric layer 110 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride, and the first dielectric layer 110 may be formed by chemical vapor deposition (CVD). The material of the first sacrificial layer 120 may include silicon oxide, and the material of the first sacrificial layer 120 may be the same as that of the first dielectric layer 110. This simplifies the process and allows for better compatibility at the interface between the first sacrificial layer 120 and the second dielectric layer 150, reducing interface defects or stress problems caused by material differences. The first sacrificial layer 120 may also be formed by chemical vapor deposition (CVD).
[0045] like Figure 5 As shown, after a first dielectric layer 110 and a first sacrificial layer 120 are sequentially formed on a substrate 100, a first groove 130 is formed in the first sacrificial layer 120 and the first dielectric layer 110. The first groove 130 penetrates the first sacrificial layer 120 and extends into the first dielectric layer 110.
[0046] Preferably, the width W1 at the opening of the first groove 130 is smaller than the width W2 at the bottom of the first groove 130. In this way, during the subsequent formation of the first metal interconnect layer 140, the first sacrificial layer 120 on the sidewall of the first groove 130 can block the first metal interconnect layer 140, which is beneficial to separate the first metal interconnect layer 140 subsequently formed in the first groove 130 from the first metal interconnect layer 140 formed on the first sacrificial layer 120.
[0047] In this embodiment, the first groove 130 can be a groove with a high aspect ratio, that is, the aspect ratio of the first groove 130 can be greater than 3. In this way, the first metal interconnect layer 140 subsequently formed in the first groove 130 can have a large aspect ratio, which is beneficial to increase the density of the subsequently formed first metal interconnect layer 140 and reduce the resistance.
[0048] Specifically, such as Figure 5 As shown, the first groove 130 includes a first groove upper part 130a and a first groove lower part 130b that are connected. The first groove upper part 130a penetrates the first sacrificial layer 120, and the second groove lower part 130b penetrates a portion of the thickness of the first dielectric layer 110. The width of the opening of the first groove 130 refers to the width of the opening of the first groove upper part 130a, and the bottom width of the first groove 130 refers to the width of the bottom of the first groove lower part 130b.
[0049] In this embodiment, the method for forming the first groove 130 in the first dielectric layer 110 and the first sacrificial layer 120 includes: firstly, as... Figure 3 As shown, a patterned first photoresist layer 121 is formed on the first sacrificial layer 120. The patterned first photoresist layer 121 has a first opening 121a. The cross-sectional shape of the first opening 121a is trapezoidal, that is, the sidewall of the first opening 121a has a certain tilt angle (not completely vertical). In this way, a groove of a similar shape can be formed in the first dielectric layer 110 during the subsequent etching process.
[0050] For example, during the formation of the patterned first photoresist layer 121, the sidewall tilt angle of the first opening 121a in the patterned first photoresist layer 121 can be adjusted by adjusting the position of the focal plane of the photolithography machine, so that the cross-sectional shape of the final formed first opening 121a is trapezoidal. Furthermore, the first opening 121a exposes a portion of the first sacrificial layer 120.
[0051] Then, as Figure 4 As shown, using the patterned first photoresist layer 121 as a mask, a dry etching process is employed to etch the first sacrificial layer 120 at the bottom of the first opening 121a to form the upper part 130a of the first groove, exposing a portion of the first dielectric layer 110. The dry etching process for etching the first sacrificial layer 120 can be anisotropic dry etching.
[0052] The cross-sectional shape of the upper part 130a of the first groove is trapezoidal, that is, the sidewall of the upper part 130a of the first groove has a certain inclination angle (not completely vertical). Since the cross-sectional shape of the first opening 121a in the patterned first photoresist layer 121 is trapezoidal, when etching the first sacrificial layer 120, the upper part 130a of the first groove with a cross-sectional shape similar to that of the first opening 121a can be formed in the first sacrificial layer 120.
[0053] Next, as Figure 5 As shown, the exposed first dielectric layer 110 is etched using a dry etching process to form the lower portion 130b of the first groove. The cross-sectional shape of the lower portion 130b of the first groove is square, such that the width of the opening of the first groove 130 is smaller than the width of the bottom of the first groove 130. The dry etching process for etching the first dielectric layer 110 can be anisotropic dry etching.
[0054] Next, the patterned first photoresist layer 121 is removed. For example, an ashing process or a plasma cleaning process can be used to remove the patterned first photoresist layer 121.
[0055] Next, refer to Figure 6 As shown, in step S2, a first metal interconnect layer 140 is formed in the first groove 130 and on the first sacrificial layer 120. The first metal interconnect layer 140 in the first groove 130 is separated from the first metal interconnect layer 140 on the first sacrificial layer 120. That is, the first metal interconnect layer 140 is formed using a semi-mosaic process. Since the width of the opening of the first groove 130 is smaller than the width of the bottom of the first groove 130, the first sacrificial layer 120 on the sidewall of the first groove 130 can prevent the deposition of the first metal interconnect layer 140 on its surface (i.e., the sidewall of the first groove 130) during the formation of the first metal interconnect layer 140. Therefore, the first metal interconnect layer 140 will not be formed on the part of the sidewall of the first groove 130 near the opening (i.e., the part of the sidewall of the upper part 130a of the first groove), thereby separating the first metal interconnect layer 140 in the first groove 130 from the first metal interconnect layer 140 on the first sacrificial layer 120.
[0056] In this embodiment, the top surface of the first metal interconnect layer 140 in the first groove 130 is lower than the top surface of the first sacrificial layer 120, so that the first metal interconnect layer 140 in the first groove 130 is completely separated from the first metal interconnect layer 140 on the first sacrificial layer 120, thereby avoiding electrical connection between the first metal interconnect layer 140 in the first groove 130 and the first metal interconnect layer 140 on the first sacrificial layer 120.
[0057] Preferably, the top surface of the first metal interconnect layer 140 in the first groove 130 is higher than the top surface of the first dielectric layer 110. This facilitates the formation of an air gap 140a in the subsequently formed second dielectric layer 150, thereby reducing parasitic capacitance.
[0058] In this embodiment, the material of the first metal interconnect layer 140 may include at least one of aluminum, titanium, tantalum, tungsten, and copper, preferably copper. The first metal interconnect layer 140 may be formed by electroplating or physical vapor deposition.
[0059] Next, refer to Figure 7 As shown, step S3 is performed to remove the first sacrificial layer 120 and the first metal interconnect layer 140 on the first sacrificial layer 120, and expose the first dielectric layer 110 and the first metal interconnect layer 140 in the first groove 130.
[0060] In this embodiment, a wet etching process is used to remove the first sacrificial layer 120 and the first metal interconnect layer 140 on the first sacrificial layer 120. The etching solution used in the wet etching process includes hydrofluoric acid, so that there is a high etching selectivity between the first sacrificial layer 120 and the first metal interconnect layer 140 in the first groove 130, thereby avoiding damage to the first metal interconnect layer 140 in the first groove 130.
[0061] Specifically, during the wet etching process, the etching solution can etch the exposed surface of the first sacrificial layer 120, causing the first sacrificial layer 120 to dissolve in the etching solution, thereby allowing the first sacrificial layer 120 to detach from the surface of the first dielectric layer 110. The exposed surface of the first sacrificial layer 120 includes the sidewall surface of the first sacrificial layer 120 exposed in the first groove 130.
[0062] When the first sacrificial layer 120 is detached, the first metal interconnect layer 140 attached to its surface will also be detached simultaneously, thereby removing the first sacrificial layer 120 and the first metal interconnect layer 140 on the first sacrificial layer 120 together. In this way, the first metal interconnect layer 140 on the first sacrificial layer 120 can be removed without performing dry etching and chemical mechanical polishing processes on the first metal interconnect layer 140, simplifying the process steps.
[0063] Furthermore, the first metal interconnect layer 140 in the first groove 130 is retained. During the wet etching process, there is a high etching selectivity between the first sacrificial layer 120 and the first metal interconnect layer 140 in the first groove 130. That is, the etching solution has a high etching rate for the first sacrificial layer 120, but a relatively weak reactivity with the first metal interconnect layer 140 in the first groove 130. In other words, the etching solution mainly etches the first sacrificial layer 120 and hardly etches the first metal interconnect layer 140 in the first groove 130. Therefore, after removing the first sacrificial layer 120 and the first metal interconnect layer 140 on the first sacrificial layer 120, the first metal interconnect layer 140 in the first groove 130 is retained.
[0064] Next, refer to Figure 11 As shown, in step S4, a second dielectric layer 150 and a second sacrificial layer 160 are sequentially formed on the second dielectric layer 150. The second dielectric layer 150 and the second sacrificial layer 160 have a second groove 170, which exposes the top surface of the first metal interconnect layer 140.
[0065] Specifically, such as Figure 8 As shown, a second dielectric layer 150 can be formed first, which covers the first dielectric layer 110 and the first metal interconnect layer 140. As an example, the material of the second dielectric layer 150 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride, and the second dielectric layer 150 can be formed by chemical vapor deposition (CVD).
[0066] In this embodiment, the material of the second dielectric layer 150 can be the same as that of the first dielectric layer 110. In other embodiments, the material of the second dielectric layer 150 can be different from that of the first dielectric layer 110. Since there is an air gap 140a between the first metal interconnect layers 140 in the original adjacent first grooves 130 after removing the first sacrificial layer 120 and the first metal interconnect layer 140 thereon, when forming the second dielectric layer 150, the second dielectric layer 150 can fill only part of the air gap 140a, so that an air gap 140a is still retained between the second dielectric layer 150 and the first metal interconnect layer 140. That is, by using non-conformal deposition of the second dielectric layer 150 to form an air gap 140a in the second dielectric layer 150, the parasitic capacitance between the first metal interconnect layers 140 can be reduced. In this embodiment, the second dielectric layer 150 is deposited on top of the air gap 140a to seal the air gap 140a. In a further embodiment, the second dielectric layer 150 may also be deposited on the sidewall of the air gap 140a.
[0067] Next, as Figure 8As shown, a second sacrificial layer 160 is formed, which covers the first dielectric layer 110. The material of the second sacrificial layer 160 may include silicon oxide, and the material of the second sacrificial layer 160 may be the same as that of the second dielectric layer 150. In other embodiments, the material of the second sacrificial layer 160 may be different from that of the second dielectric layer 150.
[0068] In this embodiment, the material of the second sacrificial layer 160 can be the same as that of the first sacrificial layer 120. In other embodiments, the material of the second sacrificial layer 160 can be different from that of the first sacrificial layer 120. The second sacrificial layer 160 can be formed by chemical vapor deposition (CVD).
[0069] Next, as Figure 11 As shown, a second groove 170 is formed in the second dielectric layer 150 and the second sacrificial layer 160. The second groove 170 exposes the top surface of the first metal interconnect layer 140. That is, the second groove 170 penetrates the second sacrificial layer 160 and a portion of the second dielectric layer 150 on the first metal interconnect layer 140.
[0070] Preferably, the width of the opening of the second groove 170 is smaller than the width of the bottom of the second groove 170. In this way, during the subsequent formation of the second metal interconnect layer 180, the second sacrificial layer 160 on the sidewall of the second groove 170 can block the second metal interconnect layer 180, thereby separating the second metal interconnect layer 180 subsequently formed in the second groove 170 from the second metal interconnect layer 180 formed on the second sacrificial layer 160.
[0071] In this embodiment, the second groove 170 can be a groove with a high aspect ratio, that is, the aspect ratio of the second groove 170 can be greater than 3, which is beneficial for forming a second metal interconnect layer with high density and high aspect ratio in the future.
[0072] In this embodiment, the bottom width of the second groove 170 is the same as the width of the top surface of the first metal interconnect layer 140.
[0073] Specifically, such as Figure 11 As shown, the second groove 170 includes a connected upper part 170a and a lower part 170b. The upper part 170a penetrates the second sacrificial layer 160, and the lower part 170b penetrates a portion of the thickness of the second dielectric layer 150. The width of the opening of the second groove 170 refers to the width of the opening of the upper part 170a, and the bottom width of the second groove 170 refers to the width of the bottom of the lower part 170b.
[0074] In this embodiment, the specific method for forming the second groove 170 in the second dielectric layer 150 and the second sacrificial layer 160 includes: as follows Figure 9 As shown, firstly, a patterned second photoresist layer 161 is formed on the second sacrificial layer 160. The patterned second photoresist layer 161 has a second opening 161a, and the cross-sectional shape of the second opening 161a is trapezoidal, meaning the sidewalls of the second opening 161a have a certain tilt angle (not completely perpendicular). Thus, in the subsequent etching process, a similarly shaped groove structure can be formed in the second dielectric layer. During the formation of the patterned second photoresist layer 161, the tilt angle of the sidewalls of the second opening 161a in the patterned second photoresist layer 161 can be adjusted by adjusting the focus plane position of the lithography machine, thereby resulting in a trapezoidal cross-sectional shape for the final formed second opening 161a. Furthermore, the second opening 161a exposes the second sacrificial layer 160 on the first metal interconnect layer 140.
[0075] Then, as Figure 10 As shown, using the patterned second photoresist layer 161 as a mask, the second sacrificial layer 160 at the bottom of the second opening 161a is dry-etched to form the upper part 170a of the second groove, exposing a portion of the second dielectric layer 150. The dry etching process for etching the second sacrificial layer 160 can be anisotropic dry etching.
[0076] The upper part 170a of the second groove has a trapezoidal cross-sectional shape, meaning that the sidewall of the upper part 170a of the second groove has a certain inclination angle (not completely vertical). Since the cross-sectional shape of the second opening 161a in the patterned second photoresist layer 161 is trapezoidal, when etching the second sacrificial layer 160, a second groove upper part 170a with a cross-sectional shape similar to that of the second opening 161a can be formed in the second sacrificial layer 160.
[0077] Next, as Figure 11 As shown, the exposed second dielectric layer 150 is etched using a dry etching process to form the lower portion 170b of the second groove. The cross-sectional shape of the lower portion 170b of the second groove is square, such that the width of the opening of the second groove 170 is smaller than the width of the bottom of the second groove 170. The dry etching process for etching the second dielectric layer 150 can be anisotropic dry etching. Afterwards, the patterned second photoresist layer 161 is removed.
[0078] Next, as Figure 12As shown, in step S5, a second metal interconnect layer 180 is formed in the second groove 170 and on the second sacrificial layer 160. The second metal interconnect layer 180 in the second groove 170 is separated from the second metal interconnect layer 180 on the second sacrificial layer 160, and the second metal interconnect layer 180 in the second groove 170 is electrically connected to the first metal interconnect layer 140. Since the width of the opening of the second groove 170 is smaller than the width of the bottom of the second groove 170, the second sacrificial layer 160 on the sidewall of the second groove 170 can prevent the deposition of the second metal interconnect layer 180 on its surface (i.e., the sidewall of the second groove 170) during the formation of the second metal interconnect layer 180. Therefore, the second metal interconnect layer 180 will not be formed on part of the sidewall of the second groove 170 (i.e., part of the sidewall of the upper part 170a of the second groove), thereby separating the second metal interconnect layer 180 in the second groove 170 from the second metal interconnect layer 180 of the second sacrificial layer 160.
[0079] In this embodiment, the top surface of the second metal interconnect layer 180 in the second groove 170 is lower than the top surface of the second sacrificial layer 160, so that the second metal interconnect layer 180 in the second groove 170 is completely separated from the second metal interconnect layer 180 on the second sacrificial layer 160, thereby avoiding electrical connection between the second metal interconnect layer 180 in the second groove 170 and the second metal interconnect layer on the second sacrificial layer 160.
[0080] In this embodiment, the second metal interconnect layer 180 may include at least one of aluminum, titanium, tantalum, tungsten, and copper, preferably copper. The material of the second metal interconnect layer 180 may be the same as that of the first metal interconnect layer 140. The second metal interconnect layer 180 may be formed by electroplating or physical vapor deposition.
[0081] Next, as Figure 13 As shown, step S6 is performed to remove the second sacrificial layer 160 and the second metal interconnect layer 180 on the second sacrificial layer 160. Specifically, a wet etching process is used to remove the second sacrificial layer 160 and the second metal interconnect layer 180 on the second sacrificial layer 160. The etching solution used in the wet etching process includes hydrofluoric acid to achieve a high etching selectivity between the second sacrificial layer 160 and the second metal interconnect layer 180 in the second trench 170, thereby avoiding damage to the second metal interconnect layer 180 in the second trench 170.
[0082] Specifically, during the wet etching process, the etching solution can etch from the exposed surface of the second sacrificial layer 160, causing the second sacrificial layer 160 to dissolve in the etching solution, thereby allowing the second sacrificial layer 160 to detach from the surface of the second dielectric layer 150. The exposed surface of the second sacrificial layer 160 includes the sidewall surface of the second sacrificial layer 160 exposed in the second groove 170.
[0083] When the second sacrificial layer 160 detaches, the second metal interconnect layer 180 attached to its surface will also detach simultaneously, thereby removing the second sacrificial layer 160 and the second metal interconnect layer 180 on its surface together. In this way, the second metal interconnect layer 180 on the second sacrificial layer 160 can be removed without performing dry etching and chemical mechanical polishing processes, simplifying the process.
[0084] Furthermore, the second metal interconnect layer 180 in the second groove 170 is retained. During the wet etching process, there is a high etching selectivity between the second sacrificial layer 160 and the second metal interconnect layer 180 in the second groove 170. That is, the etching solution has a high etching rate for the second sacrificial layer 160, but a relatively weak reactivity with the second metal interconnect layer 180 in the second groove 170. In other words, the etching solution mainly etches the second sacrificial layer 160 and hardly etches the second metal interconnect layer 180 in the second groove 170. Therefore, after removing the second sacrificial layer 160 and the second metal interconnect layer 180 on the second sacrificial layer 160, the second metal interconnect layer 180 in the second groove 170 is retained.
[0085] In this embodiment, as Figure 13 As shown, the second metal interconnect layer 180, the second dielectric layer 150, the first metal interconnect layer 140, and the first dielectric layer 110 in the second groove 170 constitute an interconnect structure. It should be noted that the interconnect structure in this embodiment can be an interconnect structure containing multiple metal interconnect layers. For example, the accompanying drawings provided by this invention only illustrate a schematic diagram of forming two metal interconnect layers, while the method for forming a multi-layered metal interconnect layer is consistent with the method provided by this invention. This process can be repeated multiple times to achieve a multi-layered metal interconnect layer, which will not be described in detail here.
[0086] In summary, in the interconnect structure formation method provided by the present invention, a first groove is first formed in the first sacrificial layer and the first dielectric layer; then, a first metal interconnect layer is formed in the first groove and on the first sacrificial layer. The first metal interconnect layer in the first groove is separated from the first metal interconnect layer on the first sacrificial layer. Since the first metal interconnect layer in the first groove is separated from the first metal interconnect layer on the first sacrificial layer, the first sacrificial layer and the first metal interconnect layer on the first sacrificial layer can be removed together, thereby achieving the goal of retaining only the first metal interconnect layer in the first groove. Subsequently, a second dielectric layer and a second sacrificial layer are sequentially formed on the first dielectric layer, and a second groove is formed in the second dielectric layer and the second sacrificial layer. Then, a second metal interconnect layer is formed in the second groove and on the second sacrificial layer. The second metal interconnect layer in the second groove is separated from the second metal interconnect layer on the second sacrificial layer. Since the second metal interconnect layer in the second groove is separated from the second metal interconnect layer on the second sacrificial layer, the second sacrificial layer and the second metal interconnect layer on the second sacrificial layer can be removed together, thereby retaining only the second metal interconnect layer in the second groove. In this way, there is no need to perform dry etching and chemical mechanical polishing processes on the first metal interconnect layer and the second metal interconnect layer, which simplifies the process steps and is conducive to forming high-density and high aspect ratio metal interconnect layers.
[0087] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
[0088] Furthermore, it should be understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the scope of protection of the present invention.
Claims
1. A method of forming an interconnect structure, comprising: The application relates to a method for manufacturing a substrate. The method comprises the following steps: providing a substrate, a first dielectric layer and a first sacrificial layer being sequentially formed on the substrate, the first sacrificial layer and the first dielectric layer having a first recess formed therein, the first recess penetrating the first sacrificial layer and extending into the first dielectric layer; forming a first metal interconnection layer in the first recess and on the first sacrificial layer, the first metal interconnection layer in the first recess and the first metal interconnection layer on the first sacrificial layer being separated from each other; removing the first sacrificial layer and the first metal interconnection layer on the first sacrificial layer, and exposing the first dielectric layer and the first metal interconnection layer in the first recess; sequentially forming a second dielectric layer and a second sacrificial layer on the first dielectric layer, the second dielectric layer and the second sacrificial layer having a second recess formed therein, the second recess exposing a top surface of the first metal interconnection layer; forming a second metal interconnection layer in the second recess and on the second sacrificial layer, the second metal interconnection layer in the second recess and the second metal interconnection layer on the second sacrificial layer being separated from each other, and the second metal interconnection layer in the second recess being electrically connected with the first metal interconnection layer; 2. The method of forming an interconnect structure of claim 1, wherein, removing the second sacrificial layer and the second metal interconnection layer on the second sacrificial layer.
3. The method of forming an interconnect structure of claim 2, wherein, The width of the first recess at the opening is smaller than the width of the bottom of the first recess.
4. The method of forming an interconnect structure of claim 3, wherein, The first recess comprises a first recess upper portion and a first recess lower portion which are communicated, the first recess upper portion penetrating the first sacrificial layer, and the first recess lower portion penetrating part of the thickness of the first dielectric layer, wherein the cross-sectional shape of the first recess upper portion is trapezoidal, and the cross-sectional shape of the first recess lower portion is square. The method for forming the first recess in the first dielectric layer and the first sacrificial layer comprises the following steps: forming a patterned first photoresist layer on the first sacrificial layer, the patterned first photoresist layer having a first opening formed therein, the cross-sectional shape of the first opening being trapezoidal, and the first opening exposing part of the first sacrificial layer; using the patterned first photoresist layer as a mask, and using a dry etching process to etch the first sacrificial layer at the bottom of the first opening to form the first recess upper portion, the first recess upper portion exposing part of the first dielectric layer; using a dry etching process to etch the exposed first dielectric layer to form the first recess lower portion; 5. The method of forming an interconnect structure of claim 1, wherein, removing the patterned first photoresist layer.
6. The method of forming an interconnect structure of claim 1, wherein, When the first metal interconnection layer is formed in the first recess and on the first sacrificial layer, the top surface of the first metal interconnection layer in the first recess is lower than the top surface of the first sacrificial layer.
7. The method of forming an interconnect structure of claim 6, wherein, The width of the second recess at the opening is smaller than the width of the bottom of the second recess.
8. The method of forming an interconnect structure of claim 7, wherein, The second recess comprises a second recess upper portion and a second recess lower portion which are communicated, the second recess upper portion penetrating the second sacrificial layer, and the second recess lower portion penetrating part of the thickness of the second dielectric layer, wherein the cross-sectional shape of the second recess upper portion is trapezoidal, and the cross-sectional shape of the second recess lower portion is square. The method for forming the second recess in the second dielectric layer and the second sacrificial layer comprises the following steps: forming a patterned second photoresist layer on the second sacrificial layer, the patterned second photoresist layer having a second opening therein, the second opening having a trapezoidal cross-sectional shape, and the second opening exposing the second sacrificial layer on the first metal interconnect layer; dry-etching the second sacrificial layer at the bottom of the second opening using the patterned second photoresist layer as a mask to form an upper portion of the second recess, the upper portion of the second recess exposing a portion of the second dielectric layer; dry-etching the exposed second dielectric layer to form a lower portion of the second recess; removing the patterned second photoresist layer.
9. The method of forming an interconnect structure of claim 1, wherein, when forming the second metal interconnect layer in the second recess and on the second sacrificial layer, a top surface of the second metal interconnect layer in the second recess is lower than a top surface of the second sacrificial layer, and the second dielectric layer has air gaps therein, the air gaps being formed in the second dielectric layer between the metal interconnect layers.
10. The method of forming an interconnect structure of claim 1, wherein, the first sacrificial layer and the second sacrificial layer each comprise silicon oxide; and a wet etching process is used to remove the first sacrificial layer and the second sacrificial layer, the wet etching process using an etching solution comprising hydrofluoric acid.