An abnormal scene interrupt reporting system

Abstract

The application relates to the technical field of integrated circuit design, in particular to an interrupt reporting system under an abnormal scene, which constructs a new data path for an interrupt control center, adopts an interrupt control center reporting mode and a bus 1 and system management processor cooperative reporting target interrupt signal mode to ensure that the host end can receive interrupt information generated by each functional unit, including the interrupt control center, avoids errors or loss of the interrupt information, improves the reliability of GPU interrupt reporting under the abnormal scene, and further improves the safety of the GPU.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to an interrupt reporting system under abnormal scenarios. Background Technology

[0002] In the massive parallel computing system of a GPU, the interrupt control center plays a crucial role as a "traffic hub" and "emergency dispatch center." It efficiently and systematically manages interrupt requests from hundreds of different internal functional units and reports to the CPU (host) in a timely and accurate manner, thereby coordinating with the CPU to control task scheduling, error handling, and system synchronization. It has evolved from simple signal transmission into an intelligent subsystem that directly affects the GPU's performance, reliability, and programmability.

[0003] Interrupt requests are a spontaneous reporting mechanism for functional units, designed to inform the host of their task completion status, error messages, and status changes. The interrupt control center first acts as a storage unit for interrupt information packets. When a functional unit generates an interrupt information packet, it writes it to the interrupt control center's storage via the first bus. Then, after scheduling and arbitration, the interrupt control center transmits the internal interrupt data request to the host.

[0004] However, the interrupt control center is typically considered a functional unit as well. When it reports an interrupt error or other exception, it also triggers an interrupt. Like other functional units, this interrupt needs to be sent to the interrupt control center; that is, if the interrupt control center's reporting process fails, it needs to re-report the interrupt itself. In this situation, even if the interrupt control center stores the interrupt-related information, the problem of not being able to report it to the host still exists, leading to a vicious cycle and even data loss.

[0005] Therefore, improving the reliability of GPU interrupt reporting in abnormal scenarios, and thus enhancing GPU security, has become an urgent problem to be solved. Summary of the Invention

[0006] To address the aforementioned technical problems, the technical solution adopted by this invention is as follows:

[0007] An interrupt reporting system for abnormal scenarios, the system comprising: several functional units, a system management processor, a first bus, an interrupt control center, a second bus, and a host terminal;

[0008] For any functional unit, the functional unit is used to generate an interrupt information packet when a fault occurs, and then send the interrupt information packet to the interrupt control center through the first bus;

[0009] The interrupt control center is used to generate an interrupt request based on the interrupt information packet after receiving the interrupt information packet, and then send the interrupt request to the host through the second bus;

[0010] The second bus is used to send response information to the interrupt control center based on the transmission status of the interrupt request sent to the host.

[0011] The interrupt control center is also used to send a target interrupt signal to the system management processor via the first bus when the response information meets the first preset condition;

[0012] The system management processor is used to notify the host of the target interrupt signal.

[0013] Compared with the prior art, the present invention has significant advantages. Through the above technical solution, the interruption reporting system under abnormal scenarios provided by the present invention achieves considerable technical progress and practicality, and has broad industrial application value. It has at least the following advantages:

[0014] This invention constructs a new data path for the interrupt control center. It adopts a method of reporting the target interrupt signal by the interrupt control center and by coordinating the reporting of the bus and the system management processor. This ensures that the host can receive interrupt information from various functional units, including those generated by the interrupt control center, thus avoiding errors or loss of interrupt information. This improves the reliability of GPU interrupt reporting in abnormal scenarios and thereby enhances the security of the GPU. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the structure of an interruption reporting system under abnormal scenarios provided by an embodiment of the present invention;

[0017] Figure 2 A schematic diagram of a circular buffer in an interrupt reporting system under abnormal scenarios provided by an embodiment of the present invention;

[0018] Figure 3 This invention provides a schematic diagram of the structure of the first and second registers in an interrupt reporting system under abnormal scenarios, as provided in an embodiment of the invention.

[0019] Figure 4This is a schematic diagram illustrating the processing flow of abnormal response information in an interruption reporting system under abnormal scenarios, provided by an embodiment of the present invention. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] This embodiment provides an interrupt reporting system under abnormal scenarios. The system includes: several functional units, a system management processor, a first bus, an interrupt control center, a second bus, and a host terminal.

[0022] For any functional unit, the functional unit is used to generate an interrupt information packet when a fault occurs, and then send the interrupt information packet to the interrupt control center through the first bus;

[0023] The interrupt control center is used to generate an interrupt request based on the interrupt information packet after receiving the interrupt information packet, and then send the interrupt request to the host through the second bus;

[0024] The second bus is used to send response information to the interrupt control center based on the transmission status of the interrupt request sent to the host.

[0025] The interrupt control center is also used to send a target interrupt signal to the system management processor via the first bus when the response information meets the first preset condition;

[0026] The system management processor is used to notify the host of the target interrupt signal.

[0027] The functional unit can refer to the functional unit inside the GPU chip. The GPU chip can contain multiple functional units. When any functional unit fails, the functional unit will generate an interrupt information packet and send it to the first bus. The first bus will then send the interrupt information packet to the interrupt control center. For example, the interrupt information packet contains information such as the functional unit identifier, the source of the functional unit failure, the virtual user identifier, the address mapping page table identifier, and the processing flow identifier.

[0028] The interrupt control center processes the received interrupt information packet accordingly, generates an interrupt request, sends the interrupt request to the second bus, and then the second bus sends the interrupt request to the host.

[0029] The transmission status of the interrupt request sent to the host can refer to whether the interrupt request was successfully delivered to the host.

[0030] See Figure 1 This is a structural diagram of an interrupt reporting system under abnormal scenarios provided by an embodiment of the present invention, with a single functional unit as an example.

[0031] In one embodiment, when the response information meets the first preset condition, the interrupt control center adjusts the interrupt signal to a preset level to obtain the target interrupt signal, so as to notify the first bus. After obtaining the target interrupt signal, the first bus generates a corresponding request and sends it to the system management processor. The system management processor informs the host of the target interrupt signal. For example, the preset level is high level, and correspondingly, the initial level of the interrupt signal is low level.

[0032] In one specific implementation, the interrupt control center includes a data storage unit;

[0033] The data storage unit is used to store the interrupt information packets sent by each functional unit to the interrupt control center;

[0034] The data storage unit has a write address pointer and a read address pointer. The write address pointer is used to identify the first location information of the currently received interrupt information packet, and the read address pointer is used to identify the second location information of the interrupt information packet that has been sent to the host.

[0035] As an example, the data storage unit is implemented using a circular buffer.

[0036] Specifically, during initialization, the read address pointer and write address pointer of the data storage unit are equal and both are 0. When an interrupt information packet is received from another functional unit, the interrupt control center converts the interrupt information packet into interrupt data and stores it in the data storage unit. Each time an interrupt information packet is stored, the write address pointer is incremented by 1. The write address pointer can also be used to indicate the number of interrupt information packets received.

[0037] After the host resolves an interrupt request, it sends a read address pointer to the interrupt control center to indicate that several interrupt requests have been processed. The data storage unit updates the read address pointer and clears the processed interrupt data. The success or failure of interrupt data transmission can be determined based on the positions of the read and write address pointers.

[0038] It should be noted that the host also includes an interrupt storage unit, which is used to store interrupt data received by the host. For example, the host can process multiple interrupt requests in batches serially. Therefore, the issued read address pointer may be incremented by M at a time, where M is a positive integer.

[0039] See Figure 2 This is a schematic diagram of a circular buffer in an interrupt reporting system under abnormal scenarios provided by an embodiment of the present invention. In this diagram, 2.1 represents the initialization state of the circular buffer, where the read address pointer and write address pointer of the data storage unit are equal and both are 0. As an example, 2.2 represents the state of the circular buffer when it receives three interrupt information packets and the host has not yet finished processing any interrupt data. In this case, the write address pointer is 3 and the read address pointer is 0. As an example, 2.3 represents the state of the circular buffer when it receives three interrupt information packets and the host has finished processing one interrupt data. In this case, the write address pointer is 3 and the read address pointer is 1.

[0040] In one specific implementation, the interrupt request includes a real data request, an adaptive data request, a real address request, and an adaptive address request, wherein the real data request and the real address request are generated based on the interrupt information packet sent by the functional unit, and the adaptive data request and the adaptive address request are generated based on the interrupt information packet corresponding to the interrupt control center during testing.

[0041] Among them, the real data request corresponds to the interrupt information packet of the functional unit, the real address request corresponds to the position of the interrupt information packet of the functional unit in the data storage unit, and the real address request can be determined according to the write address pointer.

[0042] When the GPU is not fully configured, the various functional units cannot send interrupt information packets. The interrupt control center needs to perform a warm-up test to check whether the reporting path is normal. Therefore, the interrupt control center will automatically generate an empty data request and an empty address request, which are adaptive data requests and adaptive address requests.

[0043] In one specific implementation, the response information includes normal response information and abnormal response information, wherein the abnormal response type corresponding to the abnormal response information includes at least: address translation abnormal type, access address abnormal type, destination abnormal type, data abnormal type, data request timeout abnormal type, and address request timeout abnormal type.

[0044] Among them, a normal response message indicates that the interruption request was successfully delivered to the host, while an abnormal response message indicates that the interruption request was not successfully delivered to the host. The abnormal response type can indicate the reason why the interruption request was not successfully delivered to the host.

[0045] Address translation error type refers to an address translation error that occurs when the interrupt request issued by the interrupt control center passes through the address translation unit, and the correct and valid address cannot be found in the host system memory.

[0046] An address access exception could mean that when the interrupt control center reports an interrupt request to the second bus, the address translation is correct, but the destination address being accessed does not exist.

[0047] The destination-side exception type can be that the interrupt request reported by the interrupt control center through the second bus successfully reaches the destination, but the destination gives an incorrect response due to problems such as the interrupt being occupied or the interrupt memory unit being full.

[0048] Data anomaly types can refer to discrepancies that occur before and after data enters the data storage unit, resulting in incorrect data.

[0049] The data request timeout exception type can refer to the situation where, after the interrupt control center initiates a data request, it should receive a response from the second bus within a certain period of time. If the waiting time exceeds the set time threshold, it is considered a write response timeout exception. The time threshold can be configured by the implementer through registers.

[0050] Address request timeout exception type means that after the interrupt control center initiates an address request, if the host does not process it for a long time, that is, if it does not update the read address pointer of the interrupt control center, then an exception needs to be reported.

[0051] In one specific implementation, the first preset condition is that the response information belongs to the abnormal response information.

[0052] When the response information is an abnormal response information, it means that the interrupt information of the functional unit cannot be reported to the host normally through the interrupt control center and the second bus. The interrupt control center needs to generate its own interrupt and send it to the host through the newly constructed interrupt control center, the first bus, the system management processor and the host, so as to avoid the interrupt control center repeatedly failing to report through the second bus, resulting in interrupt data errors or loss.

[0053] In one specific implementation, the interrupt control center includes a first register and a second register. The first register is used to store the interrupt information packet corresponding to the abnormal response information that meets the second preset condition. The second register is used to store the abnormal response type corresponding to the abnormal response information and the request type of the interrupt request corresponding to the abnormal response information. The request type of the interrupt request includes a real data request type, an adaptive data request type, a real address request type, and an adaptive address request type.

[0054] As an example, the first register is a 32-bit wide register, in which 8 bits are used to represent the functional unit identifier, 8 bits are used to represent the source of the functional unit fault, 5 bits are used to represent the virtual user identifier, and 11 bits are used to represent the address mapping page table identifier and the processing flow identifier.

[0055] As an example, there are four types of requests in this embodiment, so they can be represented by 2-bit encoding. There are also four types of non-timeout exception response types, which can also be represented by 2-bit encoding. By combining the encoding of the request type and the encoding of the non-timeout exception response type, there are a total of 16 possible results. There are two types of timeout exception response types, which use one-hot encoding and require an 18-bit width. That is, the width of the second register is at least 18 bits.

[0056] See Figure 3 This is a schematic diagram of the structure of the first and second registers in an interrupt reporting system under abnormal scenarios provided by an embodiment of the present invention. The second register also uses a 32-bit width. As an example, the real data request type, adaptive data request type, real address request type, and adaptive address request type in the request type are encoded as 00, 01, 10, and 11 in sequence. The address translation exception type, access address exception type, destination exception type, and data exception type in the non-timeout exception response type are encoded as 00, 01, 10, and 11 in sequence. As an example, when an address translation exception type error occurs in the adaptive data request type, the two codes are concatenated to obtain 0100, which corresponds to the 5th bit in the second register. The 5th bit in the second register is set to 1. The 16th and 17th bits in the second register correspond to the data request timeout exception type and the address request timeout exception type, respectively. As an example, when a data request timeout exception type occurs, the 16th bit in the second register is set to 1.

[0057] Specifically, in this embodiment, timeout exception response types are encoded separately so that when timeout exception response types and non-timeout exception response types occur simultaneously, they can also be effectively represented by the second register.

[0058] In one specific implementation, the interrupt control center is further configured to, after sending the interrupt request to the second bus, determine whether the request type of the interrupt request is a real data request type. If the request type of the interrupt request is a real data request type, then record the interrupt information packet and request type corresponding to the interrupt request. If the request type of the interrupt request is not a real data request type, then record the request type corresponding to the interrupt request.

[0059] The interrupt control center is further configured to, when receiving an abnormal response information corresponding to the interrupt request, determine whether the abnormal response information meets a second preset condition. If the abnormal response information meets the second preset condition, the interrupt information packet of the interrupt request corresponding to the abnormal response information is stored in the first register, and the abnormal response type and the request type of the interrupt request corresponding to the abnormal response information are stored in the second register. If the abnormal response information does not meet the second preset condition, the abnormal response type and the request type of the interrupt request corresponding to the abnormal response information are stored in the second register. The second preset condition is that the request type of the interrupt request corresponding to the abnormal response information is a real data request type.

[0060] Among them, only interrupt requests of the real data request type have real interrupt information packets. Therefore, the first register is only used to store the interrupt information packets corresponding to interrupt requests of the real data request type.

[0061] Specifically, the recording and storage process can be performed in parallel with the process of sending the target interrupt signal to the system management processor. For example, the data storage unit of the interrupt control center can be implemented by N priority storage units, where N is an integer greater than 1. The target interrupt signal can include the interrupt processing signal corresponding to each priority storage unit. When any priority storage unit is not empty, the interrupt processing signal corresponding to that priority storage unit is set to a preset level. For example, the preset level is a high level. When the host receives the high-level interrupt processing signal, it processes it in order of priority. The priority order can be determined by the implementer based on the exception information. The interrupt information packet is stored in the corresponding priority storage unit.

[0062] In one specific implementation, the host terminal is used to read the first register and the second register of the interrupt control center when it receives the target interrupt signal, obtain interrupt-related information and process the interrupt-related information;

[0063] The host terminal is also used to send a clear signal to the first bus and the interrupt control center after completing the processing of the interrupt-related information.

[0064] Specifically, when the interruption request is a real data request, the interruption-related information includes the interruption information packet, request type, and exception response type; when the interruption request is not a real data request, the interruption-related information includes the request type and exception response type.

[0065] Specifically, the clear signal is used to instruct the first bus and the interrupt control center to set their own state to idle, and to instruct the interrupt control center to clear the contents of the first register and the second register.

[0066] See Figure 4 This is a schematic diagram of the processing flow of abnormal response information in an interrupt reporting system under abnormal scenarios provided by an embodiment of the present invention. In this system, steps S101 to S109 are executed by the interrupt control center, and steps S110 to S111 are executed by the host. It can be seen that whenever the interrupt control center executes step S101, that is, after sending an interrupt request to the second bus, steps S102 to S104 are always executed, that is, the required information is recorded according to the request type corresponding to the interrupt request. After receiving the abnormal response information, step S105 is executed to record the abnormal type E. According to the judgment result of step S106, the interrupt information packet, request type and abnormal type are selectively written into the corresponding registers. Then step S109 is executed, that is, the target interrupt signal is reported to the first bus. After receiving the target interrupt signal, the host executes steps S110 to S111, that is, reads the contents of the registers and sends a clear signal after processing.

[0067] Since the interrupt control center relies heavily on the behavior of the first bus when reporting target interrupt signals, multiple and intensive reporting while the first bus is in a non-idle state may cause the relevant signals to be lost. Therefore, when the interrupt control center sends the target interrupt signal to the system management processor through the first bus, the state of the first bus needs to be idle to avoid receiving a new interrupt while the first bus is transmitting an interrupt, which would prevent it from being effectively reported to the host.

[0068] In this embodiment, the interrupt control center and the first bus switch between idle states by sending a clear signal from the host side, so as to ensure that the first bus is in an idle state when an interrupt is reported. The three steps of reporting, reading and clearing are completely decoupled, and the independence of interrupt reporting is more significant. The processing of each step is no longer affected by other units.

[0069] After the interrupt control center sends the target interrupt signal, during the period before the first bus is idle, the interrupt control center can latch all received exception response information within the time period. This allows the host to obtain all exception information within the time period by reading the first and second registers of the interrupt control center once it receives the target interrupt signal, thereby improving the efficiency of interrupt handling.

[0070] In this embodiment, a new data path is constructed for the interrupt control center. The interrupt control center reports the target interrupt signal, and Bus 1 and the system management processor report the target interrupt signal in a coordinated manner. This ensures that the host can receive interrupt information from various functional units, including the interrupt control center, thus avoiding errors or loss of interrupt information. This improves the reliability of GPU interrupt reporting in abnormal scenarios and thereby enhances the security of the GPU.

[0071] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of this invention is defined by the appended claims.

Claims

1. An interruption reporting system under abnormal scenarios, characterized in that, The system includes: several functional units, a system management processor, a first bus, an interrupt control center, a second bus, and a host terminal; For any functional unit, the functional unit is used to generate an interrupt information packet when a fault occurs, and then send the interrupt information packet to the interrupt control center through the first bus; The interrupt control center is used to generate an interrupt request based on the interrupt information packet after receiving the interrupt information packet, and then send the interrupt request to the host through the second bus; The second bus is used to send response information to the interrupt control center according to the transmission status of the interrupt request sent to the host. The response information includes normal response information and abnormal response information. The normal response information indicates that the interrupt request was successfully delivered to the host, and the abnormal response information indicates that the interrupt request was not successfully delivered to the host. The interrupt control center is also used to generate a target interrupt signal when the response information meets a first preset condition, and send the target interrupt signal to the system management processor through the first bus, wherein the first preset condition is that the response information belongs to the abnormal response information; The system management processor is used to notify the host of the target interrupt signal.

2. The interruption reporting system under abnormal scenarios according to claim 1, characterized in that, The interruption control center includes a data storage unit; The data storage unit is used to store the interrupt information packets sent by each functional unit to the interrupt control center; The data storage unit has a write address pointer and a read address pointer. The write address pointer is used to identify the first location information of the currently received interrupt information packet, and the read address pointer is used to identify the second location information of the interrupt information packet that has been sent to the host.

3. The interruption reporting system under abnormal scenarios according to claim 2, characterized in that, The interrupt request includes a real data request, an adaptive data request, a real address request, and an adaptive address request. The real data request and the real address request are generated based on the interrupt information packet sent by the functional unit, and the adaptive data request and the adaptive address request are generated based on the interrupt information packet corresponding to the interrupt control center during testing.

4. The interruption reporting system under abnormal scenarios according to claim 3, characterized in that, The abnormal response types corresponding to the abnormal response information include at least: address translation abnormal type, access address abnormal type, destination abnormal type, data abnormal type, data request timeout abnormal type, and address request timeout abnormal type.

5. The interruption reporting system under abnormal scenarios according to claim 4, characterized in that, The interrupt control center includes a first register and a second register. The first register is used to store the interrupt information packet corresponding to the abnormal response information that meets the second preset condition. The second register is used to store the abnormal response type corresponding to the abnormal response information and the interrupt request type corresponding to the abnormal response information. The interrupt request type includes real data request type, adaptive data request type, real address request type and adaptive address request type.

6. The interruption reporting system under abnormal scenarios according to claim 5, characterized in that, The interrupt control center is also used to determine whether the request type of the interrupt request is a real data request type after sending the interrupt request to the second bus. If the request type of the interrupt request is a real data request type, the interrupt information packet and request type corresponding to the interrupt request are recorded. If the request type of the interrupt request is not a real data request type, the request type corresponding to the interrupt request is recorded. The interrupt control center is further configured to, when receiving an abnormal response information corresponding to the interrupt request, determine whether the abnormal response information meets a second preset condition. If the abnormal response information meets the second preset condition, the interrupt information packet of the interrupt request corresponding to the abnormal response information is stored in the first register, and the abnormal response type and the request type of the interrupt request corresponding to the abnormal response information are stored in the second register. If the abnormal response information does not meet the second preset condition, the abnormal response type and the request type of the interrupt request corresponding to the abnormal response information are stored in the second register. The second preset condition is that the request type of the interrupt request corresponding to the abnormal response information is a real data request type.

7. The interruption reporting system under abnormal scenarios according to claim 6, characterized in that, The host terminal is used to read the first register and the second register of the interrupt control center when it receives the target interrupt signal, obtain interrupt-related information and process the interrupt-related information; The host terminal is also used to send a clear signal to the first bus and the interrupt control center after completing the processing of the interrupt-related information.

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