Memory

Abstract

The invention relates to the field of semiconductors, provides a memory, and aims to reduce the power consumption of the memory on the premise of not increasing the area of the memory. The memory comprises a memory array, a data transmission circuit and a peripheral circuit, the data transmission circuit is arranged between the storage array and the peripheral circuit and is used for data transmission between the storage array and the peripheral circuit; the data transmission circuit comprises a first data path and a second data path in the data transmission direction. The power end of the first data path is electrically connected with the first transmission line, and the grounding end is electrically connected with the second transmission line; the power end of the second data path is electrically connected with the second transmission line, and the grounding end is electrically connected with the third transmission line; wherein the first transmission line transmits a first power supply voltage, the second transmission line transmits a second power supply voltage, the third transmission line is electrically connected with the common grounding end, and the voltage value of the first power supply voltage is larger than that of the second power supply voltage.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor structures, and more particularly to a memory. Background Technology

[0002] In the circuit design of Dynamic Random Access Memory (DRAM), all circuits inside the chip, except for special circuits that operate at internal voltage, have a voltage range of VDD (the normal operating voltage of the chip, approximately 1V~1.1V for DRAM) to VSS (the common ground voltage of the chip).

[0003] To save power, many DRAMs use low dropout regulators (LDOs) internally to power high-power circuit modules, thereby reducing power consumption by lowering the power supply voltage of the corresponding circuit modules.

[0004] However, LDOs increase the area significantly, which is detrimental to the area reduction of DRAM. Summary of the Invention

[0005] This disclosure provides a memory that reduces power consumption without increasing memory area.

[0006] This disclosure provides a memory, including: a memory array, a data transmission circuit, and peripheral circuits; the data transmission circuit is disposed between the memory array and the peripheral circuits for data transmission between the memory array and the peripheral circuits; wherein, the data transmission circuit includes: a first data path and a second data path in the data transmission direction; the power supply terminal of the first data path is electrically connected to a first transmission line, and the ground terminal is electrically connected to a second transmission line; the power supply terminal of the second data path is electrically connected to the second transmission line, and the ground terminal is electrically connected to a third transmission line; wherein, the first transmission line transmits a first power supply voltage, the second transmission line transmits a second power supply voltage, the third transmission line is electrically connected to a common ground terminal, and the voltage value of the first power supply voltage is greater than the voltage value of the second power supply voltage.

[0007] Optionally, the data transmission circuit includes n first data paths and m second data paths in the data transmission direction, where n and m are positive integers.

[0008] Optionally, the memory further includes: an interface circuit coupled to the peripheral circuit, configured to output data from the peripheral circuit to the outside of the memory, and to transmit data from the outside of the memory to the peripheral circuit; the ground terminal of the memory array, the ground terminal of the peripheral circuit, and the ground terminal of the interface circuit are electrically connected to the third transmission line; the power supply terminal of the memory array and the power supply terminal of the peripheral circuit are electrically connected to the first transmission line; and the power supply terminal of the interface circuit is electrically connected to the second transmission line.

[0009] Optionally, the memory further includes: a clamping circuit, respectively coupled to the second transmission line and the third transmission line, configured to detect the voltage value of the second power supply voltage transmitted through the second transmission line, and when the voltage value of the second power supply voltage is greater than the voltage value of a preset voltage, to conduct the second transmission line and the third transmission line to form a discharge path.

[0010] Optionally, the clamping circuit includes: a detection control unit coupled to the second transmission line to receive the second power supply voltage; the detection control unit is configured to receive the preset voltage and compare the voltage value of the second power supply voltage with the voltage value of the preset voltage; if the voltage value of the second power supply voltage is greater than the voltage value of the preset voltage, then generate and output a discharge control signal in an active state; and a discharge unit coupled to the detection control unit, the second transmission line, and the third transmission line respectively; the discharge unit is configured to, according to the discharge control signal in an active state, conduct the second transmission line and the third transmission line to form the discharge path.

[0011] Optionally, the detection control unit includes a comparator, and the discharge unit includes a discharge transistor; the first input terminal of the comparator receives the preset voltage, the second input terminal is electrically connected to the second transmission line to receive the second power supply voltage, and the output terminal is used to output the discharge control signal; the first terminal of the discharge transistor is electrically connected to the second transmission line, the second terminal is electrically connected to the third transmission line, and the control terminal is electrically connected to the output terminal of the comparator.

[0012] Optionally, the memory further includes a voltage controller configured to receive configuration parameters from a mode register and adjust the voltage value of the preset voltage according to the configuration parameters.

[0013] Optionally, in the data transmission direction, the transmission path length of the first data path is greater than the transmission path length of the second data path.

[0014] Optionally, in the data transmission direction, the resistance of the first data path is greater than the resistance of the second data path, and the capacitance of the first data path is less than the capacitance of the second data path.

[0015] Optionally, in the data transmission direction, the data transmission rate of the first data path is greater than the data transmission rate of the second data path.

[0016] Optionally, the memory further includes a read / write control circuit, wherein the second data path is located between the memory array and the read / write control circuit, and the first data path is located between the read / write control circuit and the peripheral circuit.

[0017] Optionally, the memory further includes: a read / write control circuit and a data path selector, wherein the second data path is located between the memory array and the read / write control circuit and between the read / write control circuit and the data path selector, and the first data path is located between the data path selector and the peripheral circuit.

[0018] Optionally, the memory includes: at least one first chip and a second chip, the memory array is disposed in the first chip, and the read / write control circuit and the peripheral circuit are disposed in the second chip; the first data path includes a data transmission bus in the second chip; the second data path includes an interconnection structure between the first chip and the second chip.

[0019] The technical solution provided in this disclosure has at least the following advantages: by dividing the data transmission circuit into a first data path and a second data path, and configuring different power supply voltages and ground voltages for the first data path and the second data path respectively, the power consumption of the data transmission circuit is reduced, and no additional circuits are required to reduce the power consumption of the data transmission circuit, thus not increasing the area of ​​the memory. Attached Figure Description

[0020] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 A schematic diagram of a first structure of a memory having a single first data path and a single second data path provided in an embodiment of this disclosure; Figure 2 A schematic diagram of a second structure of a memory having a single first data path and a single second data path provided in an embodiment of this disclosure; Figure 3 A schematic diagram of a first structure of a memory having multiple first data paths and multiple second data paths provided in an embodiment of this disclosure; Figure 4 A schematic diagram of a second structure of a memory having multiple first data paths and multiple second data paths provided in an embodiment of this disclosure; Figure 5 This is an example of the structural division of the first data path and the second data path under the LPDDR architecture provided in this embodiment of the disclosure; Figure 6 This is an example of the structural division of the first data path and the second data path under the multi-chip architecture provided in this disclosure embodiment; Figure 7 This is an example of the structural division of the first data path and the second data path under the DDR architecture provided in this embodiment of the disclosure; Figure 8 Provided for embodiments of this disclosure Figure 1 The example memory also includes a schematic diagram of the interface circuit and the clamping circuit; Figure 9 A schematic diagram of the module structure of the clamping circuit provided in the embodiments of this disclosure; Figure 10 This is a schematic diagram of the specific structure of the clamping circuit provided in the embodiments of this disclosure. Detailed Implementation

[0022] It should be noted that the terminology used herein is for the purpose of describing particular implementations only and is not intended to limit the exemplary implementations according to embodiments of this disclosure. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0023] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure. It should also be understood that, for ease of description, the dimensions of the various parts shown in the drawings are not drawn to actual scale. Techniques, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters in the following drawings denote similar items; therefore, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0024] In the description of the embodiments of this disclosure, it should be understood that the orientation or positional relationship indicated by directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" is generally based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this disclosure and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of the embodiments of this disclosure; the directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.

[0025] Furthermore, it should be noted that the use of terms such as "first" and "second" to define components is merely for the purpose of distinguishing the corresponding components. Unless otherwise stated, the above terms have no special meaning and therefore should not be construed as limiting the scope of protection of this disclosure.

[0026] As is known from the background technology, in order to save power, many DRAMs use low-dropout regulators (LDOs) internally to power high-power circuit modules, thereby reducing power consumption by lowering the power supply voltage of the corresponding circuit modules.

[0027] Reducing memory power consumption through LDOs is problematic because LDOs significantly increase memory area, hindering DRAM size reduction. Therefore, finding new power supply solutions to replace LDOs for memory power consumption is crucial to avoiding increased memory area.

[0028] This disclosure provides a memory that reduces power consumption without increasing memory area. The memory includes a memory array, a data transmission circuit, and peripheral circuitry. The data transmission circuit is disposed between the memory array and the peripheral circuitry for data transmission between them. The data transmission circuit includes a first data path and a second data path in the data transmission direction. The power supply terminal of the first data path is electrically connected to a first transmission line, and its ground terminal is electrically connected to the second transmission line. The power supply terminal of the second data path is electrically connected to the second transmission line, and its ground terminal is electrically connected to a third transmission line. The first transmission line transmits a first power supply voltage, the second transmission line transmits a second power supply voltage, and the third transmission line is electrically connected to a common ground terminal. The voltage value of the first power supply voltage is greater than the voltage value of the second power supply voltage.

[0029] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0030] Figure 1 A schematic diagram of a first structure of a memory having a single first data path and a single second data path provided in an embodiment of this disclosure. Figure 2 A schematic diagram of a second structure of a memory provided in an embodiment of this disclosure, having a single first data path and a single second data path.

[0031] refer to Figure 1 and Figure 2 The memory 100 includes: a memory array 101, a data transmission circuit 102, and a peripheral circuit 103.

[0032] The storage array 101 includes multiple word lines, multiple bit lines, and multiple storage cells arranged in an array. Multiple storage cells arranged in a row are electrically connected to the same word line, and multiple storage cells arranged in the same column are electrically connected to the same bit line. The multiple word lines select a target word line based on row decoding, and the multiple bit lines select a target bit line based on column decoding. The storage array 101 selects a target storage cell from the multiple storage cells based on the target word line and the target bit line to achieve data read and write operations on the target storage cell.

[0033] The peripheral circuit 103 is used to process the data when reading and writing data to the target storage unit.

[0034] A data transmission circuit 102 is disposed between the storage array 101 and the peripheral circuit 103 for data transmission between the storage array 101 and the peripheral circuit 103. The data transmission circuit 102 includes a first data path 201 and a second data path 202 in the data transmission direction.

[0035] In one example, refer to Figure 1 When data is transmitted from the peripheral circuit 103 to the storage array 101, the data transmission circuit 102 includes a first data path 201 and a second data path 202 coupled in sequence; when data is transmitted from the storage array 101 to the peripheral circuit 103, the data transmission circuit 102 includes a second data path 202 and a first data path 201 coupled in sequence.

[0036] In another example, refer to Figure 2 When data is transmitted from the peripheral circuit 103 to the storage array 101, the data transmission circuit 102 includes a second data path 202 and a first data path 201 coupled in sequence; Reference Figure 2 When data is transmitted from storage array 101 to peripheral circuit 103, data transmission circuit 102 includes a first data path 201 and a second data path 202 coupled in sequence.

[0037] It should be noted that in the accompanying drawings and description of the embodiments disclosed herein, the data transmission circuit 102 is assumed to be a bidirectional transmission circuit; however, in some memory designs, the data transmission circuit is a unidirectional transmission circuit. In one example, the first data path includes a first path and a second path, and the second data path includes a third path and a fourth path. When data is transmitted from the peripheral circuit 103 to the storage array 101, the data transmission circuit includes the first path and the third path coupled in sequence; when data is transmitted from the storage array 101 to the peripheral circuit 103, the data transmission circuit includes the fourth path and the second path coupled in sequence.

[0038] The power supply terminal of the first data path 201 is electrically connected to the first transmission line 11, and the ground terminal is electrically connected to the second transmission line 21; the power supply terminal of the second data path 202 is electrically connected to the second transmission line 21, and the ground terminal is electrically connected to the third transmission line 31. The first transmission line 11 transmits a first power supply voltage V1, the second transmission line 21 transmits a second power supply voltage V2, and the third transmission line 31 is electrically connected to a common ground terminal to receive the common ground terminal voltage Vss. The voltage value of the first power supply voltage V1 is greater than the voltage value of the second power supply voltage V2.

[0039] For the first data path 201, since its power supply terminal is electrically connected to the first transmission line 11 and its ground terminal is electrically connected to the second transmission line 21, the operating voltage of the first data path 201 is the difference between the first power supply voltage V1 and the second power supply voltage V2, V1-V2. Compared with the ground terminal being electrically connected to the third transmission line 31, the operating voltage of the first data path 201 is reduced from V1 to V1-V2, and the corresponding operating current of the first data path 201 is also reduced, resulting in a significant reduction in the power consumption of the first data path 201.

[0040] For the second data path 202, since its power supply terminal is electrically connected to the second transmission line 21 and its ground terminal is electrically connected to the third transmission line 31, the operating voltage of the second data path 202 is the second power supply voltage V2. Compared with the power supply terminal being electrically connected to the first transmission line 11, the operating voltage of the second data path 202 is reduced from V1 to V2, and the corresponding operating current of the second data path 202 is also reduced, resulting in a significant reduction in the power consumption of the second data path 202.

[0041] For the data transmission circuit 102, the power consumption of the data transmission circuit 102 is greatly reduced because the power consumption of its components (first data path 201 and second data path 202) is reduced.

[0042] In summary, the memory 100 provided in this embodiment reduces the power consumption of the data transmission circuit 102 by dividing the data transmission circuit 102 into a first data path 201 and a second data path 202, and configuring different power supply voltages and ground voltages for the first data path 201 and the second data path 202 respectively. Moreover, the power consumption reduction of the data transmission circuit 102 does not require additional circuitry and does not increase the area of ​​the memory 100.

[0043] In one example, assuming the first power supply voltage V1 is 1.0V, the power consumption of the data transmission circuit operating between the first power supply voltage V1 and the common ground voltage Vss is A.

[0044] If an LDO is used to reduce the power consumption of the data transmission circuit, and the voltage drop of the LDO is 0.4V, then the operating voltage of the data transmission circuit is reduced from 1.0V to 0.6V, and the power consumption of the data transmission circuit is 0.6A.

[0045] For the data transmission circuit 102 provided in this embodiment, if the power consumption of the first data path 201 accounts for 60% and the power consumption of the second data path 202 accounts for 40%, and the second power supply voltage V2 is 0.6V, then the power consumption of the first data path is 60% × (1 - 0.6) × A = 0.24A, the power consumption of the second data path is 40% × 0.6 × A = 0.24A, and the overall power consumption of the data transmission circuit 102 is 0.24A + 0.24A = 0.48A. Therefore, under the same voltage drop, compared to using an LDO for power reduction, the power consumption of the data transmission circuit 102 is further reduced by the shared memory 100 provided in this embodiment.

[0046] It should be noted that, in Figure 1 and Figure 2 In this example, the data transmission circuit 102 is only divided into one first data path 201 and one second data path 202. This is only used as an example of the data transmission circuit 102 and does not constitute a limitation on the embodiments of this disclosure. In some embodiments, the data transmission circuit 102 includes n first data paths 201 and m second data paths 202 in the data transmission direction, where n and m are positive integers and can be the same or different.

[0047] Figure 3 A schematic diagram of a first structure of a memory having multiple first data paths and multiple second data paths provided in an embodiment of this disclosure; Figure 4 A schematic diagram illustrating a second structure of a memory provided in an embodiment of this disclosure, comprising multiple first data paths and multiple second data paths. (Refer to...) Figure 3In some embodiments, multiple first data paths 201 are arranged adjacent to each other, and multiple second data paths 202 are arranged adjacent to each other. (See reference...) Figure 4 In some embodiments, multiple first data paths 201 and multiple second data paths 202 are spaced apart.

[0048] The specific division method of the first data path 201 and the second data path 202 in the data transmission circuit 102 is as follows: (1) In some embodiments, if the transmission path length of the first data path 201 is greater than the transmission path length of the second data path 202 in the data transmission direction, then the voltage difference between the first power supply voltage V1 and the second power supply voltage V2 needs to be greater than the second power supply voltage V2. In some cases, the transmission path length of the data path is proportional to the equivalent resistance. A larger operating voltage is configured for the first data path 201 with a longer transmission path length (the first data path 201 with a larger equivalent resistance) to ensure smooth data transmission. Similarly, in other embodiments, if the transmission path length of the first data path 201 is less than the transmission path length of the second data path 202 in the data transmission direction, then the voltage difference between the first power supply voltage V1 and the second power supply voltage V2 needs to be less than the second power supply voltage V2.

[0049] (2) In some embodiments, if the resistance of the first data path 201 is greater than the resistance of the second data path 202 in the data transmission direction, then the voltage difference between the first power supply voltage V1 and the second power supply voltage V2 needs to be configured to be greater than the second power supply voltage V2. That is, a larger operating voltage is adapted to the first data path 201, which has higher power consumption, to ensure smooth data transmission. Similarly, in other embodiments, if the resistance of the first data path 201 is less than the resistance of the second data path 202 in the data transmission direction, then the voltage difference between the first power supply voltage V1 and the second power supply voltage V2 needs to be configured to be less than the second power supply voltage V2. It should be noted that the "resistance" described in this example can be understood as equivalent resistance.

[0050] (3) In some embodiments, if the capacitance of the first data path 201 is smaller than the capacitance of the second data path 202 in the data transmission direction, then the voltage difference between the first power supply voltage V1 and the second power supply voltage V2 needs to be configured to be greater than the second power supply voltage V2. That is, a larger operating voltage is adapted to the first data path 201, which has higher power consumption, to ensure smooth data transmission. Similarly, in other embodiments, if the capacitance of the first data path 201 is larger than the capacitance of the second data path 202 in the data transmission direction, then the voltage difference between the first power supply voltage V1 and the second power supply voltage V2 needs to be configured to be less than the second power supply voltage V2. It should be noted that "capacitance" can be understood as equivalent capacitance and / or parasitic capacitance.

[0051] (4) In some embodiments, if the data transmission rate of the first data path 201 is greater than the data transmission rate of the second data path 202 in the data transmission direction, then the voltage difference between the first power supply voltage V1 and the second power supply voltage V2 needs to be greater than the second power supply voltage V2. That is, a larger operating voltage is configured for the first data path 201, which needs to transmit data faster, to ensure smooth data transmission. Similarly, in other embodiments, if the data transmission rate of the first data path 201 is less than the data transmission rate of the second data path 202 in the data transmission direction, then the voltage difference between the first power supply voltage V1 and the second power supply voltage V2 needs to be less than the second power supply voltage V2.

[0052] In specific applications, the above methods can be considered in combination to configure the corresponding first power supply voltage V1 and second power supply voltage V2 according to the determined first data path 201 and second data path 202, or to divide the first data path 201 and second data path 202 in the data transmission circuit 102 according to the determined first power supply voltage V1 and second power supply voltage V2.

[0053] Figure 5 An example of structural partitioning of the first and second data paths under the LPDDR architecture provided in this disclosure. In one example, refer to... Figure 5 In the LPDDR (Low Power Double Data Rate) memory architecture, the memory 100 also includes: a read / write control circuit 401, a second data path 202 located between the memory array 101 and the read / write control circuit 401, and a first data path 201 located between the read / write control circuit 401 and the peripheral circuit 103.

[0054] Figure 6 This is an example of the structural division of the first and second data paths under the multi-chip architecture provided in this disclosure embodiment, with reference to... Figure 6 For a multi-chip memory architecture, the memory 100 includes at least one first chip 51 and a second chip 52. The storage array 101 is disposed in the first chip 51, and the read / write control circuit 401 and the peripheral circuit 103 are disposed in the second chip 52. At this time, the first data path 201 includes the data transmission bus in the second chip 52, and the second data path 202 includes the interconnection structure between the first chip 51 and the second chip 52.

[0055] Specifically, the storage array 101 is disposed in the first chip 51, which serves as the array chip or storage chip of the memory 100. The read / write control circuit 401 and the peripheral circuit 103 are disposed in the second chip 52, which serves as the logic chip of the memory 100.

[0056] It should be noted that, for multi-chip memory structures, the memory provided in this disclosure embodiment can be applied to 1C1A (1 CMOS die 1 Array die) memory architecture, 1C2A (1 CMOS die 2 Array die) memory architecture, 1CnA (1 CMOS die n Array die) memory architecture, 2C1A (2 CMOS die 1 Array die) memory architecture, and nC1A (n CMOS die 1 Array die) memory architecture. For the 1C1A memory architecture, the second data path 202 includes the interconnection structure between the first chip 51 and the second chip 52; for the 1C2A and 1CnA memory architectures, the second data path 202 includes the interconnection structure between each first chip 51 and each second chip 52; for the 2C1A and nC1A memory architectures, the second data path 202 includes the interconnection structure between the first chip 51 and each second chip 52.

[0057] In addition, the interconnect structure can be a through-silicon via (TSV) + through-silicon via structure used when the first chip 51 and the second chip 52 are stacked back to back, or a hybrid bonding + hybrid bonding structure used when the first chip 51 and the second chip 52 are stacked face to face, or a through-silicon via + hybrid bonding structure used when the first chip 51 and the second chip 52 are stacked face to back.

[0058] Figure 7 An example of structural partitioning of the first and second data paths under the DDR architecture provided in this disclosure. In one example, refer to... Figure 7 In the DDR (Double Data Rate) memory architecture, the memory 100 also includes: a read / write control circuit 501 and a data path selector 502. The second data path 202 is located between the memory array 101 and the read / write control circuit 501, and between the read / write control circuit 501 and the data path selector 502. The first data path 201 is located between the data path selector 502 and the peripheral circuit 103.

[0059] Figure 8 Provided for embodiments of this disclosure Figure 1 The example memory also includes a schematic diagram of the interface circuitry and clamping circuitry. (See reference) Figure 8In some embodiments, the memory 100 further includes an interface circuit 104 coupled to a peripheral circuit 103. The interface circuit 104 is configured to output data from the peripheral circuit 103 to the outside of the memory and to transmit data from the outside of the memory to the peripheral circuit 103. The ground terminal of the memory array 101, the ground terminal of the peripheral circuit 103, and the ground terminal of the interface circuit are electrically connected to a third transmission line 31. The power supply terminal of the memory array 101 and the power supply terminal of the peripheral circuit 103 are electrically connected to a first transmission line 11. The power supply terminal of the interface circuit 104 is electrically connected to a second transmission line 21.

[0060] As discussed above, in DRAM, in addition to the normal operating voltage VDD of the entire chip, there is usually a low voltage VDDQ (approximately 0.3V~0.5V) dedicated to input / output (IO). In this case, the first power supply voltage V1 is the normal operating voltage VDD of the chip, and it is provided to the power supply terminals of the memory array 101, the peripheral circuit 103, and the first data path 201 via the first transmission line 11. The second power supply voltage V2 is the low voltage VDDQ dedicated to input / output (IO), and it is provided to the ground terminal of the first data path 201, the power supply terminal of the second data path 202, and the power supply terminal of the interface circuit 104 via the second transmission line 21.

[0061] By multiplexing the chip's normal operating voltage VDD to the power supply voltage of the first data path 201, and multiplexing the low voltage VDDQ dedicated to input / output (IO) to the ground voltage of the first data path 201 and the power supply voltage of the second data path 202, the power consumption of the data transmission circuit 102 is reduced without adding an additional voltage source.

[0062] Since the first power supply voltage V1 is the chip's normal operating voltage VDD, and the second power supply voltage V2 is a low voltage VDDQ dedicated to input / output (IO), and both the first and second power supply voltages V1 and V2 are provided by the power management chip, to prevent current from flowing back to the power management chip through the first data path 201 and the second transmission line 21 and causing turbulence, the charge on the second transmission line 21 needs to be discharged when the actual voltage on the second transmission line 21 rises rapidly. (Continue to refer to...) Figure 8 In some embodiments, the memory 100 further includes a clamping circuit 105, which is coupled to the second transmission line 21 and the third transmission line 31 respectively. The clamping circuit 105 is configured to detect the voltage value of the second power supply voltage V2 transmitted through the second transmission line 21, and when the voltage value of the second power supply voltage V2 is greater than the voltage value of a preset voltage, conduct the second transmission line 21 and the third transmission line 31 to form a discharge path.

[0063] Figure 9This is a schematic diagram of the module structure of the clamping circuit provided in an embodiment of this disclosure. Figure 10 This is a schematic diagram illustrating the specific structure of the clamping circuit provided in an embodiment of this disclosure. (See reference...) Figure 9 In some embodiments, the clamping circuit 105 includes a detection control unit 301 and a discharge unit 302. The detection control unit 301 is coupled to the second transmission line 21 to receive a second power supply voltage V2. The discharge unit 302 is coupled to the detection control unit 301, the second transmission line 21, and the third transmission line 31, respectively. The detection control unit 301 is configured to receive a preset voltage and compare the voltage value of the second power supply voltage V2 with the voltage value of the preset voltage. If the voltage value of the second power supply voltage V2 is greater than the voltage value of the preset voltage, a discharge control signal in an active state is generated and output. The discharge unit 302 is configured to conduct the second transmission line 21 and the third transmission line 31 to form a discharge path according to the discharge control signal in an active state.

[0064] Specifically, when the voltage value of the second power supply voltage V2 is greater than the preset voltage value, the detection control unit 301 generates and outputs a discharge control signal in an effective state. The discharge unit 302 conducts the second transmission line 21 and the third transmission line 31 to form a discharge path. At this time, the voltage value of the second power supply voltage V2 on the second transmission line 21 drops rapidly until it is less than the preset voltage value. When the voltage value of the second power supply voltage V2 is not greater than the preset voltage value, the detection control unit 301 generates and outputs a discharge control signal in an invalid state. The discharge unit 302 does not conduct the second transmission line 21 and the third transmission line 31, and the voltage value of the second power supply voltage V2 on the second transmission line 21 remains unchanged.

[0065] refer to Figure 9 and Figure 10 The detection control unit 301 includes a comparator 71, and the discharge unit 302 includes a discharge transistor 72. The power supply terminal of the comparator 71 is connected to the first transmission line 11 to operate under the first power supply voltage V1. The first input terminal of the comparator 71 receives a preset voltage, the second input terminal is electrically connected to the second transmission line 21 to receive the second power supply voltage V2, and the output terminal is used to output a discharge control signal. The first terminal of the discharge transistor 72 is electrically connected to the second transmission line 21, the second terminal is electrically connected to the third transmission line 31, and the control terminal is electrically connected to the output terminal of the comparator 71 to receive the discharge control signal.

[0066] Specifically, when the voltage value of the second power supply voltage V2 is greater than the preset voltage value, comparator 71 generates and outputs a valid discharge control signal. Discharge transistor 72 turns on according to the valid discharge control signal, electrically connecting the second transmission line 21 and the third transmission line 31. At this time, the voltage value of the second power supply voltage V2 on the second transmission line 21 drops rapidly until it is less than the preset voltage value. When the voltage value of the second power supply voltage V2 is not greater than the preset voltage value, comparator 71 generates and outputs an invalid discharge control signal. Discharge transistor 72 turns off according to the invalid discharge control signal, the conductive path between the second transmission line 21 and the third transmission line 31 is broken, and the voltage value of the second power supply voltage V2 on the second transmission line 21 remains unchanged.

[0067] Continue to refer to Figure 9 In some embodiments, the memory 100 further includes a voltage controller 303, which is configured to receive configuration parameters from a mode register and adjust the voltage value of a preset voltage according to the configuration parameters.

[0068] Specifically, the configuration parameters of memory 100 are set to different values ​​in different operating modes, and these configuration parameters can be rewritten via the mode register write command MRW. This allows memory 100 to adjust the discharge threshold on the second transmission line 21 in different operating modes, thereby improving the reliability of memory 100.

[0069] In summary, the memory 100 provided in this embodiment reduces the power consumption of the data transmission circuit 102 by splitting the data transmission circuit 102 into a first data path 201 and a second data path 202, and configuring different power supply voltages and ground voltages for the first data path 201 and the second data path 202 respectively. Moreover, the power consumption reduction of the data transmission circuit 102 does not require additional circuitry and does not increase the area of ​​the memory 100. In addition, under the same voltage drop, the power consumption of the data transmission circuit 102 of the memory 100 provided in this embodiment is further reduced compared to the method of power reduction using an LDO.

[0070] In some embodiments, the memory may be a memory that includes volatile memory cells. For example, the memory may include various dynamic random access memories (DRAMs), such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, DDR5 SDRAM, DDR6 SDRAM, or Low Power Double Data Rate (LPDDR) SDRAM.

[0071] In some embodiments, the memory may also be an SRAM memory, a NAND flash memory, a NOR flash memory, an RRAM device, an FRAM device, a PRAM device, a TRAM device, or an MRAM device, etc.

[0072] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A memory, comprising: The memory comprises: a storage array, a data transmission circuit and a peripheral circuit; the data transmission circuit is arranged between the storage array and the peripheral circuit for data transmission between the storage array and the peripheral circuit; wherein the data transmission circuit comprises a first data path and a second data path in the data transmission direction; the power supply end of the first data path is electrically connected to a first transmission line, and the ground end is electrically connected to a second transmission line; the power supply end of the second data path is electrically connected to the second transmission line, and the ground end is electrically connected to a third transmission line; wherein the first transmission line transmits a first power supply voltage, the second transmission line transmits a second power supply voltage, the third transmission line is electrically connected to a common ground end, and the voltage value of the first power supply voltage is greater than the voltage value of the second power supply voltage.

2. The memory of claim 1, wherein, The data transmission circuit comprises n first data paths and m second data paths in the data transmission direction, and n and m are positive integers.

3. The memory of claim 1, wherein, The memory further comprises an interface circuit coupled to the peripheral circuit, configured to output data from the peripheral circuit to the outside of the memory, and transmit data from the outside of the memory to the peripheral circuit; the ground end of the storage array, the ground end of the peripheral circuit and the ground end of the interface circuit are electrically connected to the third transmission line; the power supply end of the storage array and the power supply end of the peripheral circuit are electrically connected to the first transmission line; the power supply end of the interface circuit is electrically connected to the second transmission line.

4. The memory of claim 3, wherein, The memory further comprises a clamping circuit coupled to the second transmission line and the third transmission line respectively, configured to detect the voltage value of the second power supply voltage transmitted by the second transmission line, and turn on the second transmission line and the third transmission line to form a discharge path when the voltage value of the second power supply voltage is greater than the voltage value of a preset voltage.

5. The memory of claim 4, wherein, The clamping circuit comprises: a detection control unit coupled to the second transmission line to receive the second power supply voltage; the detection control unit is configured to receive the preset voltage and compare the voltage value of the second power supply voltage with the voltage value of the preset voltage, and generate and output a discharge control signal in an active state if the voltage value of the second power supply voltage is greater than the voltage value of the preset voltage; a discharge unit coupled to the detection control unit, the second transmission line and the third transmission line respectively; the discharge unit is configured to turn on the second transmission line and the third transmission line to form the discharge path according to the discharge control signal in the active state.

6. The memory of claim 5, wherein, The detection control unit comprises a comparator, and the discharge unit comprises a discharge transistor; the first input end of the comparator receives the preset voltage, the second input end is electrically connected to the second transmission line to receive the second power supply voltage, and the output end is used to output the discharge control signal; the first end of the discharge transistor is electrically connected to the second transmission line, the second end is electrically connected to the third transmission line, and the control end is electrically connected to the output end of the comparator.

7. The memory of claim 4, wherein, The memory further includes a voltage controller configured to receive a configuration parameter of a mode register and adjust a voltage value of the preset voltage according to the configuration parameter.

8. The memory of claim 1, wherein, In a data transmission direction, a transmission path length of the first data path is greater than a transmission path length of the second data path.

9. The memory of claim 1, wherein, In a data transmission direction, a resistance of the first data path is greater than a resistance of the second data path, and a capacitance of the first data path is less than a capacitance of the second data path.

10. The memory of claim 1, wherein, In a data transmission direction, a data transmission rate of the first data path is greater than a data transmission rate of the second data path.

11. The memory of claim 1, wherein, The memory further includes a read-write control circuit, the second data path is located between the memory array and the read-write control circuit, and the first data path is located between the read-write control circuit and the peripheral circuit.

12. The memory of claim 1, wherein, The memory further includes a read-write control circuit and a data path selector, the second data path is located between the memory array and the read-write control circuit and between the read-write control circuit and the data path selector, and the first data path is located between the data path selector and the peripheral circuit.

13. The memory of claim 11, wherein, The memory includes: at least one first chip and a second chip, the memory array is arranged in the first chip, and the read-write control circuit and the peripheral circuit are arranged in the second chip; the first data path includes a data transmission bus in the second chip; the second data path includes an interconnection structure between the first chip and the second chip.

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