SiP power module based on circuit board layout optimization

Abstract

The invention relates to the technical field of data processing, in particular to a SiP power module based on circuit board layout optimization, which comprises a substrate, a common element, a plurality of modules and power terminals, and is characterized in that the common element, the modules and the power terminals are welded on the substrate; carrying out distribution mode combination according to appearance packaging sizes of components in the module to generate a plurality of layout schemes; according to the wiring and junction temperature conditions of components in modules in the layout scheme, the internal layout cost of the modules and the wiring cost among the modules of the layout scheme are obtained, the total layout cost is obtained in combination with the distribution conditions of the components under different junction temperature levels so as to obtain the fitness of the layout scheme, the layout scheme is iteratively optimized based on a genetic algorithm, and the layout cost of the modules is improved. And an optimal layout scheme is obtained. According to the invention, the single-module performance and multi-module cooperation relationship is effectively balanced, and the effective optimization of the circuit board layout is realized.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, and more specifically to a SiP power module based on circuit board layout optimization. Background Technology

[0002] Currently, the power semiconductor field is undergoing a critical transformation period of replacement by third-generation semiconductors. Silicon carbide (SiC), with its core advantages of low switching losses, high temperature resistance, and high power density, has become a core component replacing IGBTs in high-end fields such as new energy vehicles, photovoltaic energy storage, and 5G communications. From a technological iteration perspective, SiC modules are breaking through towards automotive-grade and high integration. To adapt to the application requirements of higher power and current, power modules often choose to connect multi-functional modules in parallel to increase power. However, the increased number of parallel modules leads to problems such as uneven current distribution, thermal superposition, and EMI coupling, directly affecting product reliability and lifespan. Layout optimization capability has become a key indicator. From a market demand perspective, downstream customers are continuously increasing their performance requirements for multi-SiC module systems. The new energy vehicle field has increasingly higher requirements for inter-module current accuracy, while the photovoltaic inverter field has set higher standards for EMC compatibility and power density. Traditional layout solutions are no longer sufficient to meet the needs of multi-objective collaborative optimization, and efficient layout optimization technologies are urgently needed to overcome industry pain points.

[0003] Current multi-SiC module placement typically employs a technical approach combining automated algorithm assistance with manual optimization. Automated algorithm assistance primarily relies on classic algorithms for semi-automated placement, with core technologies including genetic algorithms, simulated annealing algorithms, and particle swarm optimization algorithms; mainstream design tools integrate these modules. The technical approach falls into two categories: one is single-module automated optimization combined with manual multi-module combination, where algorithms optimize the parasitic parameters and thermal performance of individual modules before manual replication and combination; the other is multi-module overall automated optimization, directly treating all modules and devices as optimization targets and outputting a global placement scheme through algorithms. In current solutions, single-module optimization and multi-module collaboration are disconnected, failing to effectively resolve the core contradiction between local optima for single modules and global collaboration among multiple modules. Summary of the Invention

[0004] This invention provides a SiP power module based on circuit board layout optimization to solve existing problems.

[0005] The SiP power module based on circuit board layout optimization of the present invention adopts the following technical solution: One embodiment of the present invention provides a SiP power module based on circuit board layout optimization, including a substrate, common components, several modules and power terminals, wherein the common components, modules and power terminals are soldered on the substrate; When designing the layout of common components, modules, and power terminals on the substrate, the modules are connected in parallel and all modules are symmetrically distributed; a common area is defined at the center of the substrate, and the common components are placed in the common area. Any module contains several components. Based on the size of the module and components, as well as the wiring, the positions of the module and components are iteratively adjusted to obtain the optimal layout scheme. The specific steps include the following: Based on the external packaging dimensions of the components contained in any module, several layout schemes are generated to form all the components in the module. Based on the wiring and junction temperature of the components contained in each module in any layout scheme, the internal layout cost of each module and the wiring cost between modules under the layout scheme are obtained. Combined with the distribution of components under different junction temperature levels, the total layout cost of the layout scheme is obtained. Based on the total layout cost of the layout scheme and the internal layout cost of the modules in the layout scheme, the fitness of the layout scheme is obtained. The fitness is used in conjunction with a genetic algorithm to iteratively optimize the positions of modules and components in all layout schemes to obtain the optimal layout scheme.

[0006] Optionally, the method for generating several layout schemes of all components in a module by combining the distribution patterns according to the external package dimensions of the components contained in the module includes: For any module, obtain the external package dimensions of each component within the module, and use the center point of the module as the positioning point; Sort all components from largest to smallest according to their package size. Randomly select the locations of the components with the largest package size within the layout range. If the selected location does not meet the constraints of the package size of the component, adjust the positioning point of the component until the constraints of the corresponding package size can be met, and obtain the final position of the component. The area obtained by subtracting the area corresponding to the already laid-out components from the area corresponding to the module is taken as the optional area; and a positioning position is randomly selected in the optional area. After selection, the size of the component's outer packaging and the size of the adjacent components, as well as the size requirements of the layout position, are combined with the minimum distance requirement between the components to determine whether the constraints are met. If not, the current component position is adjusted first, and then the positions of adjacent components are adjusted; until all components are laid out. Repeat the steps to generate several layout schemes, perform DRC checks, and delete layout schemes that do not meet the DRC requirements.

[0007] Optionally, the specific method for obtaining the internal layout cost of each module and the inter-module wiring cost under the layout scheme based on the wiring and junction temperature of the components contained in each module in any layout scheme, and combining the distribution of components under different junction temperature levels to obtain the total layout cost of the layout scheme, includes: Based on the wiring and junction temperature of the components contained in each module in any layout scheme, obtain the internal layout cost of each module and the inter-module wiring cost under the layout scheme. The highest junction temperature of components in any layout scheme is obtained and clustered. Based on the distance between components at different highest junction temperature levels in the clustering results, and combined with the inter-module wiring cost under the layout scheme, the total layout cost under the layout scheme is calculated.

[0008] Optionally, the specific method for obtaining the internal layout cost of each module and the inter-module wiring cost under the layout scheme based on the wiring and junction temperature of the components contained in each module in any layout scheme is as follows: Obtain the Manhattan distances between the pins that need to be connected between all components within any module, and sum them up. Use the summed result as the total wiring cost of the module. Obtain the highest junction temperature corresponding to each component in the module using simulation software, calculate the absolute value of the difference between the highest junction temperatures of all components in the module, and record the average of all such absolute values ​​as the heat dissipation cost. Multiply the total wiring cost and the heat dissipation cost of the module and normalize the product linearly to obtain the internal layout cost of the module. Under any layout scheme, the wiring length between each module and other modules and common components is obtained and denoted as the first wiring length. The variance of all first wiring lengths is used as the wiring consistency of the layout scheme. Any module is designated as the target module. The total number of intersections when the target module is wired to other modules and common components is obtained and denoted as the wiring intersection count of the target module. A preset wiring parallel spacing threshold is established. When the target module is wired to other modules and common components, the spacing between lines when wiring occurs in parallel is obtained and denoted as the wiring parallel spacing of the target module. The total wiring length of all wiring parallel spacings less than the wiring parallel spacing threshold is obtained and denoted as the parallel wiring parameter of the target module. Based on the wiring intersection counts and parallel wiring parameters of all modules under the layout scheme, and with different preset weights for the wiring intersection counts and parallel wiring parameters, the wiring complexity of the layout scheme is calculated. The inter-module wiring cost under the proposed layout scheme is calculated by combining wiring consistency and wiring complexity.

[0009] Optionally, the specific method for obtaining the highest junction temperature of components in any layout scheme and performing clustering, calculating the total layout cost under the layout scheme based on the distance between components at different highest junction temperature levels in the clustering results, and combining this with the inter-module wiring cost under the layout scheme, includes: For any layout scheme, the highest junction temperature of all components under the layout scheme is obtained by simulation tools. The highest junction temperature of all components is clustered using the K-Means clustering algorithm, and the parameter K=3 of the K-Means clustering algorithm is preset to obtain 3 clusters. The average value of the highest junction temperature of all components in the 3 clusters is obtained as the junction temperature level of the corresponding cluster. According to the junction temperature level of the clusters from large to small, the corresponding clusters are marked as high temperature region, room temperature region and low temperature region respectively. Calculate the average distance between the corresponding center points of all components belonging to the high-temperature zone and the normal-temperature zone, respectively, and denot them as the high-temperature distance and the normal-temperature distance; obtain the difference between the average maximum junction temperature of all components in the high-temperature zone and the normal-temperature zone, and combine the difference between the high-temperature distance and the normal-temperature distance to calculate the heat concentration of the layout scheme. The total layout cost under the layout scheme is calculated by combining the inter-module wiring cost and heat concentration under the aforementioned layout scheme, and by pre-setting different weights for the inter-module wiring cost and heat concentration.

[0010] Optionally, the fitness of a layout scheme is obtained based on the total layout cost and the internal layout cost of the modules in the layout scheme. The fitness is then used in conjunction with a genetic algorithm to iteratively optimize the positions of modules and components in all layout schemes to obtain the optimal layout scheme. Specific methods include: The position coordinates of all components under any layout scheme are encoded to obtain the corresponding encoding vector of the component. The fitness of the layout scheme is obtained by combining the total layout cost of the layout scheme and the internal layout cost of all modules. The fitness is used in conjunction with the encoding vector of the component to filter and iterate the layout scheme to obtain a new layout scheme. The positions of components that conflict in the new layout scheme are adjusted, and the adaptability of the adjusted layout scheme is obtained, thereby selecting the overall coarse layout scheme. The coordinates of the components in the overall coarse layout scheme are iteratively fine-tuned to obtain the optimal layout scheme.

[0011] Optionally, the specific method for encoding the position coordinates of all components under any layout scheme to obtain the corresponding encoding vector of the component includes: For any layout scheme, obtain the position coordinates of all components under the layout scheme, and encode the position coordinates of all components with real numbers to obtain the coordinate code of each component. Construct a vector from the coordinate codes of all components in the layout scheme as the encoding vector of the layout scheme, and ensure that the coordinate codes of the same position in the encoding vectors of all layout schemes correspond to the same components.

[0012] Optionally, the fitness of a layout scheme is obtained by combining the total layout cost of the layout scheme with the internal layout cost of all modules. The fitness is then used in conjunction with the component encoding vectors to filter and iterate the layout schemes to obtain a new layout scheme. Specific methods include: The average internal layout cost of all modules in the layout scheme is recorded as the total internal layout cost of the layout scheme. Based on the total layout cost and the total internal layout cost, and with preset weights for the total layout cost and the total internal layout cost, the adaptability of the layout scheme is obtained. Preset first parameter Select the one with the highest fitness The layout scheme is designated as the elite scheme, and the remaining schemes are designated as regular schemes. The elite schemes and an equal number of random regular schemes are set as the parent pool in the genetic algorithm. All schemes in the parent pool are paired to form several scheme groups. For any scheme group, the encoding vectors of the two schemes in the scheme group are obtained. A crossover factor is preset, and the encoding vectors of the two schemes in the scheme group are weighted and fused using the crossover factor to obtain the encoding vector of the new layout scheme.

[0013] Optionally, the specific method for adjusting the positions of components that conflict in the new layout scheme and obtaining the adaptability of the adjusted layout scheme to select the overall coarse layout scheme includes: For any new layout scheme, when any component in the new layout scheme conflicts with the spacing of adjacent components, the relative position vector between the component and the conflicting component is calculated, and the coordinates are finely adjusted in the opposite direction of the vector until the minimum safe distance requirement is met; when the component exceeds the module layout area or the boundary of the heat dissipation pad, the nearest Euclidean distance from the current coordinates to the boundary of the effective area is calculated, and the component is translated in the direction of this distance until the component is completely within the effective area; after the repair is completed, the constraint verification is re-executed, and if there are still violations, the adjustment process is repeated until all components meet the constraint conditions; After each iteration, based on the fitness function, all new layout schemes are sorted from high to low fitness values. The new layout schemes are then filtered according to their fitness values, and the process continues to participate in the iteration and is repeated until the preset maximum number of iterations is reached. Finally, the layout scheme with the highest fitness is selected as the overall coarse layout scheme.

[0014] Optionally, the specific method for iteratively fine-tuning the coordinates of components in the overall coarse layout scheme to obtain the optimal layout scheme includes: For any overall coarse layout scheme, a fine-tuning range is set to apply random fine-tuning to the coordinates of each component in the overall coarse layout scheme. Simultaneously, constraint verification and repair are performed, generating several candidate schemes. These schemes are then sorted according to their fitness values, and the scheme with the highest fitness is selected. The scheme forms the parent pool, This is the preset second parameter; The schemes in the parent pool are matched pairwise to form a scheme group. The fitness of the schemes in the scheme group is obtained and the weight coefficient is obtained through linear normalization. The components at all corresponding positions in the scheme group are weighted and fused to generate a new layout scheme and add it to the parent pool. The matching, fusion, and supplementation process is repeated, and the parent pool is updated after each iteration. The iteration ends when any of the following termination conditions are met: the preset maximum number of iterations is reached; the fitness value of the optimal layout scheme does not change for 3 consecutive iterations; thus, the optimal layout scheme is obtained.

[0015] The beneficial effects of the technical solution of this invention are as follows: By combining and analyzing the external dimensions and wiring requirements of the internal components of each module, multiple layout schemes are generated. Furthermore, by comprehensively considering the wiring length within the module, heat dissipation characteristics, and the consistency and complexity of wiring between modules, a global evaluation index is constructed, achieving multi-objective optimization from local to overall. Using a genetic algorithm combined with fitness evaluation, the optimal layout configuration is obtained through iterative optimization. This solution effectively balances the performance of a single module with the collaborative relationship between multiple modules, significantly reduces the influence of parasitic parameters, improves current distribution uniformity and signal synchronization, while also improving thermal stress distribution, avoiding localized overheating, enhancing system reliability and integration density, and providing strong support for the stable operation of high-power-density electronic systems. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram illustrating the structural relationship between the layout area and the common area provided in one embodiment of the present invention; Figure 2 A flowchart illustrating the steps of circuit board layout optimization provided in one embodiment of the present invention. Detailed Implementation

[0018] To further illustrate the technical means and effects adopted by the present invention to achieve its intended purpose, the following, in conjunction with the accompanying drawings and preferred embodiments, details the specific implementation, structure, features, and effects of a SiP power module based on circuit board layout optimization proposed according to the present invention. In the following description, different "one embodiment" or "another embodiment" do not necessarily refer to the same embodiment. Furthermore, specific features, structures, or characteristics in one or more embodiments can be combined in any suitable form.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0020] The following description, in conjunction with the accompanying drawings, details a specific solution for a SiP power module based on circuit board layout optimization provided by the present invention.

[0021] Example 1: The SiP power module based on circuit board layout optimization provided in this embodiment includes a substrate, common components, several modules, and power terminals. The common components, modules, and power terminals are soldered on the substrate. The substrate material is HL832NS organic core board material. In other embodiments, ceramic materials such as silicon nitride can also be used.

[0022] In this embodiment, when designing the layout of common components, modules, and power terminals in the substrate, the modules are connected in parallel and all modules are symmetrically distributed; the substrate contains several parallel modules, and the number of parallel modules is obtained according to the design requirements; the power terminal type (such as soldered terminals) and fixed position (left and right sides of the substrate, 10mm from the edge) are determined. In addition, preset coordination parameters for the modules are included, such as the parasitic inductance difference and temperature difference between modules; the substrate size is obtained, and the minimum distance between components is set; edge constraint parameters are obtained, and based on the substrate size, the length and width of the substrate are subtracted from the edge constraint parameters to obtain a new area formed by the length and width, which serves as the layout area in the substrate; a two-dimensional rectangular coordinate system is established, with the center position of the layout area as the origin of the two-dimensional rectangular coordinate system, the horizontal axis of the two-dimensional rectangular coordinate system being parallel to the length direction of the substrate, and the vertical axis being parallel to the width direction; based on the origin of the two-dimensional rectangular coordinate system, the layout area is divided into several mutually symmetrical areas, each area being used for module layout, serving as the module layout area.

[0023] It should be noted that, in the embodiments of the present invention, the parasitic inductance difference between preset modules should be less than or equal to 0.2nH; the temperature difference should be less than or equal to 5℃; in addition, the minimum distance between preset components and the edge constraint parameters are 1mm and 5mm, respectively. The preset threshold values ​​for parasitic inductance difference, temperature difference, minimum distance between components, and edge constraint parameters can be adjusted according to the actual situation, and the embodiments of the present invention do not impose specific limitations.

[0024] Since the multi-power module solution contains common components, and the number of common components is relatively small, this embodiment first divides the layout area into common areas to arrange the common components, such as... Figure 1 The diagram shows the structural relationship between the layout area and the public area.

[0025] A common area is defined at the center of the substrate, and common components are placed in the common area.

[0026] As an optional example, a common area is defined at the center of the substrate, and common components are placed in the common area. The method includes: defining a common area in the center of the substrate, wherein the area ratio of the common area in the layout area of ​​the substrate is Q, and the center of the common area coincides with the origin of the two-dimensional rectangular coordinate system; laying out the common components in the common area, wherein the layout requirement is that the distance between the common components is minimized; the layout order is descending order of size or manual sorting, where Q is a preset area ratio.

[0027] It should be noted that, based on experience, the preset area ratio range is 20%-30%, which can be adjusted according to the actual situation. This embodiment does not impose a specific limitation. In addition, since the SiC switching speed in the power module is fast, the small differences in parasitic parameters between different modules will be amplified (such as a 1mm path difference corresponding to a 0.1nH inductance difference). Therefore, this embodiment plans the layout by symmetrically distributing different modules. This layout method can ensure that the path length and heat dissipation conditions of each module are consistent from the physical structure, thus serving as the basis for current distribution and heat balance in hardware layout design.

[0028] Example 2: It should be noted that the embodiments of the present invention take into account that in the scenario of multiple SiC modules connected in parallel, there is a fundamental difference between the local optimal goal of a single module and the global collaborative goal of multiple modules. The core conflicts are concentrated in several aspects such as parasitic parameters, heat dissipation balance, and spatial layout, all of which directly affect system performance. Traditional module layout schemes focus only on local performance in their cost functions, considering only the costs and effects within a single module, without considering the layout synergy between multiple modules when they are used in parallel.

[0029] Furthermore, when optimizing the layout of multiple parallel modules, it is first necessary to consider the overall coordination of the positions of different components within a single module. Therefore, the components of a single module are first randomly distributed within its layout area. Then, a large-scale genetic algorithm is used to transform and adjust the positions of each component on a large scale, adapting it to the overall coordination of multiple modules. This results in a coarse distribution of the overall component positions, ensuring that the overall layout meets the coordination requirements of multiple modules. Therefore, in this embodiment, after the coarse distribution, a genetic algorithm is used within the module to adjust the positions of different components, thereby optimizing the module's position to adapt to the local layout. Any module contains several components. Based on the size of the module and components, and the wiring, the positions of the module and components are iteratively adjusted to obtain the optimal layout scheme, such as... Figure 2 As shown, the specific steps are as follows: Step S201: Combine the distribution methods according to the external packaging size of the components contained in any module to generate several layout schemes for all components in the module.

[0030] It should be noted that, in one embodiment, a rough distribution plan is achieved by dividing the layout positions of multiple modules on the substrate. However, for a single module, each module usually contains multiple components (high voltage switches, diodes, capacitors, etc.). The overall distribution of these different components within the layout area needs to consider the coordination between multiple modules. In order to adapt to the cost within the module and the coordination between multiple modules, a genetic algorithm with large-scale transformation is needed to make large-scale adjustments to the different components within the layout range, and obtain the position distribution within multiple modules through the symmetry of multiple modules, simultaneously optimizing the performance of a single module and the coordination index of multiple modules, and completing the overall layout coarse optimization.

[0031] First, for any module, obtain the external package dimensions of each component within the module, and use the center point of the module as the positioning point.

[0032] Then, all components are sorted from largest to smallest according to their package size. The component with the largest package size is randomly selected and distributed within the layout range. When the selected position does not meet the constraint of the component's package size, the positioning point of the component is adjusted until the constraint of the corresponding package size can be met, thus obtaining the final position of the component.

[0033] Next, the area obtained by subtracting the area corresponding to the already laid-out components from the area corresponding to the module is used as the optional area; and a positioning position is randomly selected in the optional area. After selection, the size of the component's outer packaging and the size of the adjacent components, as well as the size requirements of the layout position, are combined with the minimum distance requirement between the components to determine whether the constraints are met. If not, the current component position is adjusted first, and then the positions of adjacent components are adjusted; until all components are laid out.

[0034] Finally, repeat the steps to generate several layout schemes and perform a Design Rule Check (DRC), deleting layout schemes that do not meet the DRC requirements.

[0035] It should be noted that in this embodiment of the invention, the number of layout schemes generated is selected as 100, which can be adjusted according to the actual situation. This embodiment of the invention does not impose any specific limitations.

[0036] Step S202: Based on the wiring and junction temperature of the components contained in each module in any layout scheme, obtain the internal layout cost of each module and the wiring cost between modules under the layout scheme, and combine the distribution of components under different junction temperature levels to obtain the total layout cost of the layout scheme.

[0037] It should be noted that among the several layout schemes obtained, since they are combined based on random distribution, the actual effects produced by different schemes vary greatly. There may be a large number of layouts that cannot effectively meet the layout requirements. Therefore, this embodiment of the invention selects to iterate these layout schemes through a genetic algorithm, expand the schemes by exchanging the positions of different components, and make a preliminary coarse layout positioning by combining the cost within the module and between multiple modules.

[0038] Step S221: Based on the wiring and junction temperature of the components contained in each module in any layout scheme, obtain the internal layout cost of each module and the wiring cost between modules under the layout scheme.

[0039] It should be noted that when laying out the internal components of a module, the main considerations are usually the wiring cost, thermal coupling, and parasitic parameters between the components within the module. Therefore, this embodiment calculates these factors separately to obtain the layout costs of each component within any module.

[0040] First, obtain the Manhattan distances between the pins that need to be connected between all components within any module, and sum them up. Use the summed result as the total wiring cost of the module. Then, obtain the highest junction temperature of each component in the module using simulation software, calculate the absolute value of the difference between the highest junction temperatures of all components in the module, and record the average of all such absolute values ​​as the heat dissipation cost. Finally, multiply the total wiring cost and the heat dissipation cost of the module and normalize the product linearly to obtain the internal layout cost of the module.

[0041] It should be noted that in this embodiment, the Simcenter Flotherm simulation software is used to simulate and obtain the junction temperature data of the components. The specific simulation software can be selected according to the actual situation. In addition, when performing multi-module layout, since the multiple modules need to be connected collaboratively and connected to common components, the cost of a single module and the layout cost of multiple modules may conflict. Therefore, this embodiment of the invention performs multi-module layout by using the symmetry between multiple modules, and then performs coordination quantification between multiple modules by using the position between multiple modules and common modules and other parameters to determine the layout coordination of multiple modules.

[0042] Then, by leveraging the symmetry of multi-path wiring, and taking the origin of the coordinate system as the center, all modules are expanded through a symmetrical layout along the axis of symmetry.

[0043] As an optional embodiment, the method of expanding the single-channel module through a symmetrical layout, based on the number of modules, includes: setting the number of modules N to 2, 4, and 6, with corresponding layout methods as follows: when When, with the horizontal or vertical axis as the axis of symmetry, place the module on both sides of the axis of symmetry; when At that time, by using central symmetry, the farthest point of coordinates is taken as the central symmetry point, and according to... The layout is distributed in a certain way; when When, with the horizontal or vertical axis as the axis of symmetry, and according to The modules are distributed in a layout such that the number of modules on both sides of the axis of symmetry is 3.

[0044] It should be noted that while individual modules aim for the shortest possible path during routing, when multiple modules are combined, there may be poor consistency in the paths between modules, as well as overlapping and interference in the routing. Therefore, it is necessary to judge the routing balance by checking the routing between modules. When routing between modules, the main considerations are the consistency of routing length and the complexity of the routing.

[0045] Secondly, under any layout scheme, the wiring length between each module and other modules and common components is obtained, denoted as the first wiring length, and the variance of all first wiring lengths is used as the wiring consistency of the layout scheme; any module is denoted as the target module, and the total number of intersections when the target module is wired to other modules and common components is obtained, denoted as the wiring intersection number of the target module; a wiring parallel spacing threshold is preset, and when the target module is wired to other modules and common components, the spacing between the lines when the wiring occurs in parallel is obtained, denoted as the wiring parallel spacing of the target module; the total wiring length of all wiring parallel spacings less than the wiring parallel spacing threshold is obtained, denoted as the parallel wiring parameter of the target module; based on the wiring intersection number and parallel wiring parameter of all modules under the layout scheme, and with different preset weights for the wiring intersection number and parallel wiring parameter, the wiring complexity of the layout scheme is calculated.

[0046] It should be noted that in this embodiment, the preset parallel spacing threshold for wiring is 1mm according to the wiring design requirements. In other embodiments, the parallel spacing threshold for wiring can be adjusted according to the specific wiring design requirements. This embodiment is not intended to limit the specific requirements.

[0047] As an optional embodiment, for any layout scheme, the specific method for calculating the routing complexity of the layout scheme is as follows:

[0048] in, This indicates the wiring complexity of the layout scheme; Indicates the first layout scheme. Number of wiring crosses for each module; Indicates the first layout scheme. Parallel routing parameters for each module; , These represent the number of routing crossovers and the weights of the parallel routing parameters, respectively.

[0049] It should be noted that, in the embodiments of the present invention, a preset , The values ​​are 0.4 and 0.6 respectively. In this embodiment, , The weighting is based on the actual constraints and priorities of the engineering routing. Specifically, in high-density multi-module layouts, the electromagnetic interference (EMI) and signal crosstalk risks caused by excessively small parallel spacing of wiring far outweigh the impact of the number of crossovers on performance. Therefore, parallel wiring parameters are given higher weights to strengthen the subsequent penalties for violations of parallel segment spacing. While wiring crossovers affect inter-layer switching and the number of vias, this can be mitigated by increasing the number of wiring layers, and the harm is relatively low, so the weight is set to 0.4. This design balances signal integrity and manufacturability, meets the requirements of high-frequency, high-power electronic systems for thermo-electrical co-optimization, and ensures that the layout meets electrical performance requirements while reducing the difficulty of subsequent wiring.

[0050] Finally, the inter-module wiring cost under the proposed layout scheme is calculated by combining wiring consistency and wiring complexity.

[0051] As an optional embodiment, for any layout scheme, the specific calculation method for the inter-module wiring cost under the layout scheme is as follows:

[0052] in, This represents the inter-module wiring cost under the described layout scheme; This indicates the consistency of wiring under the described layout scheme; This indicates the wiring complexity of the layout scheme; and These represent the weights for routing consistency and routing complexity, respectively. This represents the linear normalization function.

[0053] It should be noted that, in the embodiments of the present invention, the weights of routing consistency and routing complexity are preset. and The values ​​are 0.6 and 0.4 respectively. In power electronics or high-frequency communication systems, the consistency of wiring length between modules and common components directly affects signal synchronization, current distribution uniformity, and thermal stress distribution. Excessive length differences can lead to dynamic response imbalance and localized overheating, thus giving it higher weight. While wiring complexity (HL) affects EMI and manufacturing yield, it can be mitigated by optimizing wiring paths or adding layer stacking structures, making it relatively controllable. Therefore, wiring consistency is taken as the primary optimization goal to ensure the stability and reliability of the overall system performance, reflecting the design logic of first achieving global balance and then optimizing local components, which meets the engineering practice requirements of highly integrated multi-module systems. In addition, the wiring cost between modules reflects the comprehensive cost of wiring complexity and consistency among modules under the corresponding layout scheme. The larger this value, the higher the comprehensive cost of the layout scheme, and the more it should be eliminated among all layout schemes.

[0054] Step S222: Obtain the highest junction temperature of the components in any layout scheme and perform clustering. Based on the distance between components at different highest junction temperature levels in the clustering results, and combined with the wiring cost between modules under the layout scheme, calculate the total layout cost under the layout scheme.

[0055] It should be noted that single-module heat dissipation aims to minimize its own junction temperature (e.g., concentrating heat-generating components near heat dissipation pads). However, when multiple modules are combined, the heat-generating core of a single module may be concentrated due to the optimal layout of the single module. After multiple modules are combined, a heat accumulation point is formed, resulting in heat dissipation imbalance. Therefore, in order to avoid temperature aggregation between multiple modules, temperature clustering is performed by combining the highest junction temperature of each component with the position distribution of each component on the substrate to determine the temperature uniformity.

[0056] First, for any layout scheme, the highest junction temperature of all components under the layout scheme is obtained by simulation tools. The highest junction temperature of all components is clustered using the K-Means clustering algorithm, and the parameter K=3 of the K-Means clustering algorithm is preset to obtain 3 clusters. The average value of the highest junction temperature of all components in the 3 clusters is obtained as the junction temperature level of the corresponding cluster. According to the junction temperature level of the clusters from large to small, the corresponding clusters are marked as high temperature region, room temperature region and low temperature region respectively.

[0057] It should be noted that in this embodiment of the invention, the parameter K of the K-Means clustering algorithm is set to 3 according to the temperature level distribution of the components, so that the clustering results conform to the temperature distribution level of the components under normal conditions, thereby obtaining the high temperature zone, the normal temperature zone and the low temperature zone.

[0058] Then, the average distance between the corresponding center points of all components belonging to the high-temperature zone and the normal-temperature zone is calculated, and denoted as the high-temperature distance and the normal-temperature distance, respectively; the difference between the average maximum junction temperature of all components in the high-temperature zone and the normal-temperature zone is obtained, and the heat concentration of the layout scheme is calculated by combining the difference between the high-temperature distance and the normal-temperature distance.

[0059] As an optional embodiment, for any layout scheme, the heat concentration of the layout scheme is calculated:

[0060] In the formula: This indicates the heat concentration of the layout scheme; and These represent the distance at high temperatures and the distance at normal temperatures, respectively. and These represent the average maximum junction temperature of all components in the high-temperature region and the normal-temperature region, respectively. This represents the linear normalization function.

[0061] It should be noted that the higher the value of heat concentration, the more concentrated the heat generated by all modules is under this layout scheme; when the location distribution of the high temperature zone is significantly concentrated relative to the normal temperature zone, that is, the high temperature distance is smaller, and the average maximum junction temperature of all components in the high temperature zone is higher, it indicates that the heat of multiple modules is more concentrated and the heat distribution is less balanced.

[0062] Finally, the total layout cost under the layout scheme is calculated by combining the inter-module wiring cost and heat concentration under the aforementioned layout scheme, and by pre-setting different weights for the inter-module wiring cost and heat concentration.

[0063] As an optional embodiment, for any layout scheme, the specific method for calculating the total layout cost under the layout scheme is as follows:

[0064] in, This represents the total layout cost under the given layout scheme. This represents the cost of wiring between modules; the larger the value, the higher the cost of wiring between modules. This indicates the heat concentration of the multiple modules; the larger the value, the more concentrated the heat is across the multiple modules. and These represent the weights of wiring costs between modules and heat concentration, respectively.

[0065] It should be noted that, in the embodiments of the present invention, the weights of the wiring cost and heat concentration between preset modules are... and The weights are 0.6 and 0.4 respectively. In this embodiment, electrical performance and signal integrity are prioritized over thermal distribution optimization in high-density multi-module electronic systems. The cost of wiring between modules directly affects signal transmission delay, power distribution consistency, and EMI characteristics. Uneven wiring or excessive complexity can directly lead to system malfunctions or failures, hence its higher weight (0.6). While heat concentration affects long-term reliability and the difficulty of heat dissipation design, it can be externally compensated by enhancing heat dissipation structures (such as heat sinks and air ducts), and its harm is delayed and mitigateable. Therefore, wiring cost is the primary optimization objective, with thermal balance as a secondary optimization goal, reflecting the engineering design principle of "electricity first, thermal synergy," ensuring that the system achieves acceptable thermal distribution while meeting electrical performance requirements. The total layout cost obtained through the above scheme is... This is a comprehensive evaluation index that reflects the overall cost of the current layout scheme in terms of both electrical connection efficiency and thermal distribution rationality. A higher value indicates a less ideal layout in terms of inter-module wiring burden and heat accumulation, implying a higher risk of signal distortion, worse thermal reliability, and more complex subsequent wiring and heat dissipation design. By weighted fusion of wiring and thermal factors, a quantitative evaluation of multi-objective optimization is achieved, guiding the genetic algorithm to converge towards the globally optimal solution with excellent electrical performance and balanced thermal distribution, thereby improving system integration and stability.

[0066] Step S203: Based on the total layout cost of the layout scheme and the internal layout cost of the modules in the layout scheme, obtain the fitness of the layout scheme. Use the fitness and combine it with the genetic algorithm to iteratively optimize the positions of modules and components in all layout schemes to obtain the optimal layout scheme.

[0067] It should be noted that, based on the overall cost and intra-module cost described above, the various layout schemes are iteratively analyzed using a genetic algorithm to obtain the optimal overall layout. When performing the overall coarse layout of modules, the overall layout cost of multiple modules is used as the basis. Minimizing costs is the primary objective, with minimizing internal costs of the module as a secondary objective. During the genetic algorithm process, the substrate coordinates of the components are used as optimization variables to change the overall position of the components. Thus, during the iteration process, the coarse layout, i.e. the approximate position, of the components within the module is determined.

[0068] Step S231: Encode the position coordinates of all components under any layout scheme to obtain the corresponding encoding vector of the component. Combine the total layout cost of the layout scheme and the internal layout cost of all modules to obtain the fitness of the layout scheme. Use the fitness and the encoding vector of the component to filter and iterate the layout scheme to obtain a new layout scheme.

[0069] First, for any layout scheme, obtain the position coordinates of all components under the layout scheme, and encode the position coordinates of all components with real numbers to obtain the coordinate code of each component. Construct a vector from the coordinate codes of all components in the layout scheme as the encoding vector of the layout scheme, and ensure that the coordinate codes of the same position in the encoding vectors of all layout schemes correspond to the same components.

[0070] Then, the average internal layout cost of all modules in the layout scheme is recorded as the total internal layout cost of the layout scheme. Based on the total layout cost and the total internal layout cost, and with preset weights for the total layout cost and the total internal layout cost, the fitness of the layout scheme is obtained.

[0071] As an optional embodiment, for any layout scheme, the specific method for calculating the fitness of the layout scheme is as follows:

[0072] in, This indicates the adaptability of the layout scheme; and These are the weights of the total layout cost and the total internal layout cost, respectively. This represents the total layout cost under the given layout scheme. This represents the total internal layout cost under the given layout scheme.

[0073] It should be noted that, in this embodiment, the weights of the total layout cost and the total internal layout cost are set to 0.7 and 0.3 respectively based on experience, and can be adjusted according to the actual situation. This embodiment of the invention does not impose any specific limitations.

[0074] Finally, preset the first parameter Select the one with the highest fitness The layout scheme is designated as the elite scheme, and the remaining schemes are designated as regular schemes. The elite schemes and an equal number of random regular schemes are set as the parent pool in the genetic algorithm. All schemes in the parent pool are paired to form several scheme groups. For any scheme group, the encoding vectors of the two schemes in the scheme group are obtained. A crossover factor is preset, and the encoding vectors of the two schemes in the scheme group are weighted and fused using the crossover factor to obtain the encoding vector of the new layout scheme.

[0075] As an optional embodiment, the method for weighted fusion of the encoding vectors of two schemes in the scheme group using a cross factor to obtain the encoding vector of a new layout scheme includes: ,in The encoding vector representing the new layout scheme; This represents the preset crossover factor; This represents the encoding vector of a scheme in the scheme group; This represents the encoding vector of any scheme in the scheme group.

[0076] It should be noted that, based on experience, the first parameter in this embodiment is preset to 10 and the cross factor is 0.6. These parameters can be adjusted according to actual conditions, and this embodiment of the invention does not impose any specific limitations.

[0077] Additionally, it should be noted that for the child layout schemes (i.e., new layout schemes) generated through the scheme group, since they are obtained through cross-fusion, there is a high probability that invalid situations such as insufficient component spacing, exceeding the heat dissipation pads, and cross-module distribution will occur in the child. Therefore, it is necessary to adjust the invalid positions to valid positions through two steps of constraint verification and repair to ensure that each swapped layout scheme meets the process and performance requirements.

[0078] Step S232: Adjust the positions of components that conflict in the new layout scheme, and obtain the adaptability of the adjusted layout scheme, thereby selecting the overall coarse layout scheme.

[0079] It should be noted that after generating the offspring layout scheme using the genetic algorithm, the cross-fusion of encoding vectors may cause the component layout to violate physical constraints (such as insufficient component spacing, exceeding the heat sink pad area, or cross-module distribution). Therefore, a systematic constraint verification and repair of the offspring scheme is necessary to ensure that the scheme meets process and performance requirements. Specifically, constraint judgment is first performed: for all components in the layout scheme, each item is verified according to preset process constraints (including minimum safe distance between components, heat sink pad boundary limits, and module area isolation rules). For components that violate constraints, their coordinates are automatically adjusted in the following priority order: First, for any new layout scheme, when any component in the new layout scheme conflicts with the spacing of adjacent components, the relative position vector between the component and the conflicting component is calculated, and the coordinates are finely adjusted in the opposite direction of the vector until the minimum safe distance requirement is met. When the component exceeds the module layout area or the boundary of the heat dissipation pad, the nearest Euclidean distance from the current coordinates to the boundary of the effective area is calculated, and the component is translated in the direction of this distance until the component is completely within the effective area. After the repair is completed, the constraint verification is re-executed. If there are still violations, the adjustment process is repeated until all components meet the constraint conditions.

[0080] Then, after each iteration, based on the fitness function, all new layout schemes are sorted from high to low fitness values, and the new layout schemes are filtered according to the size of the fitness value. They continue to participate in the iteration and are executed in a loop until the preset maximum number of iterations is reached. Finally, the layout scheme with the highest fitness is selected as the overall coarse layout scheme.

[0081] As an optional embodiment, the specific method for obtaining the overall layout scheme is as follows: After each iteration, all offspring individuals are sorted from high to low fitness value according to the fitness function. The top 50% of high-quality individuals are retained as the core of the next generation population, and the bottom 50% of low-quality individuals are eliminated. At the same time, to maintain population diversity, 5% to 10% of randomly generated new individuals are added to form a new generation population, which continues to participate in subsequent iterations and is executed cyclically until the preset maximum number of iterations is reached. Finally, the layout scheme with the highest fitness is selected as the overall coarse layout scheme.

[0082] It should be noted that the maximum number of iterations is set to 200 in this embodiment, but it can be adjusted according to the actual situation. This embodiment of the invention does not impose any specific limitations.

[0083] Step S233: Iteratively fine-tune the coordinates of the components in the overall coarse layout scheme to obtain the optimal layout scheme.

[0084] It should be noted that since the coarse layout obtained above represents the approximate positions of different components, the local positions still need to be finely adjusted to improve the final layout efficiency. Therefore, this embodiment of the invention selects a small-scale genetic algorithm to perform fine-tuning of the component details while maintaining the overall layout.

[0085] As a specific example, the coordinates of components in the overall coarse layout scheme are iteratively fine-tuned to obtain the optimal layout scheme. The methods include: First, for any overall coarse layout scheme, a fine-tuning range is set to apply random fine-tuning to the coordinates of each component in the overall coarse layout scheme. Simultaneously, constraint verification and repair are performed to generate several candidate schemes. These schemes are then sorted according to their fitness values, and the scheme with the highest fitness is selected. The scheme forms the parent pool, This is the preset second parameter.

[0086] It should be noted that, based on experience, the preset fine-tuning range in this embodiment is 0~3mil, and the second parameter is 20. These parameters can be adjusted according to actual conditions, and this embodiment of the invention does not impose any specific limitations.

[0087] Subsequently, the schemes in the parent pool are matched pairwise to form scheme groups. The fitness of the schemes in the scheme groups is obtained and the weight coefficients are obtained through linear normalization. Coordinate weighted fusion is performed on all corresponding components in the scheme groups to generate new layout schemes and supplement them to the parent pool.

[0088] Finally, the matching, fusion, and supplementation process is repeated, and the parent pool is updated after each iteration. The iteration ends when any of the following termination conditions are met: the preset maximum number of iterations is reached; the fitness value of the optimal layout scheme does not change for three consecutive iterations; thus, the optimal layout scheme is obtained.

[0089] At this point, the fine-tuning of the module is complete. The output layout scheme, while maintaining the global synergy of multiple modules, achieves local optimization of wiring cost and heat dissipation performance within a single module, significantly improving system integration and reliability.

[0090] This concludes the embodiment.

[0091] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A SiP power module based on circuit board layout optimization, characterized by, The substrate, the common element, the plurality of modules and the power terminal are welded on the substrate; In the design of the layout of the common element, the module and the power terminal in the substrate, the modules are connected in parallel, and all the modules are symmetrically distributed; a common area is divided at the center of the substrate, and the common element is arranged in the common area; Any of the modules comprises a plurality of components, and the positions of the modules and the components are iteratively adjusted according to the sizes of the modules and the components and the wiring conditions to obtain an optimal layout scheme, including the following steps: According to the size of the outer shape of the components included in any module, the distribution mode is combined to generate a plurality of layout schemes formed by all the components in the module; According to the wiring conditions and the junction temperature conditions of the components included in each module in any layout scheme, the internal layout cost of each module and the inter-module wiring cost under the layout scheme are obtained, and the total layout cost of the layout scheme is obtained in combination with the distribution of the components under different junction temperature levels; Based on the total layout cost of the layout scheme and the internal layout cost of the module in the layout scheme, the fitness of the layout scheme is obtained, and the positions of the modules and the components in all the layout schemes are iteratively optimized by using the fitness and combining the genetic algorithm to obtain the optimal layout scheme.

2. The SiP power module based on the layout optimization of the circuit board according to claim 1, wherein, The method for combining the distribution mode according to the size of the outer shape of the components included in any module to generate a plurality of layout schemes formed by all the components in the module includes the following specific methods: For any module, the size of the outer shape of each component in the module is obtained, and the center point of the module is taken as a positioning point; All the components are sorted in descending order according to the size of the outer shape, and the component with the largest size of the outer shape is randomly selected and distributed in the layout range, and when the selected position does not meet the constraint of the size of the outer shape of the component, the position of the positioning point of the component is adjusted until the constraint of the corresponding size of the outer shape is met, and the final position of the component is obtained; The region obtained by subtracting the region corresponding to the laid components from the region corresponding to the module is taken as a selectable region; And a positioning position is randomly selected in the selectable region, and whether the constraint is met is judged according to the size of the outer shape of the component and the size of the outer shape of the adjacent component and the size requirement of the layout position in combination with the minimum distance requirement between the components, if not, the current component position is adjusted first, and then the adjacent component position is adjusted; until all the components are laid out; The steps are repeated to generate a plurality of layout schemes, and DRC checking is performed to delete the layout schemes that do not meet the DRC requirement.

3. The SiP power module based on the layout optimization of the circuit board according to claim 1, wherein, The method for obtaining the internal layout cost of each module and the inter-module wiring cost under the layout scheme according to the wiring conditions and the junction temperature conditions of the components included in each module in any layout scheme, and obtaining the total layout cost of the layout scheme in combination with the distribution of the components under different junction temperature levels includes the following specific methods: According to the wiring condition and the junction temperature condition of each component included in each module in any layout scheme, an internal layout cost of each module and a module-to-module wiring cost under the layout scheme are obtained; The highest junction temperature of each component in any layout scheme is obtained and clustering is performed, and according to the distance between components at different highest junction temperature levels in the clustering result and in combination with the module-to-module wiring cost under the layout scheme, a total layout cost under the layout scheme is calculated.

4. The SiP power module based on the layout optimization of the circuit board according to claim 3, characterized in that, The specific method for obtaining the internal layout cost of each module and the module-to-module wiring cost under the layout scheme according to the wiring condition and the junction temperature condition of each component included in each module in any layout scheme includes: The Manhattan distance corresponding to the pins that need to be connected between all components in any module is obtained and accumulated, and the accumulated result is taken as the total wiring cost of the module; the highest junction temperature corresponding to each component in the module is obtained through simulation software, the absolute value of the difference between the highest junction temperatures of all components in the module is calculated, and the average of all the absolute values is taken as the heat dissipation cost; the product of the total wiring cost and the heat dissipation cost of the module is linearly normalized to obtain the internal layout cost of the module; Under any layout scheme, the wiring length between each module and other modules and common components is obtained and taken as the first wiring length, and the variance of all first wiring lengths is taken as the wiring consistency of the layout scheme; any module is taken as a target module, and the total number of times of wiring intersection between the target module and other modules and common components is obtained and taken as the wiring intersection number of the target module; A preset wiring parallel spacing threshold is set, the spacing between lines when the wiring between the target module and other modules and common components is parallel is obtained and taken as the wiring parallel spacing of the target module, and the total wiring length of all wiring parallel spacings less than the wiring parallel spacing threshold is obtained and taken as the parallel wiring parameter of the target module; According to the wiring intersection number and the parallel wiring parameter of all modules under the layout scheme, and by presetting different weights for the wiring intersection number and the parallel wiring parameter, the wiring complexity of the layout scheme is calculated; The module-to-module wiring cost under the layout scheme is calculated in combination with the wiring consistency and the wiring complexity.

5. The SiP power module based on the layout optimization of the circuit board according to claim 3, characterized in that, The specific method for obtaining the highest junction temperature of each component in any layout scheme and performing clustering, and for calculating the total layout cost under the layout scheme according to the distance between components at different highest junction temperature levels in the clustering result and in combination with the module-to-module wiring cost under the layout scheme includes: For any layout scheme, obtain the highest junction temperature corresponding to each component under the layout scheme through a simulation tool, use a K-Means clustering algorithm to cluster the highest junction temperatures of all components, and preset the parameter K of the K-Means clustering algorithm as 3 to obtain three clustering clusters; obtain the average value of the highest junction temperatures of all components in the three clustering clusters as the junction temperature level of the corresponding clustering cluster, and according to the order of the junction temperature levels of the clustering clusters from large to small, the corresponding clustering cluster is recorded as a high-temperature area, a normal-temperature area, and a low-temperature area respectively; Calculate the average distance between the corresponding center points of all components belonging to the high-temperature area and the normal-temperature area respectively, and record them as a high-temperature distance and a normal-temperature distance respectively; obtain the difference between the average maximum junction temperatures of all components in the high-temperature area and the normal-temperature area, and combine the difference between the high-temperature distance and the normal-temperature distance to calculate the heat concentration degree of the layout scheme; Combine the inter-module wiring cost and the heat concentration degree under the layout scheme, and preset different weights for the inter-module wiring cost and the heat concentration degree respectively, and calculate the total layout cost under the layout scheme by combining the weights.

6. The SiP power module based on the layout optimization of the circuit board according to claim 1, wherein, The total layout cost based on the layout scheme and the internal layout cost of the modules in the layout scheme are used to obtain the fitness of the layout scheme, and the positions of the modules and the components in all layout schemes are iteratively optimized by using the fitness and combining a genetic algorithm to obtain an optimal layout scheme, including the following specific methods: Encode the position coordinates of all components under any layout scheme to obtain the encoding vector corresponding to the components, obtain the fitness of the layout scheme by combining the total layout cost of the layout scheme and the internal layout cost of all modules, and use the fitness and combine the encoding vector of the components to screen and iteratively fuse the layout scheme to obtain a new layout scheme; Adjust the positions of the components with position conflicts in the new layout scheme, and obtain the fitness of the adjusted layout scheme to screen out a global rough layout scheme; Iteratively fine-tune the coordinates of the components in the global rough layout scheme to obtain an optimal layout scheme.

7. The SiP power module based on circuit board layout optimization according to claim 6, characterized in that, The encoding of the position coordinates of all components under any layout scheme to obtain the encoding vector corresponding to the components includes the following specific methods: For any layout scheme, obtain the position coordinates of all components under the layout scheme, and encode the position coordinates of all components as real numbers to obtain the coordinate encoding of each component; the coordinate encodings of all components in the layout scheme form a vector, which is used as the encoding vector of the layout scheme, and the coordinate encodings at the same position in the encoding vectors of all layout schemes correspond to the same component.

8. The SiP power module based on the layout optimization of the circuit board according to claim 6, wherein, The fitness of the layout scheme is obtained by combining the total layout cost of the layout scheme and the internal layout cost of all modules, and the new layout scheme is obtained by using the fitness and combining the encoding vector of the components to screen and iteratively fuse the layout scheme, including the following specific methods: An average of internal layout costs of all modules in a layout scheme is denoted as a total internal layout cost of the layout scheme, and a fitness of the layout scheme is obtained according to the total layout cost and the total internal layout cost and preset weights of the total layout cost and the total internal layout cost, respectively; Preset first parameter Select the one with the highest fitness The layout scheme is designated as the elite scheme, and the remaining schemes are designated as regular schemes. The elite schemes and an equal number of random regular schemes are set as the parent pool in the genetic algorithm. All schemes in the parent pool are paired to form several scheme groups. For any scheme group, the encoding vectors of the two schemes in the scheme group are obtained. A crossover factor is preset, and the encoding vectors of the two schemes in the scheme group are weighted and fused using the crossover factor to obtain the encoding vector of the new layout scheme.

9. The SiP power module based on the layout optimization of the circuit board according to claim 6, wherein, The position adjustment of the components and elements in conflict in the new layout scheme is performed, and the fitness of the adjusted layout scheme is obtained, so as to screen the overall coarse layout scheme, including the following specific method: For any new layout scheme, when any component and element in the new layout scheme is in conflict with an adjacent component and element, a relative position vector of the component and element and the conflicting component and element is calculated, and a coordinate fine adjustment is performed in the opposite direction of the vector until the minimum safety distance requirement is met; when the component and element exceeds the module layout area or the heat dissipation pad boundary, the nearest Euclidean distance from the current coordinate to the boundary of the effective area is calculated, and a translation is performed in the distance direction until the component and element is completely located in the effective area; after the repair is completed, the constraint verification is re-executed, and if there is still a rule violation, the adjustment process is repeated until all component and elements meet the constraint condition; After each iteration, all new layout schemes are sorted according to the fitness value from high to low according to the fitness function, the new layout schemes are screened according to the numerical value of the fitness, and the iteration and circulation are continued until the preset maximum iteration number is reached, and finally the layout scheme with the highest fitness is selected as the overall coarse layout scheme.

10. The SiP power module based on the layout optimization of the circuit board according to claim 6, wherein, The coordinate of the component and element in the overall coarse layout scheme is iteratively fine adjusted to obtain the optimal layout scheme, including the following specific method: For any overall coarse layout scheme, set the fine tuning range to apply random fine tuning to the coordinates of each component in the overall coarse layout scheme, while performing constraint checking and repair, to generate a number of candidate schemes, rank these schemes by fitness value, select the top schemes with the highest fitness value to form the parent pool, is a preset second parameter; The schemes in the parent pool are matched two by two to form a scheme group, the fitness of the schemes in the scheme group is obtained, and a weight coefficient is obtained through linear normalization processing, the coordinates of all corresponding components and elements in the scheme group are weighted and fused to generate a new layout scheme and supplement to the parent pool; The matching, fusion and supplement process is repeated, the parent pool is updated after each iteration, and the iteration is ended when any one of the following termination conditions is met: the preset maximum iteration number is reached; the fitness value of the optimal layout scheme does not change continuously for 3 iterations; and the optimal layout scheme is obtained.

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