Compact low-cost multi-chip Doherty power amplifier

Abstract

The invention discloses a compact low-cost multi-chip Doherty power amplifier. The compact low-cost multi-chip Doherty power amplifier comprises a power divider, a carrier input matching network, a carrier transistor, a peak phase compensation input matching network, a peak transistor, a carrier impedance inversion output matching network and a peak output matching network. Wherein the power divider, the carrier input matching network, the carrier transistor, the peak phase compensation input matching network and the peak transistor form an amplification integrated circuit chip, and the high-mobility gallium nitride transistor can provide higher output power; the carrier impedance inversion output matching network and the peak value output matching network form a matching integrated circuit chip, and the matching integrated circuit chip preferably adopts a gallium arsenide thick gold process or a ceramic thick gold process, so that the cost can be reduced, and the function integration level can be improved. According to the invention, the reliability and consistency of the amplifier are enhanced, and a one-stop high-performance radio frequency microwave amplification solution can be provided for consumer electronics and communication equipment.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of microwave integrated circuits, and particularly relates to a compact low-cost multi-chip Doherty power amplifier. BACKGROUND

[0002] With the development of communication systems, complex modulation signals in modern communication systems often maintain a high peak-to-average ratio. In order to ensure the integrity of signal transmission, the power amplifier needs to work in a region with a high power backoff amount, and the modern communication system requires the power amplifier to have high working efficiency in the power backoff region.

[0003] The Doherty power amplifier is an amplifier based on load modulation, which can maintain high efficiency in the saturation operating point and a certain power backoff range. The traditional Doherty power amplifier design is usually a single-chip solution or a transistor die + PCB matching solution.

[0004] However, the single-chip solution has high integration, but has the problems of high cost and low efficiency. The transistor die + PCB matching solution has a relatively large size and poor consistency, and thus there is an urgent need to provide a Doherty power amplifier with low cost and high integration. SUMMARY

[0005] The purpose of the application is to provide a compact low-cost multi-chip Doherty power amplifier. High-frequency high-power output is realized through a high-mobility gallium nitride process, and the matching integrated circuit chip effectively reduces circuit loss and reduces cost through a thick gold process, and the functional integration is improved.

[0006] Technical scheme: The compact low-cost multi-chip Doherty power amplifier comprises a power divider, a carrier input matching network, a carrier transistor pHMET1, a peak phase compensation input matching network, a peak transistor pHMET2, a carrier impedance inversion output matching network, and a peak output matching network. The power divider, the carrier input matching network, the carrier transistor pHMET1, the peak phase compensation input matching network, and the peak transistor pHMET2 constitute an amplification integrated circuit chip, and the carrier impedance inversion output matching network and the peak output matching network constitute a matching integrated circuit chip. The input end of the amplification integrated circuit chip is a radio frequency signal input end, the amplification integrated circuit chip is connected with the matching integrated circuit chip, and the output end of the matching integrated circuit chip is a radio frequency signal output end.

[0007] Further, the output end of the power divider is connected with the input end of the carrier input matching network, the carrier input matching network, the carrier transistor pHMET1, and the carrier impedance inversion output matching network are sequentially connected in series, and the carrier power amplifier is formed. The power divider lower output end is connected with a peak phase compensation input matching network input end, the peak phase compensation input matching network, a peak transistor pHMET2 and a peak output matching network are cascaded in sequence to form a peak power amplifier; The output end of the carrier impedance inverter output matching network and the output end of the peak output matching network are connected as a radio frequency output of the Doherty power amplifier.

[0008] Further, the amplification integrated circuit chip adopts a gallium nitride MMIC process.

[0009] Further, the matching integrated circuit chip adopts a thick gold gallium arsenide process or a thick gold ceramic process.

[0010] Further, the gold layer thickness of the matching integrated circuit chip is 10-15 um.

[0011] Further, the carrier input matching network is a carrier grid DC bias, impedance matching multi-function fusion design.

[0012] Further, the peak phase compensation input matching network is a phase compensation, peak grid DC bias, impedance matching multi-circuit function design.

[0013] Further, the carrier impedance inverter output matching network is an impedance inverter, carrier drain DC bias, impedance matching multi-function fusion design.

[0014] Further, the peak output matching network is a peak drain DC bias, impedance matching multi-function fusion design.

[0015] Further, the power divider adopts a Wilkinson power divider, the power division ratio is 1:1, and the input end is a radio frequency signal input end.

[0016] Advantages: compared with the prior art, the amplification integrated circuit chip of the present application realizes high frequency and high power output through a high mobility gallium nitride process, and the matching integrated circuit chip effectively reduces circuit loss through a thick gold process; compared with the existing PCB scheme, the size of the present application can be reduced by nearly 10 times, the cost is significantly reduced, the functional integration degree is improved, compared with the existing single-chip scheme, the efficiency can be improved by 3-5%, and at the same time, the scheme can enhance the chip reliability and consistency, and provides a "one-stop" high-performance radio frequency microwave amplification solution for consumer electronics and communication equipment. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1This is a schematic diagram of the three-dimensional structural arrangement in an embodiment of the present invention; in the figure, there is a power divider 101, a carrier input matching network 102, a carrier transistor pHMET1 103, a peak phase compensation input matching network 104, a peak transistor pHMET2 105, a carrier impedance inverter output matching network 201, a peak output matching network 202, an amplifier integrated circuit chip 10, and a matching integrated circuit chip 20.

[0018] Figure 2 This is a schematic diagram of the Doherty circuit structure in an embodiment of the present invention; Figure 3 This is a schematic diagram showing the differences between common MMIC processes and the thick gold MMIC process in the embodiments of this invention; Figure 4 This is a size comparison diagram between the PCB solution and the embodiment of the present invention; Figure 5 The gain curve of the compact multi-chip low-cost Doherty power amplifier according to an embodiment of the present invention; Figure 6 The PAE efficiency curve of the compact multi-chip low-cost Doherty power amplifier according to an embodiment of the present invention is shown. Detailed Implementation

[0019] The technical solution of the present invention will be further described below with reference to the accompanying drawings.

[0020] The overall structure of the compact, multi-chip, low-cost Doherty power amplifier in this embodiment is referenced. Figure 1 This includes: a power divider, a carrier input matching network, a carrier transistor pHMET1, a peak phase compensation input matching network, a peak transistor pHMET2, a carrier impedance inverter output matching network, and a peak output matching network. The power divider, carrier input matching network, carrier transistor pHMET1, peak phase compensation input matching network, and peak transistor pHMET2 constitute an amplifier integrated circuit chip, while the carrier impedance inverter output matching network and peak output matching network constitute a matching integrated circuit chip.

[0021] In this embodiment, the power divider is a Wilkinson power divider with a power division ratio of 1:1 and an input terminal for radio frequency signals. The upper output of the power divider is connected to the input of the carrier input matching network. The carrier input matching network, carrier transistor pHMET1, and carrier impedance inverter output matching network are cascaded in sequence to form a carrier power amplifier. The lower output of the power divider is connected to the input of the peak phase compensation input matching network. The peak phase compensation input matching network, peak transistor pHMET2, and peak output matching network are cascaded in sequence to form a peak power amplifier. The output end of the carrier impedance inverting output matching network and the output end of the peak output matching network are connected as the radio frequency output of the Doherty power amplifier.

[0022] The amplification integrated circuit chip and the matching integrated circuit chip constitute a compact multi-chip low-cost Doherty power amplifier.

[0023] In the embodiment, the amplification integrated circuit chip selects a 0.25 um gallium nitride MMIC process of Nanjing Electronic Device Research Institute, and the transistor of the high mobility gallium nitride MMIC process can provide a power density of 6 W / mm, and meanwhile can provide high working efficiency.

[0024] The matching integrated circuit chip preferably selects a gallium arsenide thick gold process or a ceramic thick gold process to reduce the cost, and the thickness of the gold layer of the transmission line should be 10 um to 15 um, so that the transmission loss caused by the skin effect can be significantly reduced. Figure 3 The thick gold MMIC process in the embodiment is different from a common MMIC process, and compared with the common MMIC process, the thick gold MMIC process removes the buffer layer, the channel layer, the barrier layer and the SGD (source gate drain) contact ohm, and only retains the substrate layer and the gold layer of the transmission line, so that the process flow is greatly simplified and the cost is reduced.

[0025] The carrier input matching network is designed to have multiple functions of carrier gate DC bias and impedance matching, the peak phase compensation input matching network is designed to have multiple circuit functions of phase compensation, peak gate DC bias and impedance matching, the carrier impedance inverting output matching network is designed to have multiple functions of impedance inverting, carrier drain DC bias and impedance matching, and the peak output matching network is designed to have multiple functions of peak drain DC bias and impedance matching.

[0026] Through the above structural design, the compact multi-chip low-cost Doherty power amplifier can maintain high integration, Figure 4 The size of the compact multi-chip low-cost Doherty power amplifier in the embodiment is only 3.8 mm*4 mm, and the size of the Doherty power amplifier of the same frequency band in the PCB scheme is 26.5 mm*26 mm, so the size of the compact multi-chip low-cost Doherty power amplifier in the embodiment is reduced by nearly 45 times, and the size is close to that of the single-chip scheme, the integration is high, and the cost is also reduced.

[0027] Figure 5 The gain and power curve of the compact multi-chip low-cost Doherty power amplifier of the embodiment of the present application is shown in the figure, and it can be seen that the saturation power is greater than 38dBm and the saturation power gain is greater than 24dB and the backoff gain is greater than 25dB at the three frequency points of 1.8GHz, 1.9GHz and 2.0GHz.

[0028] Figure 6 The PAE efficiency curve of the compact multi-chip low-cost Doherty power amplifier of the embodiment of the present application is shown in the figure, and it can be seen that the saturation PAE efficiency is greater than 62% and the PAE efficiency at the power backoff of 6dB is greater than 50% at the three frequency points of 1.8GHz, 1.9GHz and 2.0GHz.

[0029] Finally, it should be noted that: the above embodiments only illustrate the technical idea of the present application, and cannot limit the protection scope of the present application. The above-described embodiments with reference to the drawings are only used to illustrate the present application and not to limit the scope of the present application. Any modification or equivalent replacement of the embodiments without departing from the spirit and scope of the present application should be covered within the scope of the present application. Any modification made according to the technical idea of the present application on the basis of the technical solution falls within the scope of the present application.

Claims

1. A compact low cost multi-chip Doherty power amplifier characterized by, It comprises: a power divider (101), a carrier input matching network (102), a carrier transistor pHMET1 (103), a peak phase compensation input matching network (104), a peak transistor pHMET2 (105), a carrier impedance inverter output matching network (201) and a peak output matching network (202); wherein the power divider (101), the carrier input matching network (102), the carrier transistor pHMET1 (103), the peak phase compensation input matching network (104) and the peak transistor pHMET2 (105) constitute an amplification integrated circuit chip (10), and the carrier impedance inverter output matching network (201) and the peak output matching network (202) constitute a matching integrated circuit chip (20); the input end of the amplification integrated circuit chip (10) is a radio frequency signal input end; the amplification integrated circuit chip (10) is connected with the matching integrated circuit chip (20); and the output end of the matching integrated circuit chip (20) is a radio frequency signal output end.

2. A compact low-cost multi-chip Doherty power amplifier according to claim 1, characterized in that, The output end of the power divider (101) is connected with the input end of the carrier input matching network (102), the carrier input matching network (102), the carrier transistor pHMET1 (103) and the carrier impedance inverter output matching network (201) are sequentially connected in cascade to constitute a carrier power amplifier; the input end of the peak phase compensation input matching network (104) is connected with the output end of the power divider (101), the peak phase compensation input matching network (104), the peak transistor pHMET2 (105) and the peak output matching network (202) are sequentially connected in cascade to constitute a peak power amplifier; the output end of the carrier impedance inverter output matching network (201) is connected with the output end of the peak output matching network (202) to form a radio frequency output of the Doherty power amplifier.

3. The compact low-cost multi-chip Doherty power amplifier of claim 1, wherein, The amplification integrated circuit chip (10) adopts a gallium nitride MMIC process.

4. The compact low-cost multi-chip Doherty power amplifier of claim 1, wherein, The matching integrated circuit chip (20) adopts a gallium arsenide thick gold process or a ceramic thick gold process.

5. A compact low-cost multi-chip Doherty power amplifier according to claim 4, characterized in that, The thickness of the gold layer of the matching integrated circuit chip (20) is 10-15 um.

6. The compact low-cost multi-chip Doherty power amplifier of claim 1, wherein, The carrier input matching network (102) is designed to have multiple functions of carrier grid DC bias, impedance matching and the like.

7. The compact low-cost multi-chip Doherty power amplifier of claim 1, wherein, The peak phase compensation input matching network (104) is designed to have multiple circuit functions of phase compensation, peak grid DC bias and impedance matching.

8. The compact low-cost multi-chip Doherty power amplifier of claim 1, wherein, The carrier impedance inverter output matching network (201) is designed to have multiple functions of impedance inversion, carrier drain DC bias and impedance matching.

9. The compact low-cost multi-chip Doherty power amplifier of claim 1, wherein, The peak output matching network (202) is designed to have multiple functions of peak drain DC bias and impedance matching.

10. The compact low-cost multi-chip Doherty power amplifier of claim 1, wherein, The power divider (101) adopts a Wilkinson power divider, the power division ratio is 1:1, and the input end is a radio frequency signal input end.

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