Multifunctional computing circuit

By designing a multifunctional computing circuit that shares addressing logic and computing units, the functions of affine transformation and mesh sampling are realized, solving the problems of large resource consumption and low reusability in the existing technology, and improving computing efficiency and versatility.

CN121860840APending Publication Date: 2026-04-14SHANGHAI FUDAN MICROELECTRONICS GROUP
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Patent Information

Application Number
CN202411436055.7
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2024-10-14
Publication Date
2026-04-14

AI Technical Summary

Technical Problem

In existing technologies, affine transformation and mesh sampling functions are implemented using separate circuits, resulting in high resource consumption, low reusability, high design complexity, and poor versatility.

Method used

Design a multifunctional computing circuit that uses the same set of addressing logic and computing units. It implements affine transformation and grid sampling functions through parameter configuration and performs calculations using the same set of circuits, including parameter configuration unit, read addressing unit, mapping unit, multiply-accumulate calculation unit and write addressing unit. It supports different interpolation methods and data types.

Benefits of technology

It improves the versatility and resource reusability of affine transformation and mesh sampling, reduces resource consumption, improves interpolation calculation speed and efficiency, and supports a variety of application scenarios and data types.

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Abstract

The invention discloses a multifunctional calculation circuit which comprises a parameter configuration unit used for performing parameter configuration, and configured parameters comprise an addressing base address and an interpolation mode; the read addressing unit is used for generating a read request to a read bus, reading data from an external memory according to the addressing base address, and caching the read data; the data comprises input feature map data and / or input grid data; the first-round addressing address is an addressing base address; the mapping unit is used for performing coordinate transformation according to the cached grid data, and determining adjacent point pixel values and coefficients thereof for interpolation calculation according to the obtained original image coordinates; the multiply-accumulate calculation unit is used for carrying out multiply-accumulate calculation on the adjacent point pixel value and the coefficient thereof determined by the mapping unit to obtain an interpolation; and the write addressing unit is used for writing the interpolation back to the external memory. According to the scheme, the affine transformation function and the grid sampling function can be flexibly achieved, resources are saved, and the interpolation calculation speed in the affine transformation is increased.
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