Dimm module testing circuit, device, and method

Abstract

This invention discloses a DIMM module testing circuit, device, and method, relating to the field of DIMM modules. The DIMM module testing circuit includes: a noise voltage generation module for generating PMIC input noise voltage and PMIC output noise voltage; a first noise voltage output module, whose second input terminal is connected to the first noise voltage output terminal, for interfering with the PMIC standard input voltage input terminal based on the PMIC input noise voltage to generate an input disturbance voltage and outputting it to the PMIC under test; and a second noise voltage output module, whose second input terminal is connected to the second noise voltage output terminal, for interfering with the DRAM power supply voltage output by the PMIC under test based on the PMIC output noise voltage to generate an output disturbance voltage to the DRAM under test. This invention is beneficial for simulating input and output voltage changes under complex and variable real-world scenarios.

Description

Technical Field

[0001] This invention relates to the field of DIMM module technology, and more particularly to DIMM module testing circuits, equipment and methods. Background Technology

[0002] Currently, the industry generally considers DRAM chips to be ideally consistent components. Before leaving the factory, some DRAM chips operate normally at the nominal voltage. However, in reality, various noises exist, causing the DRAM's operating voltage to fluctuate around the standard voltage. Even slight voltage fluctuations can cause the DRAM chip to malfunction, which is clearly not what users expect.

[0003] In existing technologies, CN120148599A tests SRAM, and the voltage generated by the threshold voltage test circuit changes linearly. This approach cannot test DIMMs or DRAMs. Therefore, it is necessary to develop a DIMM module test circuit that allows the noise voltage generated by the noise voltage generation circuit to have a controllable period frequency, amplitude, and timing, and can be controlled by commands throughout the process through a noise control module. Summary of the Invention

[0004] The main objective of this invention is to provide a DIMM module testing circuit, device, and method, which aims to simulate the changes in PMIC input and output voltages under complex and ever-changing real-world scenarios, making the test results closer to actual usage conditions.

[0005] To achieve the above objectives, this invention proposes a DIMM module test circuit, wherein the DIMM module includes a PMIC under test and a memory chip under test, and the DIMM module test circuit includes:

[0006] The PMIC standard input voltage input terminal is used to connect the PMIC standard input voltage.

[0007] A noise voltage generation module has a first noise voltage output terminal and a second noise voltage output terminal. The noise voltage generation module is used to generate PMIC input noise voltage and PMIC output noise voltage.

[0008] A first noise voltage output module has a first input terminal connected to the PMIC standard input voltage input terminal, and a second input terminal connected to the first noise voltage output terminal. The output terminal of the first noise voltage output module is used to connect to the PMIC under test. The first noise voltage output module is used to interfere with the PMIC standard input voltage connected to the PMIC standard input voltage input terminal according to the PMIC input noise voltage, generate an input disturbance voltage, and output it to the PMIC under test.

[0009] The second noise voltage output module has a first input terminal for connecting to the output terminal of the PMIC under test, and a second input terminal for connecting to the second noise voltage output terminal. The output terminal of the second noise voltage output module is used to connect to the memory chip under test. The second noise voltage output module is used to interfere with the DRAM power supply voltage output by the PMIC under test according to the noise voltage output by the PMIC, and generate an output disturbance voltage to the DRAM under test.

[0010] In one embodiment, the magnitude of the PMIC input noise voltage and the magnitude of the PMIC output noise voltage output by the noise voltage generation module are adjustable; and / or the frequency and amplitude of the PMIC input noise voltage and the PMIC output noise voltage output by the noise voltage generation module are adjustable.

[0011] In one embodiment, the DIMM module test circuit further includes a noise generation control module, which is connected to the noise voltage generation module;

[0012] The noise generation control module is used to control the noise voltage generation module to generate the corresponding PMIC input noise voltage and PMIC output noise voltage in a predetermined timing sequence according to the received test command.

[0013] In one embodiment, the predetermined timing includes at least:

[0014] The PMIC input noise voltage is generated independently and periodically.

[0015] The PMIC output noise voltage is generated independently and periodically.

[0016] Synchronously generate periodically varying PMIC input noise voltage and periodically varying PMIC output noise voltage.

[0017] Time-division multiplexing generates non-periodic PMIC input noise voltage and non-periodic PMIC output noise voltage;

[0018] Generate aperiodic PMIC input noise voltage independently;

[0019] Generates a non-periodic PMIC output noise voltage independently;

[0020] Synchronously generate non-periodic PMIC input noise voltage and non-periodic PMIC output noise voltage.

[0021] The PMIC input noise voltage and the PMIC output noise voltage are generated in a time-division manner, which are non-periodic.

[0022] In one embodiment, the PMIC input noise voltage fluctuates around the PMIC standard input voltage; the PMIC output noise voltage fluctuates around the DRAM power supply voltage output by the PMIC.

[0023] In one embodiment, the first noise voltage output module includes a first summing operational amplifier, the first input terminal of the first summing operational amplifier is connected to the standard input voltage access terminal of the PMIC, the second input terminal of the first summing operational amplifier is connected to the first noise voltage output terminal of the noise voltage generation module, and the output terminal of the first summing operational amplifier is used to connect to the PMIC under test.

[0024] In one embodiment, the second noise voltage output module includes a second summing operational amplifier, which is connected to the output terminal of the PMIC under test, a second input terminal of the second summing operational amplifier is connected to the second noise voltage output terminal of the noise voltage generation module, and the output terminal of the second summing operational amplifier is connected to the DRAM under test.

[0025] In one embodiment, there are multiple second noise voltage output modules. The first input terminal of each second noise voltage output module is connected to the output terminal of the PMIC under test. The second input terminal of each second noise voltage output module is connected to a second noise voltage output terminal. The output terminal of each second noise voltage output module is used to connect to a DRAM under test.

[0026] The present invention also proposes a DIMM module testing device, including a testing machine and a DIMM module testing circuit as described above;

[0027] The test terminal of the test equipment is used to connect to the memory chip under test. The test equipment is used to acquire the dynamic fluctuation voltage of the memory chip under test and determine the operating voltage range of the memory chip under test based on the dynamic fluctuation voltage.

[0028] This invention also proposes a DIMM module testing method, which uses the DIMM module testing circuit described above; the DIMM module test includes a noise voltage generation module, a first noise voltage output module, and a second noise voltage output module; the DIMM module testing method includes:

[0029] Obtain a test command, and control the noise voltage generation module to generate corresponding PMIC input noise voltage and PMIC output noise voltage according to the obtained test command in a predetermined timing sequence; the predetermined timing sequence includes at least:

[0030] The PMIC input noise voltage is generated independently and periodically.

[0031] The PMIC output noise voltage is generated independently and periodically.

[0032] Synchronously generate periodically varying PMIC input noise voltage and periodically varying PMIC output noise voltage.

[0033] Time-division multiplexing generates non-periodic PMIC input noise voltage and non-periodic PMIC output noise voltage;

[0034] Generate aperiodic PMIC input noise voltage independently;

[0035] Generates a non-periodic PMIC output noise voltage independently;

[0036] Synchronously generate non-periodic PMIC input noise voltage and non-periodic PMIC output noise voltage.

[0037] The PMIC input noise voltage and the PMIC output noise voltage are generated in a time-division manner, which are non-periodic.

[0038] The present invention also proposes a manufacturing apparatus, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the DIMM module test circuit as described above.

[0039] This invention can simulate various external noise interferences and dynamically adjust the input and output voltages of the PMIC chip that directly powers the DRAM through the noise voltage generation module 10. Specifically, it dynamically adjusts the voltage input to the PMIC and the voltage output to the DRAM, testing the operating status of the DRAM and PMIC under different operating voltages. This not only tests the operating status of the DRAM under different voltage fluctuations but also detects the performance of the PMIC chip. Compared to statically adjusting the PMIC output voltage, simulating external noise to the PMIC causes the actual input voltage of the DRAM to fluctuate continuously, expanding the testing range. One test is equivalent to multiple static PMIC voltage adjustments, resulting in higher testing efficiency. Attached Figure Description

[0040] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0041] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a schematic diagram of the circuit structure of an embodiment of the DIMM module test circuit of the present invention;

[0043] Figure 2 for Figure 1 A schematic diagram of the circuit structure provided in one embodiment of the noise voltage generation module;

[0044] Figure 3 This is a schematic diagram illustrating the workflow of each circuit module provided in an embodiment of the DIMM module test circuit of the present invention.

[0045] Figure 4 This is a test eye diagram provided for an embodiment of the DIMM module testing equipment of the present invention;

[0046] Figure 5 This is a schematic diagram of the hardware operating environment involved in the DIMM module testing device in this embodiment of the invention.

[0047] The objectives, functional characteristics, and optimal time periods of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0048] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of the present invention and are not intended to limit the present invention.

[0049] To better understand the technical solution of the present invention, a detailed description will be provided below in conjunction with the accompanying drawings and specific embodiments.

[0050] A DIMM (Dual In-line Memory Module) consists of a PCB (Printed Circuit Board), memory chips mounted on the PCB, and a power management IC (PMIC) mounted on the PCB to supply power to the memory chips. Each memory module can have a different number of memory chips depending on its size. These memory chips can be DRAM (Dynamic Random Access Memory), which is the core component of the DIMM module. Before leaving the factory, some DRAM chips, while functioning normally at their nominal voltage, may fail under slight voltage fluctuations. ATE (Automatic Test Equipment) testing equipment is typically used to expose these "gray area" chips early through high and low voltage boundary testing, preventing them from causing field failures after entering the market. Some existing PMIC chips support digitally programmable output voltage, which can be written to internal registers (such as the VOUT_COMMAND register) via I²C / I³C interfaces, allowing for static adjustment of the target voltage and supporting fine adjustment in mV units. While this allows for manual adjustment of the target output voltage, the adjustment is static, and the output voltage cannot fluctuate dynamically. It cannot simulate real-world noise and therefore cannot quickly and effectively test the limits of voltage fluctuations that the DRAM can tolerate.

[0051] To solve the above problems, refer to Figure 1 In one embodiment of the present invention, the DIMM module test circuit includes:

[0052] The PMIC standard input voltage input terminal is used to connect the PMIC standard input voltage.

[0053] The noise voltage generation module 10 has a first noise voltage output terminal and a second noise voltage output terminal. The noise voltage generation module 10 is used to generate PMIC input noise voltage and PMIC output noise voltage.

[0054] A first noise voltage output module 20 has a first input terminal connected to the PMIC standard input voltage input terminal, and a second input terminal connected to the first noise voltage output terminal. The output terminal of the first noise voltage output module 20 is used to connect to the PMIC under test. The first noise voltage output module 20 is used to interfere with the PMIC standard input voltage connected to the PMIC standard input voltage input terminal according to the PMIC input noise voltage, generate an input disturbance voltage, and output it to the PMIC under test.

[0055] The second noise voltage output module 30 has a first input terminal for connecting to the output terminal of the PMIC under test, and a second input terminal for connecting to the second noise voltage output terminal. The output terminal of the second noise voltage output module 30 is used to connect to the memory chip under test. The second noise voltage output module 30 is used to interfere with the DRAM power supply voltage output by the PMIC under test according to the noise voltage output by the PMIC, and generate an output disturbance voltage to the DRAM under test.

[0056] In this embodiment, the PCB of the DIMM module typically houses a PMIC and multiple memory chips. The PMIC steps down and filters the incoming power supply voltage before outputting it to each memory chip, providing the necessary voltage for operation. Each memory chip has multiple power pins, each connected to a power supply from a PMIC, such as VDD, VDDQ, VPP, and VSS. The power supply to the memory chips is configured in parallel; the PMIC provides different power rails to the DRAMs through multiple independent step-down switching regulators (e.g., SWA, SWB, SWC). Each power rail is connected in parallel to the corresponding power supply pin of each DRAM chip to ensure a consistent power supply voltage for all DRAM chips. While DRAM chips typically operate normally under standard voltage, in reality, unstable power supply voltage, deteriorating operating environment, excessively high ambient temperature, oxidation of memory contacts, or poor contact can cause various types of noise in the memory module. This results in the DRAM's operating voltage fluctuating around the standard voltage. Therefore, the DRAM needs to be tested before shipping to simulate various external noises to ensure it still functions correctly.

[0057] Noise typically exists at both the input and output voltages of a PMIC. The output voltage, generated by the PMIC itself or other factors, directly affects the power supply to the DRAM. Therefore, its voltage fluctuations directly impact DRAM performance, having the greatest impact on DRAM operation. This method avoids the need for frequent digital programming to configure the output voltage value and allows for the rapid acquisition of multiple dynamically fluctuating output voltage values, efficiently testing the DRAM's operating status under different voltages. Secondly, PMIC input voltage noise is often caused by unstable power supply voltage, electrostatic interference, etc., and the input voltage also affects the PMIC's output voltage. PMIC chips perform best at standard input voltages; voltages below the standard may result in insufficient output voltage, while voltages above the standard may damage the PMIC.

[0058] To address the aforementioned issues, this embodiment employs a noise voltage generation module 10 to generate PMIC input noise voltage and PMIC output noise voltage, wherein, referring to... Figure 2 The noise voltage generation module 10 can be implemented using an avalanche noise source 13, a variable gain amplifier 14, and a DC blocking coupler 15. The avalanche noise source 13 can be used to generate PMIC input noise voltage and PMIC output noise voltage, mainly utilizing the random current fluctuations generated by semiconductor devices during avalanche breakdown, thereby outputting a noise voltage signal with wide spectrum characteristics. The variable gain amplifier 14 can dynamically adjust the signal gain to adapt to changes in the amplitude of the input signal, and output the amplified PMIC input noise voltage and PMIC output noise voltage to the DC blocking coupler 15, which then couples to the first noise voltage output module 20 and the second noise voltage output module 30, respectively.

[0059] The noise voltage generation module 10 may include a first noise voltage generation module 11 and a second noise voltage generation module 12. The output terminal of the first noise voltage generation module 11 is connected to the first noise voltage output module 20, and the output terminal of the second noise voltage generation module 12 is connected to the second noise voltage output module 30. The first noise voltage generation module 11 is used to generate the PMIC input noise voltage, and the second noise voltage generation module 12 is used to generate the PMIC output noise voltage.

[0060] The PMIC input noise voltage is superimposed on the PMIC's power input terminal through the first noise voltage output module 20. This means the first noise voltage output module 20 interferes with the standard PMIC input voltage at the standard input voltage input terminal, generating an input disturbance voltage which is output to the power input terminal of the PMIC under test. This causes noise interference with the PMIC's operating voltage, simulating the input noise of the PMIC's power supply and affecting its normal operation, thus verifying the PMIC's anti-interference capability. The PMIC output noise voltage is superimposed on the PMIC's power output terminal through the second noise voltage output module 30 and output to the DRAM. This means the second noise voltage output module 30 interferes with the DRAM's power supply voltage at the DRAM power supply voltage input terminal, generating an output disturbance voltage which is output to the power input terminal of the DRAM under test. This noise interference also simulates the input noise of the DRAM's power supply. The actual PMIC input and output voltages can then fluctuate around the standard input and output voltages, creating a relatively realistic scenario. This not only tests the DRAM's operation under voltage fluctuations but also verifies the PMIC chip's anti-interference capability. When the PMIC provides dedicated power to the DRAM, the PMIC and DRAM can be considered as a whole. The PMIC input noise voltage (simulated noise 1) and PMIC output noise voltage (simulated noise 2) generated by the noise voltage generation module 10 simulate the complex and ever-changing scenarios in reality. The test results are closer to the actual usage situation, and the simulated noise test is necessary.

[0061] This invention can simulate various external noise interferences and dynamically adjust the input and output voltages of the PMIC chip that directly powers the DRAM through the noise voltage generation module 10. Specifically, it dynamically adjusts the voltage input to the PMIC and the voltage output to the DRAM, testing the operating status of the DRAM and PMIC under different operating voltages. This not only tests the operating status of the DRAM under different voltage fluctuations but also detects the performance of the PMIC chip. Compared to statically adjusting the PMIC output voltage, simulating external noise to the PMIC causes the actual input voltage of the DRAM to fluctuate continuously, expanding the testing range. One test is equivalent to multiple static PMIC voltage adjustments, resulting in higher testing efficiency.

[0062] Reference Figure 1 In one embodiment, the magnitude of the PMIC input noise voltage and the magnitude of the PMIC output noise voltage output by the noise voltage generation module 10 are adjustable; and / or the frequency of the PMIC input noise voltage and the PMIC output noise voltage output by the noise voltage generation module 10 are adjustable.

[0063] Since the input and output voltages are variable in real-world applications, in this embodiment, in order to simulate the variable input and output voltages, the noise voltage generation module 10 can adjust the magnitude and frequency of the PMIC input noise voltage and the PMIC output noise voltage in real time, thereby simulating the changes in PMIC input and output voltages under complex and variable real-world scenarios, making the test results closer to real-world usage.

[0064] Reference Figure 1 In one embodiment, the DIMM module test circuit further includes a noise generation control module 40, which is connected to the noise voltage generation module 10.

[0065] The noise generation control module 40 is used to control the noise voltage generation module 10 to generate corresponding PMIC input noise voltage and PMIC output noise voltage in a predetermined timing sequence according to the received test command.

[0066] The predetermined timing sequence includes at least the following:

[0067] The PMIC input noise voltage is generated independently and periodically.

[0068] The PMIC output noise voltage is generated independently and periodically.

[0069] Synchronously generate periodically varying PMIC input noise voltage and periodically varying PMIC output noise voltage.

[0070] Time-division multiplexing generates non-periodic PMIC input noise voltage and non-periodic PMIC output noise voltage;

[0071] Generate aperiodic PMIC input noise voltage independently;

[0072] Generates a non-periodic PMIC output noise voltage independently;

[0073] Synchronously generate non-periodic PMIC input noise voltage and non-periodic PMIC output noise voltage.

[0074] The PMIC input noise voltage and the PMIC output noise voltage are generated in a time-division manner, which are non-periodic.

[0075] In this embodiment, the noise generation control module 40 controls the noise generation module to generate corresponding PMIC input noise voltage and PMIC output noise voltage based on the received noise period / frequency, amplitude, and potential energy control commands. This simulates different application scenarios, such as fluctuations only in the PMIC standard input voltage connected to the PMIC power input terminal, fluctuations only in the DRAM power supply voltage output from the PMIC to the DRAM, synchronous fluctuations in the PMIC standard input voltage and DRAM power supply voltage, or time-sharing fluctuations in the PMIC standard input voltage and DRAM power supply voltage, i.e., fluctuations occurring sequentially. When fluctuations occur in the PMIC standard input voltage and DRAM power supply voltage, they can be periodic or non-periodic instantaneous fluctuations.

[0076] Combination Figure 3 , Figure 3 The diagram illustrates the workflow of each circuit module. In practical applications, the noise generation control module 40 configures the timing, period, and amplitude required for the first noise voltage generation module 11 to generate noise voltage, and configures the timing, period, and amplitude required for the second noise voltage generation module 12 to generate noise voltage, based on the received noise period / frequency, amplitude, and potential energy control commands. The first noise voltage generation module 11, under the control of the noise generation control module 40, generates a fluctuating PMIC input noise voltage and outputs it to the PMIC under test. The second noise voltage generation module 12, also under the control of the noise generation control module 40, generates a fluctuating PMIC output noise voltage and outputs it to the DRAM under test. Thus, the noise voltage generation module 10 dynamically adjusts the input and output voltages of the PMIC chip that directly powers the DRAM, i.e., dynamically adjusts the voltage input to the PMIC and the voltage output to the DRAM, testing the operating status of the DRAM and PMIC under different operating voltages.

[0077] In one embodiment, the PMIC input noise voltage fluctuates continuously around the PMIC standard input voltage; the PMIC output noise voltage fluctuates continuously around the DRAM power supply voltage output by the PMIC.

[0078] In this embodiment, when the PMIC standard input voltage fluctuates, it can fluctuate around an intermediate value, for example, when the PMIC standard input voltage is 12V, it can fluctuate around 12V. Specifically, the PMIC input noise voltage value can be adjusted in 0.1V steps. For example, in an analog application scenario, the voltage output to the PMIC power input terminal fluctuates between 11.9V, 12V, and 12.1V. In the next adjustment, the PMIC input noise voltage can be adjusted to fluctuate between 11.8V, 12V, and 12.2V. Furthermore, the frequency of periodic changes can also be adjusted, for example, it can be 100Hz or 100kHz. When the DRAM supply voltage fluctuates, it can fluctuate around an intermediate value, such as 1.1V. Specifically, it can fluctuate around 1.1V in 0.05V increments to adjust the PMIC input noise voltage. For example, in an analog application, the voltage output to the PMIC's power input might fluctuate between 1.05V, 1.1V, and 1.15V. In the next adjustment, the PMIC input noise voltage could fluctuate between 1.0V, 1.1V, and 1.2V. Furthermore, the frequency of these periodic changes can also be adjusted, for example, to 100Hz or 100kHz.

[0079] Reference Figure 1 In one embodiment, the first noise voltage output module 20 includes a first summing operational amplifier, the first input terminal of the first summing operational amplifier is connected to the standard input voltage access terminal of the PMIC, the second input terminal of the first summing operational amplifier is connected to the first noise voltage output terminal of the noise voltage generation module 10, and the output terminal of the first summing operational amplifier is used to access the PMIC under test.

[0080] In this embodiment, the second input terminal of the first summing operational amplifier serves as the reference signal input terminal. Through the DC blocking coupler 15, such as a capacitor, a varying PMIC input noise voltage can be connected. When the PMIC standard input voltage is used as the intermediate value and fluctuates up and down, the connected PMIC input noise voltage may be greater than or less than the PMIC standard input voltage. By adjusting the PMIC input noise voltage, the voltage value output by the first summing operational amplifier is in a fluctuating state, rather than being a stable PMIC standard input voltage.

[0081] Reference Figure 1In one embodiment, the second noise voltage output module 30 includes a second summing operational amplifier, which is connected to the output terminal of the PMIC under test, the second input terminal of the second summing operational amplifier is connected to the second noise voltage output terminal of the noise voltage generation module 10, and the output terminal of the second summing operational amplifier is connected to the DRAM under test.

[0082] In this embodiment, the second input terminal of the second summing operational amplifier serves as a reference signal input terminal and can be connected to a varying PMIC input noise voltage. When the PMIC input noise voltage fluctuates around the DRAM power supply voltage as an intermediate value, the PMIC input noise voltage connected to it may be greater than or less than the DRAM power supply voltage. By adjusting the PMIC input noise voltage, the voltage value output by the first summing operational amplifier is in a fluctuating state, rather than being a stable DRAM power supply voltage.

[0083] In one embodiment, there are multiple second noise voltage output modules 30. The first input terminal of each second noise voltage output module 30 is connected to the output terminal of the PMIC under test, the second input terminal of each second noise voltage output module 30 is connected to a second noise voltage output terminal, and the output terminal of each second noise voltage output module 30 is used to connect to a DRAM under test.

[0084] In this embodiment, the second noise voltage output module 30 can be adjusted according to the number of memory chips set in the memory module. For example, if the number of memory chips set in the memory module is 8, the number of second noise voltage output modules 30 is 8; if the number of memory chips set in the memory module is 16, the number of second noise voltage output modules 30 is 16. Furthermore, the PMIC output noise voltage and frequency output by the noise voltage generation module 10 to each second noise voltage output module 30 can be the same, different, or partially the same, to simulate abnormal changes in the DRAM power supply voltage during the actual operation of the DIMM module.

[0085] This invention also proposes a DIMM module testing method, which uses the DIMM module testing circuit described above; the DIMM module test includes a noise voltage generation module, a first noise voltage output module, and a second noise voltage output module; the DIMM module testing method includes:

[0086] Obtain a test command, and control the noise voltage generation module to generate corresponding PMIC input noise voltage and PMIC output noise voltage according to the obtained test command in a predetermined timing sequence; the predetermined timing sequence includes at least:

[0087] The PMIC input noise voltage is generated independently and periodically.

[0088] The PMIC output noise voltage is generated independently and periodically.

[0089] Synchronously generate periodically varying PMIC input noise voltage and periodically varying PMIC output noise voltage.

[0090] Time-division multiplexing generates non-periodic PMIC input noise voltage and non-periodic PMIC output noise voltage;

[0091] Generate aperiodic PMIC input noise voltage independently;

[0092] Generates a non-periodic PMIC output noise voltage independently;

[0093] Synchronously generate non-periodic PMIC input noise voltage and non-periodic PMIC output noise voltage.

[0094] The PMIC input noise voltage and the PMIC output noise voltage are generated in a time-division manner, which are non-periodic.

[0095] In this embodiment, a noise generation module is used to generate PMIC input noise voltage and PMIC output noise voltage. The PMIC input noise voltage is superimposed on the PMIC power input terminal through a first noise voltage output module. That is, the first noise voltage output module interferes with the PMIC standard input voltage connected to the PMIC standard input voltage input terminal, generating an input disturbance voltage and outputting it to the power input terminal of the PMIC under test. This causes the PMIC's operating voltage to be interfered with by noise, simulating the input noise of the PMIC power supply, thus affecting the normal operation of the PMIC and verifying its anti-interference capability. The PMIC output noise voltage is superimposed on the PMIC power output terminal through a second noise voltage output module and output to the DRAM. That is, the second noise voltage output module interferes with the DRAM power supply voltage connected to the DRAM power supply voltage input terminal, generating an output disturbance voltage and outputting it to the power input terminal of the DRAM under test. This causes the DRAM's operating voltage to be interfered with by noise, simulating the input noise of the DRAM power supply. The actual input and output voltages of the PMIC can fluctuate around the standard input and output voltages, creating a relatively realistic scenario. This allows for testing not only the DRAM's operation under voltage fluctuations but also the verification of the PMIC chip's anti-interference capabilities. When the PMIC directly powers the DRAM, the PMIC and DRAM can be considered as a single unit. The input noise voltage (simulated noise 1) and output noise voltage (simulated noise 2) generated by the noise generation module simulate complex and variable real-world scenarios, making the test results closer to actual usage. Simulated noise testing is therefore necessary. Furthermore, different application scenarios can be simulated, such as fluctuations only in the PMIC's standard input voltage connected to its power input terminal, fluctuations only in the DRAM power supply voltage output from the PMIC, synchronous fluctuations in the PMIC's standard input voltage and the DRAM power supply voltage, or time-sharing fluctuations in the PMIC's standard input voltage and the DRAM power supply voltage, meaning the PMIC's standard input voltage and the DRAM power supply voltage fluctuate sequentially. These fluctuations can be periodic or non-periodic, instantaneous.

[0096] In this embodiment, when the PMIC standard input voltage fluctuates, it can fluctuate around an intermediate value, for example, when the PMIC standard input voltage is 12V, it can fluctuate around 12V. Specifically, the PMIC input noise voltage value can be adjusted in 0.1V steps. For example, in an analog application scenario, the voltage output to the PMIC power input terminal fluctuates between 11.9V, 12V, and 12.1V. In the next adjustment, the PMIC input noise voltage can be adjusted to fluctuate between 11.8V, 12V, and 12.2V. Furthermore, the frequency of periodic changes can also be adjusted, for example, it can be 100Hz or 100kHz. When the DRAM supply voltage fluctuates, it can fluctuate around an intermediate value, such as 1.1V. Specifically, it can fluctuate around 1.1V in 0.05V increments to adjust the PMIC input noise voltage. For example, in an analog application, the voltage output to the PMIC's power input might fluctuate between 1.05V, 1.1V, and 1.15V. In the next adjustment, the PMIC input noise voltage could fluctuate between 1.0V, 1.1V, and 1.2V. Furthermore, the frequency of these periodic changes can also be adjusted, for example, to 100Hz or 100kHz.

[0097] The present invention also proposes a DIMM module testing device, including a testing device and a DIMM module testing circuit as described above;

[0098] The test terminal of the test equipment is used to connect to the memory chip under test. The test equipment is used to acquire the dynamic fluctuation voltage of the memory chip under test and determine the operating voltage range of the memory chip under test based on the dynamic fluctuation voltage.

[0099] In this embodiment, the operating status of the DRAM is tested and recorded over a period of time using a testing machine, and then plotted as an eye diagram for clear observation. Figure 4 The eye diagram, with its vertical axis representing dynamically fluctuating voltage (V) and horizontal axis representing temperature (T), clearly shows the operating range of the DRAM, whether the voltage margin meets user requirements, and indirectly indicates the anti-interference capability of the PMIC chip. If the DRAM can still perform well under dynamically fluctuating input and output voltages of the PMIC chip, this is clearly what users expect, and it can also help select DRAM chips with superior performance.

[0100] The following is for reference. Figure 5This diagram illustrates a structural schematic of a DIMM module testing device suitable for implementing embodiments of the present invention. The DIMM module testing device in these embodiments may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Description), PMPs (Portable Media Players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 5 The DIMM module testing equipment shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of the present invention.

[0101] like Figure 5 As shown, the DIMM module testing device may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1003 into a random access memory (RAM) 1004. The RAM 1004 also stores various programs and data required for the operation of the DIMM module testing device. The processing unit 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to the I / O interface 1006: input devices 1007 including, for example, a touchscreen, touchpad, keyboard, mouse, image sensor, microphone, accelerometer, gyroscope, etc.; output devices 1008 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; storage devices 1003 including, for example, magnetic tape, hard disk, etc.; and communication devices 1009. Communication device 1009 allows the DIMM module test equipment to communicate wirelessly or wiredly with other devices to exchange data. Although the figure shows a DIMM module test equipment with various systems, it should be understood that implementation or possession of all the systems shown is not required. More or fewer systems may be implemented alternatively.

[0102] In particular, according to the embodiments disclosed in this invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this invention include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this invention.

[0103] The DIMM module testing equipment provided by this invention, employing the DIMM module testing circuit in the above embodiments, can solve the problem of inconvenient DIMM module testing. Compared with the prior art, the beneficial effects of the DIMM module testing equipment provided by this invention are the same as those of the DIMM module testing circuit provided in the above embodiments, and other technical features of this DIMM module testing equipment are the same as those disclosed in the method of the previous embodiment, and will not be repeated here.

[0104] It should be understood that the various parts disclosed in this invention can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or special times can be combined in any suitable manner in one or more embodiments or examples.

[0105] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

[0106] The above description is only a part of the embodiments of the present invention and does not limit the patent scope of the present invention. All equivalent structural transformations made under the technical concept of the present invention using the contents of the present invention specification and drawings, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A DIMM module test circuit, wherein the DIMM module includes a PMIC under test and a memory chip under test, characterized in that, The DIMM module test circuit includes: The PMIC standard input voltage input terminal is used to connect the PMIC standard input voltage. A noise voltage generation module has a first noise voltage output terminal and a second noise voltage output terminal. The noise voltage generation module is used to generate PMIC input noise voltage and PMIC output noise voltage. A first noise voltage output module has a first input terminal connected to the PMIC standard input voltage input terminal, and a second input terminal connected to the first noise voltage output terminal. The output terminal of the first noise voltage output module is used to connect to the PMIC under test. The first noise voltage output module is used to interfere with the PMIC standard input voltage connected to the PMIC standard input voltage input terminal according to the PMIC input noise voltage, generate an input disturbance voltage, and output it to the PMIC under test. The second noise voltage output module has a first input terminal connected to the output terminal of the PMIC under test, and a second input terminal connected to the second noise voltage output terminal. The output terminal of the second noise voltage output module is used to connect to the memory chip under test. The second noise voltage output module is used to interfere with the DRAM power supply voltage output by the PMIC under test according to the noise voltage output by the PMIC, and generate an output disturbance voltage to the DRAM under test to simulate external noise, so as to cause the actual input voltage of the DRAM to fluctuate, and test whether the DRAM maintains normal operation under external noise.

2. The DIMM module test circuit as described in claim 1, characterized in that, The magnitudes of the PMIC input noise voltage and the PMIC output noise voltage output by the noise voltage generation module are adjustable; and / or the frequency and amplitude of the PMIC input noise voltage and the PMIC output noise voltage output by the noise voltage generation module are adjustable.

3. The DIMM module test circuit as described in claim 2, characterized in that, The DIMM module test circuit also includes a noise generation control module, which is connected to the noise voltage generation module. The noise generation control module is used to control the noise voltage generation module to generate the corresponding PMIC input noise voltage and PMIC output noise voltage in a predetermined timing sequence according to the received test command.

4. The DIMM module test circuit as described in claim 3, characterized in that, The predetermined timing sequence includes at least: The PMIC input noise voltage is generated independently and periodically. The PMIC output noise voltage is generated independently and periodically. Synchronously generate periodically varying PMIC input noise voltage and periodically varying PMIC output noise voltage. Time-division multiplexing generates non-periodic PMIC input noise voltage and non-periodic PMIC output noise voltage; Generate aperiodic PMIC input noise voltage independently; Generates a non-periodic PMIC output noise voltage independently; Synchronously generate non-periodic PMIC input noise voltage and non-periodic PMIC output noise voltage. The PMIC input noise voltage and the PMIC output noise voltage are generated in a time-division manner, which are non-periodic.

5. The DIMM module test circuit as described in claim 1, characterized in that, The PMIC input noise voltage fluctuates around the PMIC standard input voltage; the PMIC output noise voltage fluctuates around the DRAM power supply voltage output by the PMIC.

6. The DIMM module test circuit as described in any one of claims 1 to 5, characterized in that, The first noise voltage output module includes a first summing operational amplifier. The first input terminal of the first summing operational amplifier is connected to the standard input voltage access terminal of the PMIC. The second input terminal of the first summing operational amplifier is connected to the first noise voltage output terminal of the noise voltage generation module. The output terminal of the first summing operational amplifier is used to connect to the PMIC under test.

7. The DIMM module test circuit as described in any one of claims 1 to 5, characterized in that, The second noise voltage output module includes a second summing operational amplifier. The output terminal of the second summing operational amplifier is used to connect to the output terminal of the PMIC under test. The second input terminal of the second summing operational amplifier is connected to the second noise voltage output terminal of the noise voltage generation module. The output terminal of the second summing operational amplifier is used to connect to the DRAM under test.

8. The DIMM module test circuit as described in any one of claims 1 to 5, characterized in that, The number of second noise voltage output modules is multiple. The first input terminal of each second noise voltage output module is connected to the output terminal of the PMIC under test. The second input terminal of each second noise voltage output module is connected to a second noise voltage output terminal. The output terminal of each second noise voltage output module is used to connect to a DRAM under test.

9. A DIMM module testing device, characterized in that, Includes a testing machine and a DIMM module testing circuit as described in any one of claims 1 to 8; The test terminal of the test equipment is used to connect to the memory chip under test. The test equipment is used to acquire the dynamic fluctuation voltage of the memory chip under test and determine the operating voltage range of the memory chip under test based on the dynamic fluctuation voltage.

10. A method for testing DIMM modules, characterized in that, The DIMM module testing method uses the DIMM module testing circuit as described in any one of claims 1 to 8; The DIMM module test includes a noise voltage generation module, a first noise voltage output module, and a second noise voltage output module; The DIMM module testing method includes: The system acquires a test command and controls the noise voltage generation module to generate corresponding PMIC input noise voltage and PMIC output noise voltage according to a predetermined timing sequence. The PMIC input noise voltage is then output to the first noise voltage output module, which in turn interferes with the PMIC standard input voltage connected to the PMIC standard input voltage input terminal based on the PMIC input noise voltage, generating an input disturbance voltage and outputting it to the PMIC under test. Furthermore, the PMIC output noise voltage is output to a second noise voltage output module, so that the second noise voltage output module, based on the PMIC output noise voltage, interferes with the DRAM supply voltage output by the PMIC under test, generating an output disturbance voltage to the DRAM under test to simulate external noise, causing fluctuations in the actual input voltage of the DRAM, and testing whether the DRAM maintains normal operation under external noise; wherein, the predetermined timing includes at least: The PMIC input noise voltage is generated independently and periodically. The PMIC output noise voltage is generated independently and periodically. Synchronously generate periodically varying PMIC input noise voltage and periodically varying PMIC output noise voltage. Time-division multiplexing generates non-periodic PMIC input noise voltage and non-periodic PMIC output noise voltage; Generate aperiodic PMIC input noise voltage independently; Generates a non-periodic PMIC output noise voltage independently; Synchronously generate non-periodic PMIC input noise voltage and non-periodic PMIC output noise voltage. The PMIC input noise voltage and the PMIC output noise voltage are generated in a time-division manner, which are non-periodic.

Images