Radar plot data processing system and method based on page-locked memory

Abstract

The application discloses a radar point data processing system and method based on page locking memory, wherein a performance monitoring module determines a comprehensive load factor according to system running state parameters; a page locking memory management module performs capacity adjustment on a page locking memory buffer pool according to the comprehensive load factor; a receiving module writes radar point data into an idle page locking memory block; a GPU processing module binds the page locking memory block with a CUDA flow, performs parallel processing on the radar point data to obtain a processing result, and writes the processing result into a display memory cache shared buffer; a display control display module responds to completion of writing of the processing result, performs display rendering on the processing result, and outputs a consumption completion signal; and the GPU processing module responds to the consumption completion signal, releases the CUDA flow, GPU display memory and page locking memory block, thereby realizing stable and efficient processing of radar point data in a high-throughput and high real-time application scenario.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and in particular to a radar spot data processing system and method based on page-locked memory. Background Technology

[0002] Radar systems detect targets by emitting and receiving electromagnetic waves, and process the echo signals to form radar point data. Radar point data is fundamental information for target detection, tracking, and situational analysis; its processing efficiency and real-time performance directly affect the overall performance of the radar system. In applications such as multi-radar cooperative detection, high-resolution radar imaging, and dense target surveillance, the scale of point data generated by radar systems per unit time increases significantly, exhibiting characteristics such as large data volume, high update frequency, and complex processing links.

[0003] To improve the processing capability of radar point data, related technologies have introduced graphics processing units (GPUs) as processing units. However, in this approach, the transmission method of radar point data between the radar acquisition device, host memory, and GPU memory, as well as the configuration and management strategies of memory resources, often become key factors restricting the overall performance and stability of data processing. For example, after radar point data is written to host memory by the acquisition device, it is then copied to GPU memory by the central processing unit (CPU) or driver. This data transmission link often involves multiple data copying processes, with a high CPU involvement, which not only increases data transmission latency but also consumes a large amount of host processing resources. When the scale of radar point data continues to increase or the data update frequency increases, the data transmission process can easily become a bottleneck for the overall system performance. Page-locked memory can improve the data transmission efficiency from host memory to GPU memory, but the size of the page-locked memory buffer is usually configured in a fixed manner during system initialization. The system cannot dynamically adjust based on changes in radar point data flow and system operating status. In scenarios with data bursts or high loads, a fixed-size page-locked buffer can easily lead to DMA queue backlog and processing delays. Conversely, under low loads, prolonged occupation of a large amount of page-locked memory reduces host memory resource utilization and affects system stability. The data transfer process from host memory to GPU memory and the GPU parallel computing process often lack a unified scheduling and coordination mechanism. Data copying and kernel function execution are difficult to fully overlap, resulting in the GPU being idle for some time periods and low overall computing resource utilization. In high-throughput radar point processing scenarios, these problems are further amplified, restricting the improvement of system processing capabilities. The inability to dynamically optimize memory configuration and processing strategies based on system operating status leads to significant performance fluctuations under different load conditions. Summary of the Invention

[0004] The purpose of this application is to provide a radar spot data processing system with page-locked memory, which can solve technical problems such as limited data transmission efficiency, rigid page-locked memory configuration, insufficient GPU resource utilization, and lack of adaptive adjustment mechanism, so as to achieve stable and efficient processing of radar spot data in high-throughput and high-real-time application scenarios.

[0005] In a first aspect, this application provides a radar spot data processing system based on page-locked memory, the system comprising:

[0006] The performance monitoring module is used to obtain the system operating status parameters of the current sampling period and determine the comprehensive load factor based on the system operating status parameters;

[0007] The page-locked memory management module is used to adjust the capacity of the page-locked memory buffer pool based on the overall load factor.

[0008] The receiving module is used to write the received radar spot data into any free page-locked memory block in the page-locked memory buffer pool with adjusted execution capacity using direct memory access (DMA).

[0009] The GPU processing module is used to respond to the detection that a page-locked memory block write operation has been completed, bind the page-locked memory block to a CUDA stream of a computing unified device architecture, asynchronously transmit radar spot data to GPU memory through the CUDA stream and perform parallel processing, obtain the processing result, and write the processing result to the shared buffer of the memory cache.

[0010] The display control module is used to respond to the completion of writing the processing result, perform display rendering of the processing result, and output a consumption completion signal;

[0011] The GPU processing module is used to release the CUDA stream and GPU memory in response to the consumption completion signal, and to notify the page lock memory management module to release the page lock memory block.

[0012] In one embodiment, system operating status parameters include at least one of the following: PCIe bandwidth utilization, DMA wait queue length, GPU computing resource idle rate, and page-locked memory buffer pool occupancy ratio. The page-locked memory management module is specifically used for:

[0013] Determine whether the current sampling period is within the cooling period, which is the time period during which capacity adjustment is paused;

[0014] If the current sampling period is within the cooling period, the page-locked memory management module temporarily freezes the capacity adjustment of the page-locked memory buffer pool;

[0015] If the current sampling period is not within a cooling-off period, the page-locked memory management module performs capacity adjustment on the page-locked memory buffer pool. The capacity adjustment includes:

[0016] If the combined load factor of multiple consecutive sampling periods exceeds the first load threshold, the page-locked memory management module performs an expansion operation, and after the expansion operation is completed, the capacity of the page-locked memory buffer pool is adjusted to enter the cooling cycle.

[0017] If the combined load factor of multiple consecutive sampling periods is lower than the second load threshold, the page-locked memory management module performs a containment operation, and after the containment operation is completed, the capacity of the page-locked memory buffer pool is adjusted to enter the cooling cycle, and the first load threshold is greater than the second load threshold.

[0018] In one embodiment, the page-locking memory management module is specifically used for:

[0019] For each sampling period,

[0020] If the overall load factor of the sampling period exceeds the first load threshold, the high load count value is incremented by one until the obtained high load count value exceeds the trigger count threshold, at which point the page locking memory management module performs an expansion operation.

[0021] If the overall load factor of the sampling period is lower than the second load threshold, the low load count value is incremented by one until the acquired low load count value exceeds the trigger count threshold, at which point the page locking memory management module performs a containment operation.

[0022] In one embodiment, the system operating status parameters include at least one of the following: DMA wait queue length and GPU computing resource idle rate, wherein the GPU processing module is specifically used for:

[0023] The GPU processing module dynamically selects the CUDA stream processing mode based on system operating status parameters, whereby...

[0024] If the DMA wait queue length continues to grow, the GPU processing module determines that the CUDA stream processing mode is simplified mode, and the CUDA stream reduces computational complexity by executing some kernel functions;

[0025] If the GPU computing resource idle rate exceeds a preset threshold, the GPU processing module determines that the CUDA stream processing mode is normal mode, and the CUDA stream executes all kernel functions.

[0026] In one embodiment, the page-locking memory management module is specifically used for:

[0027] For each page-locked memory block in the page-locked memory buffer pool, the state of the page-locked memory block includes free state, writing state, pending state, processing state, and releasing state. A state machine is used to update the state of the page-locked memory block.

[0028] When the page-locked memory block is in an idle state, in response to the memory block allocation request information output by the data receiving module, the page-locked memory management module switches the state of the page-locked memory block from the idle state to the writing state.

[0029] When the page-locked memory block is in the writing state, the data receiving module writes the radar spot data into the page-locked memory block in DMA mode. The page-locked memory management module records the transmission status and writing start time of the page-locked memory block, and switches the status of the page-locked memory block from the writing state to the pending state when the writing of the page-locked memory block is completed.

[0030] When the page-locked memory block is in the pending state, the page-locked memory management module adds the page-locked memory block to the pending queue, updates the status timestamp, outputs a memory block ready notification to the GPU processing module, and responds to the GPU processing module by binding the page-locked memory block to the CUDA stream and switching the status of the page-locked memory block from the pending state to the processing state.

[0031] When the page-locked memory block is in the processing state, it is bound to a CUDA stream. In response to the processing completion notification output by the GPU processing module, the page-locked memory management module switches the state of the page-locked memory block from the processing state to the release state.

[0032] When the page-locked memory block is in the releasing state, the page-locked memory management module responds to the memory block release notification signal output by the GPU processing module and switches the state of the page-locked memory block from the releasing state to the idle state.

[0033] In one embodiment, the GPU processing module is specifically used for,

[0034] In response to a memory block ready notification, the GPU processing module selects any free CUDA stream from the CUDA stream pool, binds the page-locked memory block in the pending state to the free CUDA stream, and during the binding period, the lifecycle of the CUDA stream is synchronized with the lifecycle of the page-locked memory block.

[0035] In response to the consumption completion signal, the GPU processing module unbinds the page-locked memory block and releases the CUDA stream, thus releasing the CUDA stream;

[0036] The GPU processing module sets concurrency constraints on the CUDA stream pool, ensuring that the number of CUDA streams in a bound relationship does not exceed the sum of the number of page-locked memory blocks in the pending state and the number of page-locked memory blocks in the processing state.

[0037] In one embodiment, the GPU processing module is specifically used for,

[0038] For any CUDA stream in a binding relationship, the state of the CUDA stream includes an initialization state, a processing state, and a completion state. The state of the CUDA stream is updated using a finite state machine.

[0039] When the CUDA stream is in the initialization state, the GPU processing module performs an initialization operation on the CUDA stream. In response to the completion of the initialization operation, the state of the CUDA stream is switched from the initialization state to the processing state. The initialization operation includes at least one of the following: creating a CUDA stream context, allocating a shared buffer for the processing result, and initializing the CUDA stream.

[0040] When the CUDA stream is in the processing state, the CUDA stream asynchronously transmits radar point data to the GPU memory, performs parallel processing on the radar point data to obtain the processing result, writes the processing result to the shared buffer of the memory cache, sets the status flag of the shared buffer of the memory cache to the data ready flag, and switches the state of the CUDA stream from the processing state to the completed state.

[0041] When the CUDA stream is in the completed state, in response to the consumption completion signal output by the display control module, the GPU processing module releases the CUDA stream, outputs a memory block release notification signal to the page-locked memory management module, and switches the CUDA stream from the completed state to the initialization state.

[0042] In one embodiment, the display control module is specifically used for,

[0043] In response to the detection that the status flag of the shared memory cache is a data ready flag, the display control module reads the processing result from the shared memory cache and performs the display rendering operation;

[0044] Once the display rendering operation is complete, the display control module outputs a consumption completion signal to the GPU processing module.

[0045] In one embodiment, the data receiving module is connected to an external radar acquisition device via a PCIe bus. Specifically, the data receiving module is used for...

[0046] The data receiving module receives radar point data output by the radar acquisition device and outputs memory block allocation request information to the page locking memory management module;

[0047] When the page-locked memory block allocated by the page-locked memory management module is in write mode, the data receiving module writes radar spot data into the page-locked memory block in DMA mode.

[0048] Secondly, this application provides a radar spot data processing method based on page-locked memory, the method comprising:

[0049] Obtain the system operating status parameters for the current sampling period, determine the comprehensive load factor based on the system operating status parameters, and adjust the capacity of the page-locked memory buffer pool according to the comprehensive load factor.

[0050] The received radar spot data is written to any free page-locked memory block in the page-locked memory buffer pool with adjusted execution capacity using direct memory access (DMA).

[0051] In response to the detection that a page-locked memory block write operation has been completed, a memory block ready notification for the page-locked memory block is output.

[0052] In response to a memory block ready notification, the page-locked memory block is bound to a CUDA stream of a compute unified device architecture. The CUDA stream asynchronously transmits radar point data to GPU memory and performs parallel processing on the radar point data to obtain the processing result, which is then written to the shared buffer of the memory cache.

[0053] In response to the detection that a write operation to the shared buffer of the video memory cache has been completed, the processing result is executed for display rendering, and a consumption completion signal is output.

[0054] In response to the consumption completion signal, release the CUDA stream, GPU memory, and page-locked memory blocks.

[0055] This application adjusts the capacity of the page-locked memory buffer pool by comprehensively considering load factors, transforming the memory block management of the page-locked memory buffer pool from static configuration to dynamic adjustment oriented towards DMA (Direct Memory Access) blocking and data backlog. This allows for dynamic management and adjustment of capacity based on changes in radar point data flow and system operating status. In scenarios with data bursts or high loads, this reduces data processing latency, while in low loads, it improves the utilization of host memory resources and system stability. It dynamically matches memory resources and data flow requirements under different load conditions, ensuring continuous operation even under sudden high loads, significantly improving the stability and reliability of the radar point processing system. By using page-locked memory blocks as the direct DMA write target for radar point data, radar point data can enter the data processing path without being copied by the central processing unit, paving the way for subsequent GPU processing. Parallel processing provides stable and continuous data input; it establishes a correspondence between the lifecycle state of page-locked memory blocks and CUDA streams, ensuring that GPU processing scheduling is consistent with the host-side data supply capacity; and it achieves coordination between processing results and the display control module through a shared buffer of video memory cache, reducing unnecessary data backhauls and forming a closed loop of performance monitoring, memory block capacity adjustment, memory block state updates, GPU scheduling, GPU processing, display control consumption, display control feedback, and memory reclamation. This enables an orderly, controllable, and feedback-based collaborative operation mechanism for radar point data in the stages of reception, caching, transmission, parallel computing, and display; thus giving the system better real-time processing capabilities and operational stability when facing large-scale, high-speed radar point data. Attached Figure Description

[0056] Figure 1 A system block diagram of a radar spot data processing system based on page-locked memory provided in this application embodiment;

[0057] Figure 2 A schematic diagram of the capacity adjustment process provided in this application embodiment;

[0058] Figure 3 A schematic diagram illustrating the state update of a page-locked memory block provided in an embodiment of this application;

[0059] Figure 4 A schematic diagram illustrating the process of binding page-locked memory blocks to CUDA streams as provided in an embodiment of this application;

[0060] Figure 5 This is a schematic diagram illustrating the data interaction between the GPU processing module and the display control module provided in an embodiment of this application.

[0061] Figure 6 This is a flowchart illustrating the radar spot data processing method based on page-locked memory provided in an embodiment of this application. Detailed Implementation

[0062] The present application will be described in detail below with reference to the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present application. Any structural, methodological, or functional modifications made by those skilled in the art based on these embodiments are included within the protection scope of the present application.

[0063] Please refer to Figure 1 This application provides a radar spot data processing system based on page-locked memory. The system includes a performance monitoring module 11, a data receiving module 12, a page-locked memory management module 13, a GPU processing module 14, and a display control module 15. The performance monitoring module 11 acquires system operating status parameters for the current sampling period and determines a comprehensive load factor based on these parameters. The page-locked memory management module 13 adjusts the capacity of the page-locked memory buffer pool according to the comprehensive load factor. The data receiving module 12 writes the received radar spot data to any free page-locked memory block in the adjusted page-locked memory buffer pool using direct memory access (DMA). Upon detecting the completion of the page-locked memory block write operation, the page-locked memory management module 13 outputs a memory block readiness notification. In response to the memory block readiness notification, the GPU processing module 14 binds the page-locked memory block to a CUDA stream of a unified computing device architecture. The CUDA stream asynchronously transmits the radar spot data to the GPU memory and performs parallel processing on the radar spot data to obtain the processing result, which is then written to the shared buffer of the GPU memory cache. In response to the detection that a write operation to the shared buffer of the video memory cache has been completed, the display control module 15 performs display rendering on the processing result and outputs a consumption completion signal. In response to the consumption completion signal, the GPU processing module 14 releases the CUDA stream and GPU video memory, and the page-locked memory management module 13 releases the page-locked memory block.

[0064] For example, the performance monitoring module 11 collects system operating status parameters at a preset sampling period. These parameters include at least one of the following: PCIe bandwidth utilization, DMA wait queue length, GPU computing resource idle rate, and page-locked memory buffer pool occupancy rate. The acquired system operating status parameters are normalized to calculate the corresponding comprehensive load factor, thus obtaining the comprehensive load factor for the current sampling period. The comprehensive load factor directly reflects whether DMA writes are blocked, whether memory blocks are insufficient, and whether there are computational or waiting bottlenecks in the GPU. The page-locked memory management module 13 adjusts the capacity of the page-locked memory buffer pool based on the comprehensive load factor. This capacity adjustment includes expansion and containment operations. The page-locked memory management module 13 adjusts the capacity of the page-locked memory buffer pool by comprehensively considering the load factor. This transforms the memory block management of the page-locked memory buffer pool from static configuration to dynamic adjustment in response to DMA blocking and data backlog. As a result, the capacity is dynamically managed and adjusted according to changes in radar point data flow and system operating status. This reduces data processing latency in scenarios with data bursts or high loads, and improves the utilization of host memory resources and system stability when the load is low.

[0065] For example, PCIe bandwidth utilization can be understood as the ratio of the actual data transfer throughput of the PCIe link to the upper limit of the effective bandwidth that the PCIe link can provide within a preset sampling window. For example, PCIe bandwidth utilization = (number of PCIe bytes transferred within the sampling window / sampling window ÷ theoretical effective PCIe bandwidth). DMA wait queue length can be understood as the amount of data waiting to be processed in the wait queue. GPU computing resource idle rate can be understood as the percentage of time that GPU computing units are engaged in ineffective computing execution within a preset sampling window. Page-locked memory buffer pool occupancy rate can be understood as the percentage of the total capacity of the page-locked memory buffer pool that is occupied (cannot be immediately allocated) within a preset sampling window.

[0066] For example, after system initialization, the page-locked memory management module 13, in cooperation with the operating system and device driver, pre-allocates several page-locked memory blocks in the page-locked memory buffer pool. Each page-locked memory block corresponds to a contiguous, non-swapable physical memory page and is registered as a target area that can be directly accessed by the DMA controller. During subsequent system operation, the page-locked memory management module 13 dynamically adjusts the page-locked memory buffer pool according to the system load state based on the acquired comprehensive load factor.

[0067] For example, the data receiving module 12 requests a free page-locked memory block from the page-locked memory management module 13. The page-locked memory management module 13 allocates a corresponding page-locked memory block, and the data receiving module 12 writes the radar spot data into the page-locked memory block using DMA. During the DMA write, the page-locked memory block is marked as "writing" to prevent concurrent access by other modules. This embodiment eliminates the data copying process of the central processing unit (CPU) by directly writing the radar spot data into the host memory area (page-locked memory block) that can be efficiently accessed by the GPU, thus providing stable and continuous data input for subsequent parallel processing by the GPU.

[0068] For example, after the page-locked memory block is written, a write completion event is reported to the data receiving module 12 via an interrupt or polling mechanism. The page-locked memory management module 13 outputs a memory block ready notification for the page-locked memory block. After receiving the memory block ready notification, the GPU processing module 14 allocates a Compute Unified Device Architecture (CUDA) stream for the page-locked memory block, binds the page-locked memory block to the CUDA stream, and establishes a one-to-one correspondence between the two. The CUDA stream asynchronously transmits radar point data to the GPU memory and performs kernel function processing on the radar point data, including point unpacking, coordinate transformation, noise suppression, point analysis, and trajectory generation, etc., to obtain the processing result, which is then written to a pre-allocated shared buffer of the GPU memory cache. Each page-locked memory block is always associated with a CUDA stream throughout its lifecycle. The CUDA stream is responsible for processing the radar point data corresponding to the page-locked memory block, so as to tightly couple GPU scheduling with memory resource status and prevent GPU idling or data accumulation on the host memory side.

[0069] For example, when the write operation of the shared buffer of the video memory cache is completed, the display control module 15 performs display rendering on the processing result and outputs a consumption completion signal to the GPU processing module 14. The consumption completion signal is used to indicate that the processing result has been completely consumed. Upon receiving the consumption completion signal, the GPU processing module 14 releases the CUDA stream and GPU video memory, and notifies the GPU processing module 14 to perform memory release. The page-locked memory management module 13 releases the page-locked memory block to reset the page-locked memory block to free.

[0070] In this embodiment, the capacity of the page-locked memory buffer pool is adjusted by comprehensively considering the load factor. This transforms the memory block management of the page-locked memory buffer pool from static configuration to dynamic adjustment oriented towards DMA blocking and data backlog. This allows for dynamic management and adjustment of capacity based on changes in radar point data flow and system operating status, enabling adaptive expansion or contraction of the page-locked memory buffer pool. This can promptly increase the number of available page-locked memory blocks in scenarios of data bursts or high loads, reduce the DMA wait queue length, maintain the continuity of the data transmission link, significantly improve the transmission efficiency of the radar point data GPU processing link, and reduce system latency caused by data transfer, thus reducing data processing latency. At low loads, it improves the utilization of host memory resources and system stability. Using page-locked memory blocks as the direct DMA write target for radar point data allows radar point data to enter the data processing path without being copied by the central processing unit, providing a stable and continuous data flow for subsequent GPU parallel processing. According to the input; the lifecycle state of page-locked memory blocks is associated with CUDA streams, so that each page-locked memory block to be processed is bound to a CUDA stream during the processing cycle, ensuring that GPU processing scheduling is consistent with the data supply capacity of the host side, effectively overlapping data transmission with GPU parallel computing, reducing GPU idle waiting time, and enabling GPU computing resources to continuously operate at high efficiency, thereby improving overall processing throughput; through the shared buffer of video memory cache, the processing results are coordinated with the display control module 15, reducing unnecessary data backhaul, forming a closed loop of performance monitoring, memory block capacity adjustment, memory block state update, GPU scheduling, GPU processing, display control consumption, display control feedback, and memory reclamation, so that radar spot data forms an orderly, controllable, and feedback-enabled collaborative operation mechanism among the various links of reception, caching, transmission, parallel computing, and display; enabling the system to have better real-time processing capabilities and operational stability when facing large-scale, high-speed radar spot data.

[0071] In one embodiment, the data receiving module 12 is connected to an external radar acquisition device via a PCIe bus. The radar acquisition device outputs radar point data. The data receiving module 12 receives the radar point data output by the radar acquisition device and outputs a memory block allocation request to the page-locked memory management module 13. Upon receiving the memory block allocation request, the page-locked memory management module 13 selects any free page-locked memory block from the page-locked memory buffer pool. When the page-locked memory block is in a write state, the data receiving module 12 writes the radar point data to the page-locked memory block using DMA. During the DMA write, the page-locked memory block is marked as "writing" to avoid concurrent access conflicts. After the radar point data is written to the page-locked memory block, the data receiving module 12 sends a write completion event to the page-locked memory management module 13 via interrupt or polling. The page-locked memory management module 13 then switches the state of the locked memory block from "writing" to "pending," triggering an update of the page-locked memory block's state. Page-locked memory management module 13 sends a memory block ready notification to GPU processing module 14, indicating that the radar spot data in the page-locked memory block can enter the GPU processing stage.

[0072] In one embodiment, such as Figure 2 The diagram illustrates the capacity adjustment process. During system operation, the performance monitoring module 11 acquires system operating status parameters for the current sampling period. To eliminate differences in the dimensions and numerical ranges of different performance indicators, the acquired system operating status parameters are normalized and converted into a unified numerical range (0-1) for subsequent comprehensive evaluation and comparison. Based on the normalized system operating status parameters, a comprehensive load factor is calculated using a multi-indicator fusion method. The comprehensive load factor characterizes the overall load level of the current system across multiple dimensions, including data access, memory turnover, and GPU processing, and serves as the basis for adjusting the capacity of the page-locked memory buffer pool in the page-locked memory management module 13. The comprehensive load factor can be calculated using a specific mathematical model, or it can be implemented using weighted summation, logical combination, or other equivalent fusion methods. This application does not limit the specific calculation method of the comprehensive load factor.

[0073] The page-locked memory management module 13 determines whether the current sampling period is within a cooldown period, which is a time period during which capacity adjustments are paused. This cooldown period can be understood as a time period used to temporarily freeze subsequent capacity adjustments after performing memory block expansion or containment operations, to prevent system instability caused by frequent expansion and contraction due to short-term load fluctuations. If the current sampling period is within a cooldown period, the page-locked memory management module 13 temporarily freezes capacity adjustments to the page-locked memory buffer pool, does not perform any capacity adjustment operations, and directly proceeds to the next sampling period.

[0074] If the current sampling period is not within a cooling-off period, the page-locked memory management module 13 adjusts the capacity of the page-locked memory buffer pool based on the comprehensive load factor. If the comprehensive load factor for multiple consecutive sampling periods exceeds the first load threshold, indicating that the system is under high load, the page-locked memory management module 13 performs a capacity expansion operation and, after the expansion operation is completed, adjusts the capacity of the page-locked memory buffer pool into a cooling-off period. The first load threshold is a preset high load threshold. The expansion operation can be understood as increasing the number of page-locked memory blocks in the page-locked memory buffer pool to improve the system's data access and turnover capabilities. After the expansion is completed, a cooling-off period begins, and subsequent capacity adjustment operations are paused.

[0075] If the combined load factor for multiple consecutive sampling periods is lower than the second load threshold, it indicates that the system is in a low-load state. The page-locked memory management module 13 performs a containment operation, and after the containment operation is completed, the capacity of the page-locked memory buffer pool is adjusted to enter a cooling cycle. The second load threshold is a preset low-load threshold. The first load threshold is greater than the second load threshold. The containment operation can be understood as releasing page-locked memory blocks that have been idle for a long time in the page-locked memory buffer pool to reduce host memory usage. After containment is completed, a cooling cycle is entered, and subsequent capacity adjustment operations are paused.

[0076] For example, for each sampling period, if the overall load factor of that sampling period exceeds the first load threshold, the high load count is incremented by one, and it is determined whether the incremented high load count exceeds the trigger count threshold. If it does not exceed the threshold, the page-locked memory management module 13 does not immediately perform a capacity expansion operation, but directly proceeds to the next sampling period. This process is repeated in the next sampling period until the acquired high load count exceeds the trigger count threshold N, at which point the page-locked memory management module 13 performs a capacity expansion operation. After the capacity expansion operation is completed, the high load count is reset to 0, and a cooling-off period begins.

[0077] For example, for each sampling period, if the overall load factor of that sampling period is lower than the second load threshold, the low load count is incremented by one, and it is determined whether the incremented low load count exceeds the trigger count threshold. If it does not exceed the threshold, the page-locked memory management module 13 does not immediately perform a containment operation, but directly proceeds to the next sampling period. This process is repeated in the next sampling period until the acquired low load count exceeds the trigger count threshold N, at which point the page-locked memory management module 13 performs a containment operation. After the containment operation is completed, the low load count is reset to 0, and a cooling-off period begins.

[0078] This embodiment forms a continuously running adaptive control loop by collecting system status parameters, calculating comprehensive load factors, and determining expansion / shrinkage. It periodically samples the system's operating status and evaluates the comprehensive load to achieve adaptive expansion / shrinkage control of the page-locked host memory buffer pool size. This maintains stable system operation and resource utilization efficiency under different data flow load conditions. By coordinating the adjustment cycle and the cooling cycle, the system can respond to load changes while avoiding frequent memory adjustments caused by instantaneous fluctuations, thus ensuring the stability of system operation.

[0079] In one embodiment, such as Figure 3 The diagram illustrates the state update of a page-locked memory block. For each page-locked memory block in the page-locked memory buffer pool, its state includes idle, writing, pending, processing, and releasing states. A state machine is used to update the state of the page-locked memory block. When the page-locked memory block is in the idle state, in response to the memory block allocation request information output by the data receiving module 12, the page-locked memory management module 13 switches from the idle state to the writing state. When a page-locked memory block is in the idle state, it indicates that the memory block is not currently occupied by any data receiving or processing flow, its physical pages have been locked and registered as a target area that can be directly accessed by the DMA controller, and it can respond to memory block allocation requests from the data receiving module 12. When the data receiving module 12 sends a memory block allocation request and successfully allocates a page-locked memory block in the idle state, the page-locked memory block triggers a state transition condition, switching from the idle state to the writing state.

[0080] When the page-locked memory block is in the "writing" state, the data receiving module 12 writes radar point data into the page-locked memory block using DMA. The page-locked memory management module 13 records the transmission status and write start time of the page-locked memory block, and switches from the "writing" state to the "pending" state in response to the completion of the write operation. After the page-locked memory block switches to the "writing" state, it indicates that the DMA transfer process has been initiated, and the radar point data is directly written into the page-locked memory block. This page-locked memory block is marked as non-reallocatable, and its access permissions are restricted to prevent concurrent access conflicts from other modules before the data is fully written. In the "writing" state, the page-locked memory management module 13 records the DMA transfer status and write start time of the page-locked memory block for subsequent anomaly detection and load assessment. When the radar point data transmission is complete, and a write completion event is reported via interrupt or polling, a state transition condition is triggered, and the page-locked memory block switches from the "writing" state to the "pending" state.

[0081] When the page-locked memory block is in a pending state, the page-locked memory management module 13 adds the page-locked memory block to the pending queue, updates the status timestamp, outputs a memory block ready notification to the GPU processing module 14, and, in response to the GPU processing module 14, binds the page-locked memory block to a CUDA stream. The page-locked memory management module 13 then switches from the pending state to the processing state. When the page-locked memory block is in a pending state, it indicates that the radar point data in the memory block has been completely written, but has not yet entered the GPU parallel processing stage. The page-locked memory management module 13 adds the page-locked memory block to the pending queue, updates the memory block status timestamp, and simultaneously outputs a memory block ready notification to the GPU processing module 14. The page-locked memory block in the pending state waits for GPU scheduling resources. When the GPU processing module 14 allocates the corresponding CUDA stream to the page-locked memory block, the state transition condition is triggered, and the page-locked memory block switches from the pending state to the processing state.

[0082] When the page-locked memory block is in the "processing" state, it is bound to a CUDA stream. In response to the processing completion notification output by the GPU processing module 14, the page-locked memory management module 13 switches from the "processing" state to the "releasing" state. The "processing" state indicates that the page-locked memory block has been bound to a CUDA stream. Within this CUDA stream, the GPU processing module 14 performs asynchronous data transfer of radar point data from the page-locked memory block to the GPU memory. After the data transfer is complete, the CUDA stream sequentially executes parallel computation kernel functions such as point unpacking, coordinate transformation, noise suppression, point analysis, and trajectory generation. In the "processing" state, the page-locked memory block is marked as non-reclaimable to ensure data consistency during GPU computation. Once all kernel functions on the GPU side have been executed and the corresponding processing results have been generated, a state transition condition is triggered, and the page-locked memory block switches from the "processing" state to the "releasing" state.

[0083] When the page-locked memory block is in the release state, in response to the memory block release notification signal output by the GPU processing module 14, the page-locked memory management module 13 switches from the release state to the idle state. When the page-locked memory block is in the release state, it indicates that the GPU-side computation task has been completed, but the processing result has not yet been fully consumed by the display module 15. The GPU processing module 14 keeps the CUDA stream associated with the page-locked memory block in the controlled release phase and waits for the display module 15 to return a "consumption complete" signal. In the release state, the page-locked memory management module 13 releases the CUDA stream bound to the page-locked memory block and cleans up related temporary resources; when the display module 15 completes the display and sends back a consumption complete signal, the state transition condition is triggered, and the page-locked memory block switches from the release state back to the idle state.

[0084] At any given time, each page-locked memory block is only allowed to be in one of the above states, and state transitions must meet the corresponding triggering conditions; cross-state transitions are not allowed. To support the above state management mechanism, the page-locked memory management module 13 maintains a set of management attributes for each page-locked memory block, including but not limited to: a unique identifier for the memory block, a current state flag, a state change timestamp, a physical memory address, an associated CUDA stream identifier, and a valid data length.

[0085] This embodiment manages each page-locked memory block in the page-locked host memory buffer pool using an explicit state machine approach. The page-locked memory block serves as the smallest scheduling and reclamation unit, and state constraints ensure data consistency, concurrency safety, and the orderly connection of processing flows. Each page-locked memory block exists in only one defined state throughout its lifecycle, and state transitions are only allowed when preset trigger conditions are met. This avoids abnormal situations such as data overwriting, duplicate processing, or premature reclamation. Furthermore, strict lifecycle control is implemented for page-locked memory blocks across data reception, GPU processing, and result consumption stages, providing a reliable foundation for subsequent adaptive memory scheduling and performance closed-loop control.

[0086] In one embodiment, such as Figure 4The diagram illustrates the process of binding page-locked memory blocks to CUDA streams. In response to a memory block readiness notification, the GPU processing module 14 selects any idle CUDA stream from the CUDA stream pool and binds the page-locked memory block in a pending state to that idle CUDA stream. During the binding process, the lifecycle of the CUDA stream is synchronized with the lifecycle of the page-locked memory block. When the page-locked memory management module 13 detects that a page-locked memory block is in a "pending" state, the GPU processing module 14 selects an idle CUDA stream from the CUDA stream pool and binds it to the page-locked memory block. After binding, the CUDA stream sequentially outputs the asynchronous data transfer from the page-locked memory block to the GPU memory, along with the corresponding parallel processing kernel function. During the binding process, a one-to-one correspondence is maintained between the page-locked memory block and the CUDA stream, and the lifecycle of the CUDA stream is synchronized with the processing cycle of the page-locked memory block to prevent the page-locked memory block from being prematurely reclaimed or reallocated before the GPU finishes processing. In response to the consumption completion signal, the GPU processing module 14 releases the page-locked memory blocks and the CUDA stream binding fiber, thus releasing the CUDA stream. The GPU processing module 14 sets concurrency constraints on the CUDA stream pool, ensuring that the number of CUDA streams in a binding relationship does not exceed the sum of the number of page-locked memory blocks in the pending state and the number of page-locked memory blocks in the processing state, thereby preventing GPU scheduling from outpacing the host-side data supply capacity.

[0087] This embodiment achieves synchronous scheduling of page-locked memory blocks and CUDA streams within the processing cycle by binding and unbinding the page-locked memory blocks and CUDA streams. The CUDA stream is released synchronously when the page-locked memory block is released, ensuring an orderly connection between host-side data supply and GPU parallel processing, thus guaranteeing the stability and resource utilization efficiency of the GPU parallel processing process. By setting concurrency constraints, it prevents GPU scheduling from leading to insufficient host-side data supply, avoiding memory resource contention and DMA write blocking.

[0088] In one embodiment, for any CUDA stream in a binding relationship, the state of the CUDA stream includes an initialization state, a processing state, and a completion state, and the state of the CUDA stream is updated using a finite state machine.

[0089] When the CUDA stream is in the initialization state, the GPU processing module 14 performs an initialization operation on the CUDA stream. In response to the completion of the initialization operation, the GPU processing module 14 switches from the initialization state to the processing state. The initialization operation includes at least one of the following: creating a CUDA stream context, allocating a shared memory buffer for the processing results, and initializing the CUDA stream.

[0090] When the CUDA stream is in the processing state, the GPU processing module 14 receives a memory block ready notification from the page-locked memory management module 13. The GPU processing module 14 binds the corresponding CUDA stream to the page-locked memory block. The CUDA stream asynchronously transmits radar point data from the page-locked memory block to the GPU memory. The radar point data is processed in parallel to obtain the processing result. The processing result is written to the shared buffer of the memory cache, and the status flag of the shared buffer of the memory cache is set to the data ready flag. The GPU processing module 14 switches from the processing state to the completed state.

[0091] For example, during the processing of radar spot data, the GPU processing module 14 can adaptively select the CUDA stream processing mode based on system operating status parameters. If the DMA wait queue length continues to increase, indicating a risk of congestion on the host side and a high system load, the GPU processing module 14 determines the CUDA stream processing mode to be simplified mode. The CUDA stream reduces computational complexity and shortens processing latency by executing some kernel functions. If the GPU computing resource idle rate exceeds a preset threshold, indicating a low system load, the GPU processing module 14 determines the CUDA stream processing mode to be normal mode. The CUDA stream executes all kernel functions to improve data processing accuracy. In this embodiment, the GPU processing module 14 adaptively selects the processing mode based on the system load parameters fed back by the performance monitoring module 11. When the system load is high, it executes the simplified processing mode to actively reduce the computational complexity of a single batch, thereby shortening the memory block occupation time, accelerating the release speed of page-locked memory blocks, improving the memory block turnover speed, and avoiding DMA write blocking due to excessive processing time, thus ensuring the overall response speed of the system. When the load is low, it executes the full processing mode to improve processing accuracy, thereby improving the stability of the system under sudden load scenarios.

[0092] When the CUDA stream is in the completed state, in response to the consumption completion signal output by the display module 15, the GPU processing module 14 releases the CUDA stream, outputs a memory block release notification signal to the page-locked memory management module 13, and switches from the completed state to the initialization state. In the completed state, the GPU processing module 14 waits for the display module 15 to return a consumption completion signal indicating the processing result; upon receiving the consumption completion signal, it releases the CUDA stream and video memory resources associated with the current processing task and notifies the page-locked memory management module 13 to reclaim the corresponding page-locked memory block. After the resource release and state reclamation operations are completed, the state machine returns to the initialization state.

[0093] This embodiment uses state machine control to achieve closed-loop operation of the GPU processing flow between the initialization, execution and recycling phases, keeping GPU resource scheduling synchronized with host-side data supply and ensuring the stability and continuity of the system processing flow.

[0094] In one embodiment, such as Figure 5 The diagram illustrates the data interaction between the GPU processing module 14 and the display control module 15. In response to detecting that the status flag of the shared memory cache is set to "data ready," the display control module 15 reads the processing result from the shared memory cache and performs a display rendering operation. The GPU processing module 14 writes the processing result to the shared memory cache and sets the "data ready" flag. The display control module 15 detects this "data ready" flag, reads the processing result from the shared memory cache, and performs a display rendering operation.

[0095] After the display rendering operation is completed, the display control module 15 outputs a consumption completion signal to the GPU processing module 14. After the display control module 15 finishes displaying, it sends a consumption completion signal to the GPU processing module 14. Upon receiving the consumption completion signal, the GPU processing module 14 releases the corresponding CUDA stream and sends a memory block release notification to the page-locked memory management module 13. Upon receiving the memory block release notification, the page-locked memory management module 13 resets the state of the corresponding page-locked memory block to the idle state.

[0096] This embodiment achieves secure delivery of GPU processing results, orderly consumption of display control, and timely reclamation of page-locked memory resources through a timing coordination mechanism. This ensures the continuity and stability of the system processing flow, establishes a clear synchronization relationship between processing result consumption and memory block release, and guarantees that memory resources are fully utilized before entering the next round of scheduling.

[0097] like Figure 6 As shown, this application provides a radar spot data processing method based on page-locked memory, the method comprising:

[0098] S601, obtain the system operating status parameters of the current sampling period, determine the comprehensive load factor based on the system operating status parameters, and adjust the capacity of the page-locked memory buffer pool according to the comprehensive load factor;

[0099] S602, writes the received radar spot data into any free page-locked memory block in the page-locked memory buffer pool after the execution capacity is adjusted, using direct memory access (DMA) mode.

[0100] S603, in response to detecting that a page-locked memory block write operation has been completed, outputs a memory block ready notification for the page-locked memory block;

[0101] S604, in response to a memory block ready notification, binds a page-locked memory block to a CUDA stream of a compute unified device architecture. The CUDA stream asynchronously transmits radar point data to GPU memory, performs parallel processing on the radar point data to obtain the processing result, and writes the processing result to the shared buffer of the memory cache.

[0102] S605, in response to the detection that a write operation to the shared buffer of the video memory cache has been completed, performs display rendering on the processing result and outputs a consumption completion signal;

[0103] S606, in response to a consumption completion signal, releases CUDA streams, GPU memory, and page-locked memory blocks.

[0104] This application also provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it implements the steps of any of the above-described page-locked memory-based radar spot data processing methods.

[0105] This application provides a schematic diagram of the hardware structure of an electronic device. The electronic device includes a processor, a communication interface, a memory, and a communication bus. The processor, communication interface, and memory communicate with each other via the communication bus. The connection method between the processor, communication interface, and memory is merely exemplary; in practice, the processor, communication interface, and memory may also communicate with each other using other connection methods besides the communication bus.

[0106] The memory can be used to store computer programs, which may include instructions and data to implement the steps of any of the above-described page-locked memory-based radar spot data processing methods. In the embodiments of this application, the memory can be various types of storage media, such as random access memory (RAM), read-only memory (ROM), non-volatile RAM (NVRAM), programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), flash memory, optical memory, and registers. The memory may include hard disks and / or RAM.

[0107] The processor can be a general-purpose processor, which performs specific steps and / or operations by reading and executing a computer program stored in memory (e.g., RAM). The general-purpose processor may use data stored in memory during the execution of these steps and / or operations. A general-purpose processor can be, for example, but not limited to, a central processing unit (CPU). Furthermore, the processor can also be a special-purpose processor, which is specifically designed to perform specific steps and / or operations. Special-purpose processors can be, for example, but not limited to, ASICs and FPGAs. Additionally, the processor can be a combination of multiple processors, such as a multi-core processor.

[0108] A communication interface can include input / output (I / O) interfaces, physical interfaces, and logical interfaces used for interconnecting devices within a network device, as well as interfaces used for interconnecting the network device with other devices (e.g., network devices). The communication network can be Ethernet, a radio access network (RAN), a wireless local area network (WLAN), etc. The communication interface can be a module, circuit, transceiver, or any device capable of enabling communication.

[0109] In implementation, each step of the above method can be completed by integrated logic circuits in the processor's hardware or by instructions in software. The method disclosed in the embodiments of this application can be directly implemented by a hardware processor, or by a combination of hardware and software modules in the processor. The software modules can reside in readily available storage media in the art, such as random access memory (RAM), read-only memory (ROM), programmable read-only memory (ROM), electrically erasable programmable memory (EPR), or registers. This storage medium is located in memory 803. The processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method. To avoid repetition, detailed descriptions are omitted here.

[0110] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. A and B can be singular or plural. Additionally, the character " / " in this article generally indicates an "or" relationship between the preceding and following related objects, but it can also represent an "and / or" relationship. Please refer to the context for a more accurate understanding.

[0111] In this application, "at least one" means one or more, and "more than one" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or multiple items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0112] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0113] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the apparatus embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0114] The above are merely preferred embodiments of this application and are not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. A radar spot data processing system based on page-locked memory, characterized in that, The system includes: The performance monitoring module is used to obtain the system operating status parameters of the current sampling period. Based on the normalized system operating status parameters and the multi-index fusion method, a comprehensive load factor is calculated. The comprehensive load factor is used to characterize the comprehensive load level of the system in multiple dimensions such as data access, memory turnover and GPU processing. The system operating status parameters include at least one of the following: PCIe bandwidth utilization, DMA wait queue length, GPU computing resource idle rate and page-locked memory buffer pool occupancy ratio. The page-locked memory management module is used to adjust the capacity of the page-locked memory buffer pool according to the comprehensive load factor. The receiving module is used to write the received radar spot data into any free page-locked memory block in the page-locked memory buffer pool with adjusted execution capacity using direct memory access (DMA). The GPU processing module is used to respond to the detection that the page-locked memory block write operation is completed, bind the page-locked memory block to a CUDA stream of a computing unified device architecture, asynchronously transmit the radar spot data to the GPU memory through the CUDA stream and perform parallel processing to obtain the processing result, and write the processing result to the shared buffer of the memory cache. The display control module is used to respond to the completion of writing the processing result, perform display rendering on the processing result, and output a consumption completion signal; The GPU processing module is configured to release the CUDA stream and the GPU memory in response to the consumption completion signal, and to notify the page-locked memory management module to release the page-locked memory block.

2. The radar spot data processing system based on page-locked memory according to claim 1, characterized in that, The page-locking memory management module is specifically used for: Determine whether the current sampling period is within a cooling period, where the cooling period is the time during which capacity adjustment is paused; If the current sampling period is within the cooling period, the page-locked memory management module temporarily freezes the capacity adjustment of the page-locked memory buffer pool; If the current sampling period is not within the cooling period, the page-locked memory management module performs capacity adjustment on the page-locked memory buffer pool, the capacity adjustment including: If the combined load factor of multiple consecutive sampling periods exceeds the first load threshold, the page-locked memory management module performs an expansion operation, and after the expansion operation is completed, the capacity of the page-locked memory buffer pool is adjusted to enter the cooling cycle. If the combined load factor of multiple consecutive sampling periods is lower than the second load threshold, the page-locked memory management module performs a containment operation and adjusts the capacity of the page-locked memory buffer pool to enter a cooling cycle after the containment operation is completed, wherein the first load threshold is greater than the second load threshold.

3. The radar spot data processing system based on page-locked memory according to claim 2, characterized in that, The page-locking memory management module is specifically used for: For each sampling period, If the overall load factor of the sampling period exceeds the first load threshold, the high load count value is incremented by one until the obtained high load count value exceeds the trigger count threshold, at which point the page locking memory management module performs an expansion operation. If the overall load factor of the sampling period is lower than the second load threshold, the low load count value is incremented by one until the acquired low load count value exceeds the trigger count threshold, at which point the page locking memory management module performs a containment operation.

4. The radar spot data processing system based on page-locked memory according to claim 1, characterized in that, The system operating status parameters include at least one of the following: DMA wait queue length and GPU computing resource idle rate, wherein the GPU processing module is specifically used for: The GPU processing module dynamically selects the processing mode of the CUDA stream based on the system operating status parameters, wherein, If the DMA wait queue length continues to grow, the GPU processing module determines that the processing mode of the CUDA stream is simplified mode, and the CUDA stream reduces computational complexity by executing some kernel functions; If the idle rate of the GPU computing resources exceeds a preset threshold, the GPU processing module determines that the processing mode of the CUDA stream is normal mode, and the CUDA stream executes all kernel functions.

5. The radar spot data processing system based on page-locked memory according to claim 1, characterized in that, The page-locking memory management module is specifically used for: For each page-locked memory block in the page-locked memory buffer pool, the state of the page-locked memory block includes an idle state, a writing state, a pending state, a processing state, and a releasing state. The state of the page-locked memory block is updated using a state machine approach. When the page-locked memory block is in an idle state, the page-locked memory management module responds to the memory block allocation request information output by the data receiving module and switches the state of the page-locked memory block from the idle state to the writing state. When the page-locked memory block is in the writing state, the data receiving module writes the radar spot data into the page-locked memory block in DMA mode. The page-locked memory management module records the transmission status and writing start time of the page-locked memory block, and switches the status of the page-locked memory block from the writing state to the pending state when the writing of the page-locked memory block is completed. When the page-locked memory block is in a pending state, the page-locked memory management module adds the page-locked memory block to the pending queue, updates the status timestamp, outputs a memory block ready notification to the GPU processing module, and in response to the GPU processing module, binds the page-locked memory block to the CUDA stream, and switches the status of the page-locked memory block from the pending state to the processing state. When the page-locked memory block is in the processing state, the page-locked memory block is bound to a CUDA stream. In response to the processing completion notification output by the GPU processing module, the page-locked memory management module switches the state of the page-locked memory block from the processing state to the releasing state. When the page-locked memory block is in the releasing state, the page-locked memory management module responds to the memory block release notification signal output by the GPU processing module and switches the state of the page-locked memory block from the releasing state to the idle state.

6. The radar spot data processing system based on page-locked memory according to claim 1, characterized in that, The GPU processing module is specifically used for, In response to the memory block ready notification, the GPU processing module selects any idle CUDA stream from the CUDA stream pool, establishes a binding relationship between the page-locked memory block in the pending state and the idle CUDA stream, and during the binding period, the lifecycle of the CUDA stream is synchronized with the lifecycle of the page-locked memory block. In response to the consumption completion signal, the GPU processing module releases the binding relationship between the page-locked memory block and the released CUDA stream, and releases the CUDA stream; The GPU processing module sets concurrency constraints on the CUDA stream pool, which ensure that the number of CUDA streams in a bound relationship does not exceed the sum of the number of page-locked memory blocks in the pending state and the number of page-locked memory blocks in the processing state.

7. The radar spot data processing system based on page-locked memory according to claim 6, characterized in that, The GPU processing module is specifically used for, For any CUDA stream in a binding relationship, the state of the CUDA stream includes an initialization state, a processing state, and a completion state. The state of the CUDA stream is updated using a finite state machine. When the CUDA stream is in the initialization state, the GPU processing module performs an initialization operation on the CUDA stream. In response to the completion of the initialization operation, the state of the CUDA stream is switched from the initialization state to the processing state. The initialization operation includes at least one of the following: creating a CUDA stream context, allocating a shared buffer for the processing result, and initializing the CUDA stream. When the CUDA stream is in the processing state, the CUDA stream asynchronously transmits the radar point data to the GPU memory, performs parallel processing on the radar point data to obtain the processing result, writes the processing result into the shared buffer of the memory cache, sets the status flag of the shared buffer of the memory cache to the data ready flag, and switches the state of the CUDA stream from the processing state to the completed state. When the CUDA stream is in the completed state, in response to the consumption completion signal output by the display control module, the GPU processing module releases the CUDA stream, outputs a memory block release notification signal to the page-locked memory management module, and switches the state of the CUDA stream from the completed state to the initialization state.

8. The radar spot data processing system based on page-locked memory according to claim 1, characterized in that, The display control module is specifically used for... In response to detecting that the status flag of the shared video memory cache is a data ready flag, the display control module reads the processing result from the shared video memory cache and performs a display rendering operation; Once the display rendering operation is completed, the display control module outputs a consumption completion signal to the GPU processing module.

9. The radar spot data processing system based on page-locked memory according to claim 1, characterized in that, The data receiving module is connected to an external radar acquisition device via a PCIe bus. Specifically, the data receiving module is used for... The data receiving module receives radar point data output by the radar acquisition device and outputs memory block allocation request information to the page-locked memory management module. When the page-locked memory block allocated by the page-locked memory management module is in a write state, the data receiving module writes the radar spot data into the page-locked memory block in a DMA manner.

10. A radar spot data processing method based on page-locked memory, characterized in that, The method includes: The system operating status parameters for the current sampling period are obtained. A comprehensive load factor is calculated based on the normalized system operating status parameters and a multi-index fusion method. The capacity of the page-locked memory buffer pool is adjusted according to the comprehensive load factor. The comprehensive load factor is used to characterize the comprehensive load level of the system in multiple dimensions such as data access, memory turnover and GPU processing. The system operating status parameters include at least one of the following: PCIe bandwidth utilization, DMA wait queue length, GPU computing resource idle rate and page-locked memory buffer pool occupancy ratio. The received radar spot data is written to any free page-locked memory block in the page-locked memory buffer pool with adjusted execution capacity using direct memory access (DMA). In response to the detection that the page-locked memory block write operation is complete, a memory block ready notification for the page-locked memory block is output; In response to the memory block ready notification, the page-locked memory block is bound to a CUDA stream of a compute unified device architecture. The CUDA stream asynchronously transmits the radar spot data to the GPU memory and performs parallel processing on the radar spot data to obtain the processing result, which is then written to the shared buffer of the memory cache. In response to the detection that the write operation to the shared buffer of the video memory cache is complete, the processing result is displayed and rendered, and a consumption completion signal is output. In response to the consumption completion signal, the CUDA stream, the GPU memory, and the page-locked memory block are released.

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