High-speed data sending method based on DDR (Double Data Rate)

Abstract

The invention discloses a DDR-based high-speed data sending method, and belongs to the technical field of data transmission. The method is applied to a data transmission system comprising an FPGA main control chip, a DDR cache module, an NVME storage module and an optical fiber sending module. The method comprises a data receiving and preprocessing step, a DDR cache writing step, a cache data reading step, a data storage step and a data sending step. According to the method, the DDR memory is used as a high-speed cache medium, the double data rate transmission characteristic of the DDR and a DMA direct memory access mechanism are utilized, efficient data carrying is achieved, and the bandwidth limitation of a traditional bus is broken through. An annular queue is adopted to manage a storage space, read-write parallelization of double DDR groups is realized through a ping-pong operation mode, and a flow control mechanism is set to coordinate upstream and downstream data streams. The method is suitable for video monitoring, radar signal processing and other application scenes needing continuous high-speed data output.

Description

Technical Field

[0001] This invention relates to the field of data transmission technology, and more specifically to a high-speed data transmission method based on DDR. Background Technology

[0002] In the context of high-speed modern data transmission technology, data transmission speed and efficiency have become crucial factors restricting technological progress. Current high-speed data transceiver solutions generally employ industrial control computers based on PCIe or PXIe architectures, using a host computer to interact with a fiber optic transceiver module to achieve data transmission. In the specific implementation, the host computer sends data to the slave computer through the fiber optic transceiver module's driver program, utilizing the FIFO buffer structure within the FPGA. FIFO is a first-in-first-out buffer structure, which can optimize data transmission efficiency and timing matching issues to a certain extent.

[0003] However, traditional FIFO-based data transmission schemes have inherent technical bottlenecks. Since data transmission bandwidth is directly limited by the bandwidth of the bus or communication interface itself, the actual transmission rate cannot exceed the bus's maximum bandwidth, making it difficult to further improve the system's data throughput. Simultaneously, in traditional schemes, the CPU frequently participates in the data transfer process, consuming significant processor resources and reducing the overall system efficiency. Furthermore, in existing high-speed data transmission and storage schemes, fiber optic communication and storage functions are typically distributed across different boards, requiring data transmission between these boards via a bus. This not only increases data processing latency but also results in a large system footprint, making it difficult to meet the requirements of device miniaturization.

[0004] With the rapid development of DDR memory and FPGA technologies, leveraging the high-speed read / write characteristics of DDR for data transmission has become a new technological approach. DDR employs a dual-edge triggered operating mechanism, allowing data transmission on both the rising and falling edges of the clock signal, thus doubling the data transfer rate at the same clock frequency. Combined with DMA (Direct Memory Access) mechanisms, direct data transfer between peripherals and memory can be achieved, reducing CPU intervention. However, effectively utilizing DDR memory as a high-speed cache medium and achieving efficient data transmission through reasonable data management and scheduling mechanisms remain key technical challenges that need to be addressed. Summary of the Invention

[0005] To address the problems existing in the background technology, this invention provides a high-speed data transmission method based on DDR, which is applied to a data transmission system including an FPGA main control chip, a DDR cache module, an NVME storage module, and an optical fiber transmission module. The method includes the following steps:

[0006] S1. Data Reception and Preprocessing Steps: The FPGA main control chip receives the data to be transmitted sent by the host computer through the PXIE bus interface, performs format parsing and data packet reassembly on the data to be transmitted, and generates standardized data frames.

[0007] S2, DDR cache writing step: The FPGA main control chip writes the standardized data frame into the DDR cache module according to the preset address mapping rules, establishes a data cache queue, and records the storage address and data length information of each data frame;

[0008] S3. Cache data reading steps: The FPGA main control chip reads the data frame to be sent from the DDR cache module according to the data sending request and the first-in-first-out principle, and performs data integrity verification.

[0009] S4. Data storage steps: The FPGA main control chip writes the verified data frame to the NVME storage module for persistent storage through the PCIE interface, and updates the data storage status table at the same time.

[0010] S5. Data transmission steps: The FPGA main control chip reads data from the NVME storage module according to the transmission protocol, and sends the data to the optical fiber transmission module through the GTH high-speed serial interface to complete the high-speed data transmission.

[0011] In the preferred embodiment, step S1 specifically includes:

[0012] S11, PXIE bus initialization: The FPGA main control chip configures the link parameters of the PXIEx8 interface, including link speed, data bit width and transmission mode, and establishes a communication link with the host computer.

[0013] S12. Data packet reception: The FPGA main control chip receives the raw data packet sent by the host computer via DMA and stores the raw data packet in the receiving buffer.

[0014] S13, Protocol Parsing: Parse the protocol header of the data packets in the receive buffer to extract the packet header information, payload length and checksum of the data packets;

[0015] S14. Data Frame Reassembly: Based on the protocol parsing results, the payload data is divided or merged according to the preset frame length to generate standardized data frames of fixed length. Each standardized data frame contains a frame header, data field, and frame tail checksum.

[0016] In a preferred embodiment, the DDR cache module includes a first DDR group and a second DDR group. The first DDR group uses four DDR4 chips connected in parallel to form a 64-bit data width, and the second DDR group uses two DDR4 chips connected in parallel to form a 32-bit data width. Step S2 specifically includes:

[0017] S21, DDR Initialization Configuration: The FPGA main control chip initializes the first DDR group and the second DDR group respectively, and configures the DDR working clock, refresh cycle and timing parameters;

[0018] S22, Address Space Allocation: Divide the DDR storage space into multiple logical partitions, assign a starting address and capacity to each partition, and establish an address mapping table;

[0019] S23. Write Address Calculation: Calculate the target write address based on the current write pointer position and the data frame length. The formula for calculating the target write address is as follows:

[0020] ;

[0021] Where Addr_write is the target write address; Base_addr is the partition start base address; W_ptr is the current write pointer value; Frame_size is the byte length of the normalized data frame (bytes); Total_size is the total partition capacity (bytes); mod is the modulo operator;

[0022] S24. Burst Write Operation: The DDR burst transfer mode is used to write the standardized data frame to the target address. After the write is completed, the write pointer and data frame counter are updated to generate a data frame descriptor containing address and length information.

[0023] In the preferred embodiment, step S3 specifically includes:

[0024] S31. Read Request Judgment: The FPGA main control chip detects the data sending request signal and determines whether the DDR cache queue is not empty.

[0025] S32. Read Address Calculation: Calculate the target read address based on the read pointer position. The formula for calculating the target read address is as follows:

[0026] ;

[0027] Where Addr_read is the target read address; Base_addr is the partition's starting base address; R_ptr is the current read pointer value; Frame_size is the byte length of the normalized data frame; Total_size is the total partition capacity; and mod is the modulo operator.

[0028] S33, Burst Read Operation: Uses DDR burst transfer mode to read a complete data frame from the target address into the read buffer;

[0029] S34. Data Verification: Perform CRC verification on the read data frame. If the verification passes, update the read pointer and output the data frame. If the verification fails, mark the error and trigger the reread mechanism.

[0030] In a preferred embodiment, the method for determining whether the DDR cache queue is non-empty in step S31 is as follows:

[0031] The number of cached data frames is calculated using the following formula:

[0032] ;

[0033] in, This represents the number of data frames currently cached. To write pointer value; This is the read pointer value; Queue_depth is the depth of the cache queue; mod is the modulo operator; when When the value is greater than 0, the cache queue is determined to be in a non-empty state.

[0034] In a preferred embodiment, the NVMe storage module includes two solid-state drives connected to the FPGA main control chip via a PCIe x4 interface; step S4 specifically includes:

[0035] S41. Storage path selection: Select the target storage disk based on the current load status and remaining capacity of the two solid-state drives;

[0036] S42, NVME command generation: Generate an NVME write command based on the length of the data frame to be stored and the target storage address. The NVME write command includes a command opcode, a logical block address, and a data length.

[0037] S43, DMA data transfer: Transfers data frames from the read buffer to the write buffer of the NVMe storage module via PCIe DMA;

[0038] S44. Storage Status Update: After the NVME storage module completes the data writing, it returns a completion status. The FPGA main control chip updates the data storage status table and records the storage location and storage timestamp of the data frame.

[0039] In a preferred embodiment, the optical fiber transmitting module is a 12-channel parallel optical transceiver module; step S5 specifically includes:

[0040] S51, Sending Task Scheduling: The FPGA main control chip determines the storage location of the data to be sent according to the sending protocol and generates an NVME read command;

[0041] S52, Data Read: Read the data to be sent from the solid-state drive into the send buffer using the NVME read command;

[0042] S53. Encoding Processing: Encode the data to be transmitted into 8B / 10B or 64B / 66B encoding to generate an encoded data stream suitable for high-speed serial transmission.

[0043] S54, GTH serial transmission: The FPGA's GTH high-speed transceiver converts the encoded data stream into a high-speed serial signal, which is then transmitted to the device under test via the fiber optic transmission module, completing the data transmission process.

[0044] In the preferred embodiment, the first DDR group and the second DDR group use a ping-pong operation mode for data caching, specifically as follows:

[0045] When the first DDR group is in the data writing state, the second DDR group is in the data reading state;

[0046] After the first DDR group completes the writing of a data block, it switches to the read state, and at the same time the second DDR group switches to the write state;

[0047] Continuous data processing is achieved through ping-pong operations, thereby improving data throughput.

[0048] In a preferred embodiment, the method further includes a flow control step:

[0049] Calculate the cache utilization rate, and the formula for calculating the cache utilization rate is:

[0050] ;

[0051] Wherein, Occupancy is the cache utilization rate (%). The current number of cached data frames; Queue_depth is the depth of the cache queue;

[0052] When the cache occupancy rate exceeds the preset high watermark threshold, a pause request signal is sent to the host computer; when the cache occupancy rate is lower than the preset low watermark threshold, a resume transmission signal is sent to the host computer.

[0053] In a preferred embodiment, the data transmission system further includes a clock management module, which provides synchronous clock signals to the FPGA main control chip, DDR cache module, NVME storage module and fiber optic transmission module to ensure the timing consistency of data transmission between the modules.

[0054] The beneficial effects achieved by this invention are as follows:

[0055] This invention utilizes DDR memory as a high-speed cache medium, leveraging its double data rate transmission capability and combining it with Direct Memory Access (DMA) to achieve efficient data transfer between memory and peripherals. Since DDR can transmit data on both the rising and falling edges of the clock signal, its data throughput is doubled compared to traditional single-edge triggered memory at the same clock frequency. Simultaneously, the DMA mechanism allows peripherals to directly access memory for data transfer without full CPU involvement, thus reducing the CPU's workload and improving overall system efficiency. By first writing data to the DDR cache and then directly transmitting it under FPGA control, the data transmission process is freed from the limitations of traditional bus bandwidth, overcoming the bottleneck of data throughput.

[0056] This invention employs a circular queue approach to manage DDR memory space, achieving ordered data access through the coordinated operation of write and read pointers. A circular queue is a queue structure where the pointer automatically wraps back to the beginning when it reaches the end of the memory space, thus enabling the cyclical use of the storage space. This organization method avoids frequent memory allocation and deallocation operations, simplifies address calculation logic, and reduces the complexity of memory management. Through preset address mapping rules and modulo operations, the target read / write address is always limited to the effective storage range, ensuring the correctness and reliability of data access.

[0057] The DDR cache module of this invention employs a dual-DDR group configuration and achieves continuous pipelined data processing through a ping-pong operation mode. When one DDR group is in the data writing state, the other DDR group is simultaneously in the data reading state. The two DDR groups alternately switch their working states, allowing read and write operations to be executed in parallel. The essence of the ping-pong operation is to avoid the waiting time caused by read-write conflicts through a double buffering mechanism, thereby improving data throughput. This working mode is particularly suitable for application scenarios with continuous data flow and high real-time requirements, effectively ensuring the continuity and stability of data transmission.

[0058] This invention also incorporates a flow control mechanism. By monitoring the cache occupancy status and sending control signals to the host computer based on preset high and low watermark thresholds, the system coordinates the matching relationship between upstream and downstream data flows. When the cache occupancy rate exceeds the high watermark threshold, the system requests the host computer to suspend data transmission to avoid cache overflow; when the cache occupancy rate falls below the low watermark threshold, the system notifies the host computer to resume data transmission to avoid data underload. Through this flow control mechanism, the system can maintain stable operation under different data flow rates, improving the reliability and adaptability of data transmission. Furthermore, this invention introduces CRC checksum and reread mechanisms during data reading to further ensure the integrity and correctness of data transmission. Attached Figure Description

[0059] Figure 1This is a schematic diagram of the host computer software flow of Embodiment 1 of the present invention;

[0060] Figure 2 This is a hardware system block diagram used in Embodiment 1 of the present invention;

[0061] Figure 3 This is a data transmission flow diagram of Embodiment 1 of the invention. Detailed Implementation

[0062] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. In addition, the forms of the various structures described in the following embodiments are merely illustrative. The present invention is not limited to the structures described in the following embodiments. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0063] The high-speed data transmission method based on DDR provided by this invention is applied to a data transmission system comprising an FPGA main control chip, a DDR cache module, an NVME storage module, and an optical fiber transmission module. This system uses DDR memory as a high-speed cache medium, leveraging DDR's double data rate transmission characteristics and combining it with DMA (Direct Memory Access) mechanism to achieve efficient data transfer between memory and peripherals, reducing the number of CPU interventions, thereby breaking through the limitations of traditional bus bandwidth and improving overall data transmission efficiency.

[0064] The FPGA main control chip, as the core control unit of the entire data transmission system, is responsible for coordinating data interaction between various modules. The DDR cache module is connected to the FPGA main control chip via a high-speed bus and is used to temporarily store data to be transmitted. Its dual-edge triggered operating mechanism doubles the data transmission rate at the same clock frequency. The NVMe storage module is connected to the FPGA main control chip via a PCIe interface for persistent data storage. The fiber optic transmission module is connected to the FPGA main control chip via a GTH high-speed serial interface and is responsible for transmitting data to external devices in the form of optical signals.

[0065] The data transmission system also includes a clock management module, which is connected to the FPGA main control chip, DDR cache module, NVME storage module, and fiber optic transmission module to provide synchronous clock signals for each module. The clock management module uses a phase-locked loop circuit to generate a stable reference clock and distributes the clock signal to each functional module through a clock buffer to ensure the timing consistency of data transmission between modules and avoid data sampling errors caused by clock deviations.

[0066] The high-speed data transmission method based on DDR of the present invention includes the following steps.

[0067] Step S1: Data Reception and Preprocessing. Step S1 involves data reception and preprocessing. The FPGA main control chip receives the data to be transmitted from the host computer via the PXIE bus interface, performs format parsing and data packet reassembly on the data to be transmitted, and generates standardized data frames. The PXIE bus is a high-speed serial bus standard based on PCI Express technology, featuring high bandwidth and low latency, suitable for high-speed data acquisition and transmission scenarios. During the data reception process, the receiving logic inside the FPGA main control chip performs protocol identification and format conversion on the raw data stream, unifying raw data packets of different lengths into standardized data frames of a fixed format, facilitating subsequent storage management and transmission scheduling.

[0068] Step S1 specifically includes the following sub-steps. Step S11 initializes the PXIE bus. The FPGA main control chip configures the link parameters of the PXIEx8 interface, including the link speed, data bit width, and transmission mode, establishing a communication link with the host computer. During initialization, the XDMAIP core inside the FPGA main control chip is responsible for negotiating and establishing the PCIE link. The XDMAIP core is a PCIE interface IP core that supports DMA transfer, enabling efficient data transfer. The configuration of the link speed determines the peak bandwidth of data transmission, the configuration of the data bit width affects the amount of data transmitted in a single transmission, and the selection of the transmission mode relates to the reliability and efficiency of data transmission. After initialization, a stable data channel is established between the FPGA main control chip and the host computer, preparing for subsequent data transmission.

[0069] Step S12 involves data packet reception. The FPGA main control chip receives the raw data packet sent by the host computer via DMA and stores it in the receive buffer. DMA, or Direct Memory Access, is a data transfer method that allows peripherals to directly access memory without the CPU's full involvement, thus reducing the CPU load and improving transfer efficiency. During DMA transfer, the XDMAIP core automatically moves data from the PCIe interface to the receive buffer according to a preset transfer descriptor. The transfer descriptor contains information such as the source address, destination address, and transfer length. The receive buffer is typically located in the FPGA's internal BlockRAM, offering advantages such as high access speed and low latency.

[0070] Step S13 involves protocol parsing, which parses the protocol header of the data packets in the receive buffer, extracting the packet header information, payload length, and checksum. The protocol header is typically located at the beginning of the data packet and contains metadata such as data type identifier, sequence number, and length field. The payload is the actual user data carried in the data packet, and its length is indicated by the length field in the protocol header. The checksum is used to verify whether errors have occurred during data packet transmission; commonly used checksum algorithms include CRC (Cyclic Redundancy Check) and checksum algorithms. Through protocol parsing, the FPGA main control chip can accurately identify the boundaries and content of each data packet, providing a basis for data frame reassembly.

[0071] Step S14 involves data frame reassembly. Based on the protocol parsing results, the payload data is segmented or merged according to a preset frame length to generate standardized data frames of fixed length. Each standardized data frame includes a frame header, a data field, and a frame tail checksum. The frame header records management information such as the frame sequence number, timestamp, and data length. The data field stores the actual payload data, and the frame tail checksum is used to verify data integrity during subsequent readings. Using standardized data frames of fixed length simplifies DDR memory management and address calculation, while also facilitating sequential and random data access.

[0072] Step S2 is the DDR cache write step. In this step, the FPGA main control chip writes standardized data frames into the DDR cache module according to a preset address mapping rule, establishing a data cache queue and recording the storage address and data length information of each data frame. The DDR cache module manages the storage space using a circular queue organization method. A circular queue is a queue structure where the head and tail are connected. When the write pointer reaches the end of the storage space, it automatically wraps back to the beginning, thus realizing the circular utilization of the storage space. This organization method avoids frequent memory allocation and release operations, improving storage efficiency.

[0073] The DDR cache module includes a first DDR group and a second DDR group. The first DDR group uses four DDR4 chips connected in parallel to form a 64-bit data bus width, while the second DDR group uses two DDR4 chips connected in parallel to form a 32-bit data bus width. DDR4 is the fourth generation of Double Data Rate Synchronous Dynamic Random Access Memory, offering higher data transfer rates and lower operating voltages compared to its predecessors. Connecting multiple chips in parallel expands the data bus width, increasing the data throughput per access. The 64-bit bus width of the first DDR group is suitable for bulk transfers of large data volumes, while the 32-bit bus width of the second DDR group is suitable for flexible access of small data volumes.

[0074] Step S2 specifically includes the following sub-steps. Step S21 is the DDR initialization configuration. The FPGA main control chip initializes the first DDR group and the second DDR group respectively, configuring the DDR operating clock, refresh cycle, and timing parameters. DDR memory needs to be refreshed periodically to maintain data; the refresh cycle setting needs to strike a balance between data retention reliability and access efficiency. Timing parameters include CAS latency, row address to column address latency, and row precharge time, etc. Correct configuration of these parameters is a prerequisite for stable DDR operation. The FPGA main control chip completes the DDR initialization configuration through the MIG controller. MIG is a dedicated DDR controller IP core that provides a standard AXI bus interface for user logic to access DDR.

[0075] Step S22 involves address space allocation, dividing the DDR storage space into multiple logical partitions, assigning a starting address and capacity to each partition, and establishing an address mapping table. The purpose of address space allocation is to organize the physical storage space into logically contiguous storage areas, facilitating orderly data management. Each logical partition can correspond to an independent data channel or data type, and partitions are isolated from each other to avoid data confusion. The address mapping table records information such as the starting address, capacity, and current usage status of each partition. The FPGA main control chip completes the conversion from logical address to physical address by querying the address mapping table.

[0076] Step S23 involves calculating the write address, based on the current write pointer position and the data frame length. The write pointer is a counter used to track the current write position; its value increments after each data frame is written. The target write address is calculated using a base address plus an offset. The offset is determined by the product of the write pointer value and the data frame length, and is limited to the partition capacity using a modulo operation to achieve the wraparound function of the circular queue. The formula for calculating the target write address is as follows: ;

[0077] In this formula, Addr_write is the target write address; Base_addr is the partition's starting base address; W_ptr is the current write pointer value; Frame_size is the length of the normalized data frame in bytes; Total_size is the total partition capacity in bytes; and mod is the modulo operator, used to wrap the address around. The write address calculated using this formula always remains within the partition's effective address range. When the write pointer increments to the point where the offset exceeds the partition capacity, the modulo operation automatically wraps the address back to near the partition's starting position, achieving circular utilization of storage space.

[0078] Step S24 is a burst write operation, which uses the DDR burst transfer mode to write a standardized data frame to the target address. After the write is completed, the write pointer and data frame counter are updated to generate a data frame descriptor containing address and length information. Burst transfer is an efficient data transfer mode of DDR, which can continuously transfer multiple data packets after a single address transmission, reducing address transfer overhead and improving data transfer efficiency. The burst length can be configured according to actual needs; commonly used burst lengths include 4-packets, 8-packets, and 16-packets. The data frame descriptor is a data structure that records the storage location and size of the data frame in DDR for subsequent read operations.

[0079] The first and second DDR groups employ a ping-pong operation mode for data caching to achieve continuous data pipelined processing. When the first DDR group is in data writing mode, the second DDR group is in data reading mode. After the first DDR group completes the writing of a data block, it switches to reading mode, while the second DDR group switches to writing mode. The essence of ping-pong operation is to parallelize read and write operations through a double buffering mechanism, avoiding waiting time caused by read / write conflicts, thereby improving data throughput. This operating mode is particularly suitable for applications with continuous data flow and high real-time requirements.

[0080] Step S3 is the cache data reading step. In step S3, the FPGA main control chip reads the data frame to be sent from the DDR cache module according to the data transmission request, following a first-in-first-out (FIFO) principle, and performs data integrity verification. The FIFO principle ensures that data is read out sequentially according to the writing order, maintaining data timing consistency. Data integrity verification is used to detect whether errors have occurred during data storage and retrieval, ensuring the correctness of the transmitted data.

[0081] Step S3 specifically includes the following sub-steps.

[0082] Step S31 involves determining the read request. The FPGA main control chip detects the data transmission request signal and checks whether the DDR cache queue is not empty. A non-empty cache queue indicates the presence of data frames to be read, allowing the chip to respond to the transmission request. The method for determining whether the cache queue is non-empty is to calculate the number of cached data frames. The formula for calculating the number of cached data frames is: ;

[0083] Where N_buffer is the number of data frames currently buffered; W_ptr is the write pointer value; R_ptr is the read pointer value; Queue_depth is the buffer queue depth; and mod is the modulo operator. This formula determines the number of data frames in the queue by calculating the difference between the write pointer and the read pointer. The modulo operation after adding the queue depth is used to handle cases where the write pointer, after wrapping around, is less than the read pointer. When N_buffer is greater than 0, the buffer queue is considered non-empty, and a read operation can be performed.

[0084] Step S32 involves calculating the read address, based on the read pointer position. The read pointer tracks the current read position and works with the write pointer to manage the circular queue. The target read address is calculated similarly to the write address, using a base address plus an offset. The formula for calculating the target read address is:

[0085] ;

[0086] Where Addr_read is the target read address; Base_addr is the partition's starting base address; R_ptr is the current read pointer value; Frame_size is the byte length of the normalized data frame; Total_size is the total partition capacity; and mod is the modulo operator. This formula ensures that the read address always points to a valid data storage location and cyclically changes within the partition as the read pointer increments.

[0087] Step S33 is a burst read operation, which uses DDR burst transfer mode to read a complete data frame from the target address into the read buffer. The read buffer is used to temporarily store the data read from DDR, providing a data source for subsequent checksum and transmission operations. Burst read and burst write use the same transfer mode, reducing address overhead and improving read efficiency through continuous data transmission. The FPGA main control chip controls the DDR read operation through the FDMA IP core. FDMA is a custom DMA controller IP core that supports data conversion between user-defined buses and AXI buses.

[0088] Step S34 is data verification. A CRC check is performed on the read data frame. If the check passes, the read pointer is updated and the data frame is output. If the check fails, an error is marked and a reread mechanism is triggered. CRC, or Cyclic Redundancy Check, is an error detection algorithm based on polynomial division, characterized by strong error detection capability and high computational efficiency. When writing to DDR, the FPGA main control chip pre-calculates the CRC check value of the data frame and appends it to the frame end. During reading, the CRC value of the read data is recalculated and compared with the stored check value. If they match, the data is considered correct. The reread mechanism automatically rereads the data frame when the check fails, improving the reliability of data transmission.

[0089] The method of this invention also includes a flow control step to coordinate the data flow between the host computer and the data transmission system, preventing buffer overflow or underload caused by a mismatch between the data generation rate and the consumption rate. The core of flow control is monitoring the buffer occupancy status and sending a control signal to the host computer according to a preset threshold. The formula for calculating the buffer occupancy rate is as follows: ;

[0090] Where Occupancy is the cache utilization rate; N_buffer is the number of data frames currently cached; and Queue_depth is the cache queue depth. When the cache utilization rate exceeds the preset high-water mark threshold, a pause request signal is sent to the host computer, requesting the host computer to pause data transmission to avoid cache overflow. When the cache utilization rate falls below the preset low-water mark threshold, a resume transmission signal is sent to the host computer, notifying the host computer to continue sending data. The settings of the high-water mark threshold and the low-water mark threshold need to be adjusted according to the actual data flow characteristics of the system to achieve a balance between cache utilization and transmission continuity.

[0091] Step S4 is the data storage step. The FPGA main control chip writes the verified data frames to the NVME storage module via the PCIe interface for persistent storage, and simultaneously updates the data storage status table. NVME, or Non-Volatile Memory Express, is a high-speed storage interface protocol based on the PCIe bus, offering lower access latency and higher transmission bandwidth compared to the traditional SATA interface. Persistent storage saves data on non-volatile storage media, ensuring data retention even during system power outages, making it suitable for applications requiring long-term data preservation.

[0092] The NVMe storage module consists of two solid-state drives (SSDs) connected to the FPGA controller chip via a PCIe x4 interface. The two SSDs can be configured to operate independently or collaboratively. In independent mode, each SSD stores different types of data, while in collaborative mode, data redundancy backup or bandwidth expansion can be achieved.

[0093] Step S4 specifically includes the following sub-steps. Step S41 is storage path selection, which selects the target storage disk based on the current load status and remaining capacity of the two solid-state drives (SSDs). The load status reflects the current busy / idle level of the SSDs; selecting a storage disk with a lower load can reduce waiting time. The remaining capacity reflects the available storage space of the SSDs; selecting a storage disk with sufficient remaining capacity can prevent storage space from being exhausted. The storage path selection strategy can be customized according to actual application needs, such as using a round-robin strategy, a minimum load strategy, or a capacity balancing strategy.

[0094] Step S42 generates the NVME command. Based on the length of the data frame to be stored and the target storage address, an NVME write command is generated. The NVME write command includes a command opcode, a logical block address, and a data length. The command opcode indicates that the command type is a write operation, the logical block address specifies the storage location of the data on the solid-state drive (SSD), and the data length indicates the amount of data to be written. The NVME command follows the command format defined by the NVMe specification. The FPGA main control chip submits the assembled command to the SSD's submission queue, and the SSD controller retrieves the command from the queue and executes it.

[0095] Step S43 is DMA data transfer, which uses PCIe DMA to transfer the data frame from the read buffer to the write buffer of the NVMe storage module. PCIe DMA transfer utilizes the high bandwidth of the PCIe bus to achieve high-speed data transfer. During the transfer, the DMA controller of the FPGA main control chip automatically completes the data transfer from the source address to the destination address according to the transfer descriptor. The CPU does not need to participate in the actual data transfer work, thereby saving CPU resources and improving transfer efficiency.

[0096] Step S44 involves updating the storage status. After the NVME storage module completes the data writing, it returns a completion status. The FPGA main control chip then updates the data storage status table, recording the storage location and timestamp of the data frame. The completion status is returned through the NVME's completion queue, which the FPGA main control chip obtains through polling or interrupts. The data storage status table is a management data structure that records the metadata of each stored data frame, including the storage device number, logical block address, data length, and storage time, for use in subsequent data reading and management operations.

[0097] Step S5 is the data transmission step. In step S5, the FPGA main control chip reads data from the NVME storage module according to the transmission protocol and sends the data to the fiber optic transmission module via the GTH high-speed serial interface, completing the high-speed data transmission. GTH is a high-speed serial transceiver inside the FPGA, supporting multiple serial communication protocols and featuring high transmission rate and low bit error rate. The fiber optic transmission module converts electrical signals into optical signals for long-distance transmission through the fiber optic medium, offering advantages such as strong anti-interference capability and large transmission bandwidth.

[0098] The fiber optic transmission module is a 12-channel parallel optical transceiver module, capable of simultaneously transmitting multiple data streams in parallel, further enhancing the system's data throughput. This module uses MPO-type fiber optic connectors, featuring high density and easy plugging / unplugging, making it suitable for high-speed data centers and communication equipment.

[0099] Step S5 specifically includes the following sub-steps. Step S51 is the transmission task scheduling. The FPGA main control chip determines the storage location of the data to be transmitted according to the transmission protocol and generates an NVME read command. The transmission protocol defines the order, timing, and format requirements for data transmission. The FPGA main control chip queries the data storage status table according to the protocol requirements to determine the data frames to be transmitted and their storage locations on the solid-state drive.

[0100] Step S52 involves data reading, where the data to be sent is read from the solid-state drive (SSD) into the transmit buffer using an NVME read command. The format of the NVME read command is similar to that of the write command, including the command opcode, logical block address, and data length. Upon receiving the read command, the SSD controller reads the data from the specified logical block address and transmits it to the transmit buffer of the FPGA main control chip via PCIeDMA. The transmit buffer temporarily stores the data to be sent, providing a data source for subsequent encoding and transmission operations.

[0101] Step S53 involves encoding the data to be transmitted, performing either 8B / 10B or 64B / 66B encoding to generate an encoded data stream suitable for high-speed serial transmission. 8B / 10B encoding converts 8-bit data into 10-bit symbols, introducing DC balance and sufficient signal transitions to facilitate clock recovery and data synchronization at the receiving end. 64B / 66B encoding converts 64-bit data into 66-bit symbols, offering higher encoding efficiency and suitability for higher-speed serial transmission. The choice of encoding method depends on the transmission rate and protocol requirements; the encoder within the FPGA main control chip performs the encoding conversion.

[0102] Step S54 is the GTH serial transmission. The FPGA's GTH high-speed transceiver converts the encoded data stream into a high-speed serial signal, which is then transmitted to the device under test via the fiber optic transmission module, completing the data transmission process. The GTH transceiver integrates a serializer and driver circuitry to convert the parallel encoded data into a high-speed serial differential signal. The serial signal is connected to the electro-optical conversion unit of the fiber optic transmission module via high-speed differential traces. The electro-optical conversion unit modulates the electrical signal into an optical signal and couples it to the optical fiber. The optical signal propagates in the optical fiber and, upon reaching the receiving end, is converted back into an electrical signal by the photoelectric conversion unit, completing the long-distance data transmission.

[0103] Data bit width conversion is involved in the process of reading data from DDR to fiber optic transmission. After the FPGA main control chip reads data from DDR via FDMA, it buffers the data into a bit width conversion FIFO. Since the bit width of the data sent by the host computer is usually larger than the bit width of the fiber optic transmission interface, bit width conversion is required through a FIFO. The FIFO's input side handles wide-bit-width data, and the output side handles narrow-bit-width data. Continuous data output is achieved by matching the FIFO's read / write clock ratio. During the bit width conversion process, the byte valid bit also needs to be processed. The byte valid bit indicates whether each byte carries valid data. The interface module determines the valid range of the data based on the byte valid bit, ensuring that only valid data is sent to the fiber optic channel.

[0104] This invention presents a high-speed data transmission method based on DDR memory. By using DDR memory as a high-speed cache medium, it leverages the double data rate transmission capability of DDR and the efficient data transfer mechanism of DMA to achieve high-speed data caching and transmission. A circular queue is used to manage the DDR storage space, simplifying address calculation and space management; ping-pong operations enable parallel read and write operations, improving data throughput; and a flow control mechanism coordinates upstream and downstream data flows, ensuring data transmission stability. This method overcomes the limitations of traditional bus bandwidth and is suitable for applications requiring continuous high-speed data output, such as video surveillance and radar signal processing.

[0105] Example 1, referring to Figures 1-3 This embodiment mainly involves data transmission. The host computer adds the SDK for the fiber optic transceiver module driver and imports the interactive programmable interface. The user interface of the host computer and the software for calling the fiber optic transceiver module driver are separated into two parts: interface software and service software. The interface software can be drawn using C# WinForms or WPF. The service software uses C++ for easy compatibility with the fiber optic transceiver module's SDK. The two software parts establish request-response and publish-subscribe links through high-performance asynchronous messaging libraries such as ZMQ. Cross-language message communication can be achieved using the ProtoBuf serialized structured data format. Ultimately, this achieves the separation and distributed deployment of the software interface and functionality, i.e., the separation of the user's operating computer and the workstation where the fiber optic transceiver module resides.

[0106] Data transmission can be divided into the following steps:

[0107] (1) Map the data transmission path to the drive path of the fiber optic transceiver module and save it as an XML configuration file for easy loading. For example, the data transmission path "Image Transmission 1" corresponds to "Card No. 0 Channel 1" of the fiber optic transceiver module.

[0108] (2) Use .NET's WPF to draw the host computer sending interface. The interface should include the file path of the data to be sent, enable and disable each transmission, frame length and frame interval of each transmission, number of transmissions, start writing to DDR, stop writing to DDR, start sending to DDR, stop sending to DDR, etc.

[0109] (3) The host computer writes to DDR, and the interface software sends a ProtoBuf serialization command to the service software through the ZMP interface. The service software starts a thread, which uses a file stream to read large files from the local hard drive, reading 64MB at a time and writing them to the fiber optic transmission module FPGA.

[0110] The FPGA incorporates a BLOCKDESIGN core responsible for data exchange between the CPU and FPGA. The FPGA and CPU interact via XDMAIP (DMA subsystem for PCI Express, an upgraded version of the PCIe IP core provided by Xilinx). The CPU sends the fiber optic data to be transmitted via PCIe to the XDMA. Upon receiving the data, the XDMA sends it to the MIG via the AXI bus interconnect, AXI_INTERCONNECT. The MIG is the DDR controller, using a standard AXI bus. The AXI bus-based MIG allows users to control DDR read / write operations via a standardized bus interface. Data sent to the MIG in this software can be seamlessly converted back to DDR by the MIG. The user-side FPGA program reads DDR data via the FDMAIP core, also using the AXI_INTERCONNECT and the DDR controller MIG during the reading process. The FDMA is a custom IP core capable of converting and reversing data from the user-defined bus to the AXI bus. The data transmission process is described in the reference section. Figure 3 As shown.

[0111] Through the above process, the FPGA writes data into DDR memory. Note that reading 64MB from the hard drive at a time avoids insufficient memory allocation due to excessive data reads. The host computer can specify the amount of data written to DDR, and a stop flag can be set for the thread. A stop command can be sent via the interface software to stop the DDR writing thread.

[0112] (4) The host computer initiates transmission. The interface software, based on user operations, obtains the enable status, frame length, frame interval, and transmission count for each channel. This information is then sent to the service software via ZMQ. Upon receiving this information, the service software enables the FPGA channel transmission of the fiber optic transmission module, allowing multiple channels using the same DDR data source to transmit simultaneously and multiple times. Data transmission is stopped by disabling the fiber optic transmission module interface.

[0113] After receiving the start command, the FPGA first reads the data from the DDR through FDMA and caches it in a 144-to-72 FIFO. The CPU sends data with a bit width of 128 bits, and the other 16 bits in the 144 bits are the byte valid bits.

[0114] The specific rules for data concatenation at the FIFO input from 144 to 72 are as follows:

[0115] 144-bit data = {15-8 bytes of valid bits, 127-64 bytes of data, 7-0 bytes of valid bits (8 bits), 63-0 bytes of data (2 bits)};

[0116] Byte valid bits keep (16 bits) = {15th byte valid bits, ..., 0th byte valid bits}.

[0117] Byte validity bit: 1 indicates that the byte is valid, and 0 indicates that the byte is invalid.

[0118] After the 144-to-72 FIFO is converted, the valid data is integrated and transmitted to the 64-to-64 FIFO. The interface module determines that there is enough buffered data for one frame before sending it out.

[0119] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A high-speed data transmission method based on DDR, characterized in that, It is applied to a data transmission system comprising an FPGA main control chip, a DDR cache module, an NVME storage module, and an optical fiber transmission module. The method includes the following steps: S1. Data Reception and Preprocessing Steps: The FPGA main control chip receives the data to be transmitted sent by the host computer through the PXIE bus interface, performs format parsing and data packet reassembly on the data to be transmitted, and generates standardized data frames. S2, DDR cache writing step: The FPGA main control chip writes the standardized data frame into the DDR cache module according to the preset address mapping rules, establishes a data cache queue, and records the storage address and data length information of each data frame; S3. Cache data reading steps: The FPGA main control chip reads the data frame to be sent from the DDR cache module according to the data sending request and the first-in-first-out principle, and performs data integrity verification. S4. Data storage steps: The FPGA main control chip writes the verified data frame to the NVME storage module for persistent storage through the PCIE interface, and updates the data storage status table at the same time. S5. Data transmission steps: The FPGA main control chip reads data from the NVME storage module according to the transmission protocol, and sends the data to the optical fiber transmission module through the GTH high-speed serial interface to complete the high-speed data transmission.

2. The high-speed data transmission method based on DDR according to claim 1, characterized in that, Step S1 specifically includes: S11, PXIE bus initialization: The FPGA main control chip configures the link parameters of the PXIEx8 interface, including link speed, data bit width and transmission mode, and establishes a communication link with the host computer. S12. Data packet reception: The FPGA main control chip receives the raw data packet sent by the host computer via DMA and stores the raw data packet in the receiving buffer. S13, Protocol Parsing: Parse the protocol header of the data packets in the receive buffer to extract the packet header information, payload length and checksum of the data packets; S14. Data Frame Reassembly: Based on the protocol parsing results, the payload data is divided or merged according to the preset frame length to generate standardized data frames of fixed length. Each standardized data frame contains a frame header, data field, and frame tail checksum.

3. The high-speed data transmission method based on DDR according to claim 1, characterized in that, The DDR cache module includes a first DDR group and a second DDR group. The first DDR group uses four DDR4 chips connected in parallel to form a 64-bit data width, and the second DDR group uses two DDR4 chips connected in parallel to form a 32-bit data width. Step S2 specifically includes: S21, DDR Initialization Configuration: The FPGA main control chip initializes the first DDR group and the second DDR group respectively, and configures the DDR working clock, refresh cycle and timing parameters; S22, Address Space Allocation: Divide the DDR storage space into multiple logical partitions, assign a starting address and capacity to each partition, and establish an address mapping table; S23. Write Address Calculation: Calculate the target write address based on the current write pointer position and the data frame length. The formula for calculating the target write address is as follows: ； Where Addr_write is the target write address; Base_addr is the partition start base address; W_ptr is the current write pointer value; Frame_size is the byte length of the normalized data frame (bytes); Total_size is the total partition capacity (bytes); mod is the modulo operator; S24. Burst Write Operation: The DDR burst transfer mode is used to write the standardized data frame to the target address. After the write is completed, the write pointer and data frame counter are updated to generate a data frame descriptor containing address and length information.

4. The high-speed data transmission method based on DDR according to claim 3, characterized in that, Step S3 specifically includes: S31. Read Request Judgment: The FPGA main control chip detects the data sending request signal and determines whether the DDR cache queue is not empty. S32. Read Address Calculation: Calculate the target read address based on the read pointer position. The formula for calculating the target read address is as follows: ； Where Addr_read is the target read address; Base_addr is the partition start base address; R_ptr is the current read pointer value; Frame_size is the byte length of the normalized data frame (bytes); Total_size is the total partition capacity (bytes); mod is the modulo operator; S33, Burst Read Operation: Uses DDR burst transfer mode to read a complete data frame from the target address into the read buffer; S34. Data Verification: Perform CRC verification on the read data frame. If the verification passes, update the read pointer and output the data frame. If the verification fails, mark the error and trigger the reread mechanism.

5. The high-speed data transmission method based on DDR according to claim 4, characterized in that, The method for determining whether the DDR cache queue is not empty in step S31 is as follows: The number of cached data frames is calculated using the following formula: ； in, This represents the number of data frames currently cached. To write pointer value; This is the read pointer value; Queue_depth is the depth of the cache queue; mod is the modulo operator; when When the value is greater than 0, the cache queue is determined to be in a non-empty state.

6. The high-speed data transmission method based on DDR according to claim 1, characterized in that, The NVME storage module includes two solid-state drives connected to the FPGA main control chip via a PCIe x4 interface; step S4 specifically includes: S41. Storage path selection: Select the target storage disk based on the current load status and remaining capacity of the two solid-state drives; S42, NVME command generation: Generate an NVME write command based on the length of the data frame to be stored and the target storage address. The NVME write command includes a command opcode, a logical block address, and a data length. S43, DMA data transfer: Transfers data frames from the read buffer to the write buffer of the NVMe storage module via PCIe DMA; S44. Storage Status Update: After the NVME storage module completes the data writing, it returns a completion status. The FPGA main control chip updates the data storage status table and records the storage location and storage timestamp of the data frame.

7. The high-speed data transmission method based on DDR according to claim 1, characterized in that, The optical fiber transmitting module is a 12-channel parallel optical transceiver module; step S5 specifically includes: S51, Sending Task Scheduling: The FPGA main control chip determines the storage location of the data to be sent according to the sending protocol and generates an NVME read command; S52, Data Read: Read the data to be sent from the solid-state drive into the send buffer using the NVME read command; S53. Encoding Processing: Encode the data to be transmitted into 8B / 10B or 64B / 66B encoding to generate an encoded data stream suitable for high-speed serial transmission. S54, GTH serial transmission: The FPGA's GTH high-speed transceiver converts the encoded data stream into a high-speed serial signal, which is then transmitted to the device under test via the fiber optic transmission module, completing the data transmission process.

8. The high-speed data transmission method based on DDR according to claim 3, characterized in that, The first DDR group and the second DDR group use a ping-pong operation mode for data caching. The specific method is as follows: When the first DDR group is in the data writing state, the second DDR group is in the data reading state; After the first DDR group completes the writing of a data block, it switches to the read state, and at the same time the second DDR group switches to the write state; Continuous data processing is achieved through ping-pong operations, thereby improving data throughput.

9. The high-speed data transmission method based on DDR according to claim 5, characterized in that, The method also includes a flow control step: Calculate the cache utilization rate, and the formula for calculating the cache utilization rate is: ； Wherein, Occupancy is the cache utilization rate (%). The current number of cached data frames; Queue_depth is the depth of the cache queue; When the cache occupancy rate exceeds the preset high watermark threshold, a pause request signal is sent to the host computer; when the cache occupancy rate is lower than the preset low watermark threshold, a resume transmission signal is sent to the host computer.

10. The high-speed data transmission method based on DDR according to claim 1, characterized in that, The data transmission system also includes a clock management module, which provides synchronous clock signals to the FPGA main control chip, DDR cache module, NVME storage module and fiber optic transmission module to ensure the timing consistency of data transmission between the modules.

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