Processor soft error fault mode analysis system
The processor soft error failure mode analysis system solves the problems of high cost and long cycle of traditional simulation methods, realizes efficient soft error assessment and reliability analysis, and supports risk assessment and design optimization of space missions.
Patent Information
- Application Number
- CN202610088086.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-22
- Publication Date
- 2026-05-01
AI Technical Summary
Traditional methods for simulating processor soft errors on the ground are costly, time-consuming, and have significant limitations, making it difficult to effectively assess processor reliability in space missions.
Design a processor soft error fault mode analysis system, including fault generation, injection, data acquisition, processing and display modules. Through collaborative work, establish a correlation model of fault mode-system response-task impact, and realize in-situ testing and closed-loop correlation modeling of multi-physics coupling.
It enables rapid and batch evaluation of soft error rates in the early stages of processor design, reduces R&D costs, shortens iteration cycles, provides high-value reliability design basis, and supports system-level vulnerability analysis.
Smart Images
Figure CN121958047A_ABST
Abstract
Description
A processor soft error failure mode analysis system Technical Field
[0001] This invention relates to the field of processor soft error fault analysis technology, specifically to a processor soft error fault mode analysis system. Background Technology
[0002] In space applications, processors are the "brains" of core electronic systems in satellites, space stations, and deep space probes, and their reliability directly determines the success or failure of the mission. Unlike the terrestrial environment, space has complex high-energy radiation fields that can cause soft errors in processors. For example, the logic state of a circuit can be temporarily altered, a phenomenon known as a bit flip or single-event upset. Space missions are characterized by high cost, long cycles, and lack of repairability; therefore, simulating soft errors on the ground is a crucial means of evaluating and optimizing processor soft error performance.
[0003] Before conducting space missions, traditional ground-based simulations directly employ a "radiation source irradiation + hardware testing" approach, such as using heavy-ion accelerators or proton cyclotron accelerators. While these methods can obtain realistic data, they are costly and time-consuming per test. Software simulations (such as Monte Carlo simulations and TCAD device-level simulations) or hardware-in-the-loop simulations (such as FPGA hardware-accelerated simulations) can quickly assess soft error rates under different architectures and processes in the early stages of processor design, significantly reducing R&D costs and shortening iteration cycles. However, the aforementioned "radiation source irradiation + hardware testing" method for processor fault injection is time-consuming and labor-intensive, and traditional software simulation methods also have significant limitations. Summary of the Invention
[0004] The purpose of this invention is to provide a processor soft error fault mode analysis system to solve the problems mentioned in the background art.
[0005] To achieve the above objectives, the present invention provides the following technical solution: a processor soft error fault mode analysis system, comprising: a fault generation module, used to define fault types and injection locations, laying the input foundation for subsequently establishing a correlation model of fault mode-system response-task impact; a fault injection module, used to realize the execution closed loop of the target processor's start-stop-injection, and accurately record the time, location, and mode of each injection, providing a traceable basis for establishing the temporal correlation of fault mode-system response-task impact; a data receiving module, used to continuously collect and capture the output data of the target processor during the fault injection process through an established communication channel; and a data processing module, used to structure the returned data. The system employs data processing and metadata annotation to precisely associate each record with its corresponding fault injection event, providing standardized data input for establishing a multi-dimensional correlation model of fault mode-system response-task impact. The results display module visualizes the distribution and temporal evolution of error types, intuitively revealing the degree of impact and sensitive areas of different fault modes on system tasks. The controlled operation module supports remote operation and status monitoring of the system through a remotely controllable system start / stop and status monitoring mechanism, enabling in-situ testing. The fault generation module, fault injection module, data receiving module, data processing module, results display module, and controlled operation module work together to establish a correlation model of fault mode-system response-task impact.
[0006] Preferably, the fault generation module is responsible for constructing fault modes for the configuration registers and memory of the target processor; the user can select candidate targets including general-purpose registers, peripheral registers and memory regions, and set a flipping method for each type of target, the flipping method including unit flipping, multi-bit flipping and full flipping; the fault generation module provides two types of fault coverage strategies: traversal mode and random mode.
[0007] Preferably, the traversal mode enumerates registers, memory addresses and their corresponding fault mode combinations in a predetermined order to form a systematic full-coverage injection sequence; the random mode samples registers or memory units and their flipping methods in the same fault space based on a pseudo-random algorithm to generate an unpredictable but reproducible error injection sequence.
[0008] Preferably, the fault injection module forms a controlled execution closed loop around the start-stop-injection logic of the target processor: when the user starts the fault injection module on the host, it first checks the current communication and debugging environment, and enters the injection-ready running state according to the configured fault generation mode. At this time, the target processor executes according to normal business logic.
[0009] Preferably, when the preset triggering conditions are met, the fault injection module first switches the processor from normal operation to suspended state through the debugging interface, freezing the current register and memory states; then, it applies the corresponding fault mode to the selected register or memory unit, and after the injection is completed, it sends a continue running or restart instruction to the target processor, so that it can resume execution in the context of the fault state.
[0010] Preferably, it also includes a data communication module, which is used to configure and establish serial, TCP, UDP and USB communication channels for the target processor and its peripheral devices. The data receiving module runs on these established channels for a long time, continuously receiving various feedback data from the target processor during normal operation and fault injection, and automatically archives and stores it.
[0011] Preferably, after the host of the data processing module receives the data from the target processor, the data processing module performs data parsing and integrity checks on the content returned by each communication channel according to a preset communication protocol, decomposes the original byte stream into valid messages, and adds a timestamp, channel type, physical port or IP information and session identifier metadata to each message to form a structured record; these structured records are also pushed to the result display module in real time for statistics, visualization and comparison display.
[0012] Preferably, the result display module includes a real-time error trend chart, a data line chart, and a pie chart, used to display the changes in the number of errors and the frequency of abnormal events over time, and to display the correlation between the fault mode and the system output based on the classification results and data type distribution information obtained from the data analysis module.
[0013] Preferably, the controlled operation module implements a TCP or UDP server on the host side, providing remote start, stop, and status monitoring functions; the controlled operation module is configured with a heartbeat monitoring mechanism to periodically check the connection status and provide alarms when abnormalities occur.
[0014] The system's workflow is as follows: the fault generation module generates a fault sequence to be executed based on the user-configured target and flipping method, using either a traversal or random mode strategy; the fault injection module drives the target processor into an injection state and executes a "run-pause-inject-restart" loop according to the fault sequence; the data receiving module continuously collects logs, error codes, and status words returned by the target processor during normal operation and injection, and automatically archives them by session and channel; the data processing module parses and verifies the raw byte stream according to the protocol, decomposing it into structured records with timestamps, channel types, ports or IPs, and session identifiers; the result display module converts the processing results of the data processing module into visual charts for display; and the controlled operation module provides a remote control and monitoring entry point for the entire process.
[0015] Compared with the prior art, the present invention adopts the above technical solution and has the following technical effects: 1. It supports the in-situ testing capability of multi-physics field coupling and simulates the effects of real and complex space environment.
[0016] Through remote start / stop and status monitoring via the controlled operation module, this system can be linked with ground simulation equipment for thermal, vacuum, vibration, and magnetic environments to perform radiation soft error injection tests while applying mechanical and thermal environmental stresses. This in-situ testing capability with multi-physics coupling can more realistically simulate the synergistic effects of processor failures in a comprehensive space environment, and has irreplaceable value in revealing potential system-level vulnerabilities and interactive failure modes.
[0017] 2. Achieve application-oriented closed-loop correlation modeling, surpassing traditional single-point fault injection.
[0018] This system, through the collaborative efforts of fault generation, injection, data acquisition, and processing modules, not only records "where the flip occurred," but more importantly, captures "the system's dynamic response after the flip" and "the final task execution result." This end-to-end closed-loop correlation model of "fault mode-system response-task impact" directly links physical-level bit flips with system-level functional failures and task risks, providing valuable quantitative evidence for the reliability design and fault-tolerance strategy optimization of space processors.
[0019] 3. Provides highly configurable and reproducible fault stimuli to support systematic testing and in-depth analysis.
[0020] The fault generation module supports precise target selection of registers and memory units, and provides two injection strategies: traversal (systematic coverage) and random (stress testing). Combined with the fault injection module's precise freezing and on-site modification of the processor's execution state, it ensures complete traceability and reproducibility of each injection event in terms of time, location, and mode. This creates strictly controllable experimental conditions for locating sensitive units, analyzing error propagation paths, and verifying the effectiveness of fault tolerance mechanisms, greatly enhancing the depth of testing and the scientific rigor of analysis.
[0021] 4. Build a fully digital, high-efficiency analysis pipeline to significantly improve evaluation efficiency and iteration speed.
[0022] Compared to the time-consuming and costly direct irradiation testing, this system forms a fully digital automated analysis pipeline through software-defined faults, hardware-in-the-loop injection, automatic data acquisition and structured processing, and result visualization. It can quickly and in batches perform fault injection and sensitivity analysis in the early stages of processor design or the entire satellite design stage, without waiting for process tape-out or occupying scarce accelerator time, thereby significantly reducing R&D costs and shortening the cycle of reliability verification and design iteration. Attached Figure Description
[0023] Figure 1 is a design architecture diagram of the soft error failure mode analysis system of this application; Figure 2 is a sequence diagram of the execution of this application. Detailed Implementation
[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Embodiments
[0025] As shown in Figure 1, a processor soft error fault mode analysis system includes a fault generation module, a fault injection module, a data receiving module, a data processing module, a result display module, and a controlled operation module.
[0026] The fault generation module defines fault types and injection locations, laying the input foundation for establishing a correlation model of fault mode, system response, and task impact. The fault injection module implements a closed-loop execution of the target processor's start-stop-injection process and accurately records the time, location, and mode of each injection, providing traceable evidence for establishing a temporal correlation of fault mode, system response, and task impact. The data receiving module continuously collects and captures the target processor's output data during the fault injection process through the established communication channel. The data processing module performs structured processing and metadata annotation on the returned data, accurately associating each record with the corresponding fault injection event, thus establishing a multidimensional correlation of fault mode, system response, and task impact. The model provides standardized data input; the results display module visualizes the distribution and temporal evolution of error types, intuitively revealing the impact of different failure modes on system tasks and sensitive areas; the controlled operation module supports in-situ testing of the entire satellite, subsystems, and modules through a remotely controllable system start-up, shutdown, and status monitoring mechanism, enabling the simultaneous coupling of soft errors caused by radiation effects during thermal, vibration, and magnetic experiments; the fault generation module, fault injection module, data receiving module, data processing module, results display module, and controlled operation module work together to establish a correlation model of failure mode-system response-task impact, and can achieve in-situ testing, achieving experimental effects of multi-physics coupling, providing data support for risk assessment of space missions.
[0027] The fault generation module is responsible for constructing fault modes for the target processor's configuration registers and memory. Users can select candidate targets including general-purpose registers, peripheral registers, and memory regions, and set a flipping method for each type of target. The flipping method includes unit flipping, multi-bit flipping, and full flipping. The fault generation module provides two types of fault coverage strategies: one is the traversal mode, which enumerates registers, memory addresses, and their corresponding fault mode combinations in a predetermined order to form a systematic full-coverage injection sequence; the other is the random mode, which samples registers or memory units and their flipping methods in the same fault space based on a pseudo-random algorithm to generate an unpredictable but reproducible error injection sequence.
[0028] The fault injection module forms a controlled execution closed loop around the start-stop-injection logic of the target processor: when the user starts the fault injection module on the host, the fault injection module first checks the current communication and debugging environment, and enters the waiting-to-inject running state according to the configured fault generation mode. At this time, the target processor executes according to normal business logic.
[0029] When the preset trigger conditions are met, the fault injection module first switches the processor from normal operation to suspended state through the debug interface, freezing the current register and memory states. Then, it applies the corresponding fault mode to the selected register or memory unit, completes the injection, and then issues a continue running or restart instruction to the target processor, so that it can resume execution in the context of the fault state.
[0030] The data communication module is responsible for configuring and establishing serial, TCP, UDP, and USB communication channels for the target processor and its peripheral devices. The data receiving module runs continuously on these established channels, receiving various feedback data from the target processor during normal operation and fault injection. When the user selects a channel and starts monitoring on the data communication page, the system creates a corresponding receiving thread or event loop for that channel, continuously reading data from the serial port buffer, network socket, or USB endpoint. The data is then automatically archived to a unified directory according to the storage settings of the current session. This provides a complete and traceable raw data foundation for subsequent statistical analysis of the differences in communication behavior before and after fault injection on the target processor, plotting real-time / offline error line graphs, and comparing specific fault injection events with corresponding communication anomalies on the data analysis page.
[0031] After the host of the data processing module receives the data from the target processor, the data processing module performs data parsing and integrity checks on the content returned from each communication channel according to the preset communication protocol, breaks down the original byte stream into valid messages, and adds timestamps, channel types, physical port or IP information and session identifier metadata to each message to form structured records; these structured records are also pushed to the results display module in real time for statistics, visualization and comparison display.
[0032] The results display module includes real-time error trend charts, data line charts, and pie charts. On the one hand, it displays the changes in the number of errors and the frequency of abnormal events over time; on the other hand, based on the classification results and data type distribution information obtained from the data analysis module, it displays the correlation between fault modes and system output.
[0033] The core function of the controlled operation module is to implement a TCP or UDP server on the host, enabling users to remotely start, stop, and monitor the status of the system. This module is used to set the protocol type, listening port, and heartbeat message interval for controlled operation. The heartbeat message is used to periodically check if the server is online, and continuously outputs the most recent heartbeat time and the current operating status on the terminal. When a user starts the controlled operation service, the module opens the corresponding TCP or UDP listening port and starts the heartbeat monitoring logic. If no heartbeat is received for an extended period or a connection error occurs, the module will issue an alarm in the terminal, indicating that the remote control terminal has lost connection or there is a network anomaly. When a user stops the controlled operation service, the module closes the listening port, stops heartbeat detection, disconnects all remote connections, and records the service stoppage and possible error reasons in the terminal output, while also recording the start or stoppage activity log. Overall, this controlled operation module provides a configurable remote control entry point with heartbeat monitoring capabilities for the target processor fault injection system, allowing external control terminals to drive or monitor system operation in a controlled, secure, and reliable manner through TCP or UDP interfaces.
[0034] As shown in Figure 2, the system operates in the following stages.
[0035] Phase 1: System Initialization and Host-side Startup and Configuration: The operator starts the system on the host, and the controlled execution module receives the start command. The fault generation module reads the user-defined fault injection configuration, such as target register, memory address, and flip mode, and generates a fault sequence to be executed accordingly.
[0036] Establishing Communication and Connection: The fault injection module is responsible for establishing a physical connection with the target processor, such as through debugging interfaces like JTAG or SWD. The data receiving module simultaneously establishes a communication channel with the target processor, such as a serial port, to prepare for receiving its runtime data. Once both connection and communication are successfully established, the system enters a ready state.
[0037] Phase Two: Main Loop Injection and Monitoring Triggering and Pausing: The system enters the main loop. The fault injection module awaits preset trigger conditions, such as a specific time, event, or instruction. Once triggered, it immediately pauses the target processor from normal operation through the debug interface, freezing its current registers, memory, and all other states.
[0038] Status Reading and Fault Injection: The module reads and records the current state of the processor. Then, based on a pre-generated fault sequence, it performs a fault injection operation, such as bit flipping, at a specified location (register or memory unit).
[0039] Recovery and Data Acquisition: After injection, the fault injection module issues commands to restore the target processor to operation in the tampered context. Simultaneously, the data receiving module begins continuously receiving operation logs, status data, and other data transmitted back by the target processor via serial ports and other channels.
[0040] Data Processing and Real-Time Analysis: The data processing module parses the received serial port data, converts it into structured records according to the protocol, and adds metadata such as timestamps and session IDs. Next, the module compares the injected system output with the normal baseline or expected results to identify anomalies.
[0041] Results visualization update: The results display module updates charts in real time based on the analysis results, such as error line charts and status distribution charts, dynamically presenting indicators such as fault impact and system response to users.
[0042] Loop or Termination: After completing one injection-analysis cycle, the process returns to the starting point of the main loop, waiting for the next trigger to prepare for the next fault injection in the sequence. When all fault sequences have been executed, or when the user issues a stop command through the controlled operation module, the fault injection module will stop the injection process.
[0043] Those skilled in the art will understand that the features described in the various embodiments and / or claims of the present invention can be combined or combined in various ways, even if such combinations or combinations are not explicitly described in the present invention. In particular, the features described in the various embodiments and / or claims of the present invention can be combined or combined in various ways without departing from the spirit and teachings of the present invention. All such combinations and / or combinations fall within the scope of the present invention.
Claims
1. A processor soft error fault mode analysis system, characterized in that, include: The fault generation module is used to define fault types and injection locations, laying the input foundation for the subsequent establishment of a correlation model of fault mode-system response-task impact; The fault injection module is used to realize the execution closed loop of target processor start-stop-injection, and accurately record the time, location and mode of each injection, providing a traceable basis for establishing the time sequence correlation of fault mode-system response-task impact; The data receiving module is used to continuously collect and capture the output data of the target processor during the fault injection process through the established communication channel; The data processing module is used to perform structured processing and metadata annotation on the returned data, so that each record is accurately associated with the corresponding fault injection event, providing standardized data input for establishing a multi-dimensional correlation model of fault mode-system response-task impact; The results display module is used to visualize the distribution and temporal evolution of error types, intuitively revealing the impact of different failure modes on system tasks and sensitive areas; Controlled operation module: Through a remotely controllable system start-up and shutdown and status monitoring mechanism, it supports remote operation and status monitoring of the system and realizes in-situ testing; the fault generation module, fault injection module, data receiving module, data processing module, result display module and controlled operation module work together to establish a correlation model of fault mode-system response-task impact.
2. The processor soft error fault mode analysis system according to claim 1, characterized in that, The fault generation module is responsible for constructing fault modes for the configuration registers and memory of the target processor. Users can select candidate targets including general-purpose registers, peripheral registers and memory regions, and set a flipping method for each type of target. The flipping method includes unit flipping, multi-bit flipping and full flipping. The fault generation module provides two types of fault coverage strategies: traversal mode and random mode.
3. The processor soft error fault mode analysis system according to claim 2, characterized in that, The traversal mode: enumerates registers, memory addresses and their corresponding fault mode combinations in a predetermined order to form a systematic full-coverage injection sequence; the random mode: based on a pseudo-random algorithm, samples registers or memory units and their flipping methods in the same fault space to generate an unpredictable but reproducible error injection sequence.
4. The processor soft error fault mode analysis system according to claim 1, characterized in that, The fault injection module forms a controlled execution loop around the startup-stop-injection logic of the target processor: when the user starts the fault injection module on the host, it first checks the current communication and debugging environment, and enters the waiting-to-inject running state according to the configured fault generation mode. At this time, the target processor executes according to normal business logic.
5. The processor soft error fault mode analysis system according to claim 4, characterized in that, When the preset triggering conditions are met, the fault injection module first switches the processor from normal operation to suspended state through the debugging interface, freezing the current register and memory states; then, it applies the corresponding fault mode to the selected register or memory unit, and after the injection is completed, it sends a continue running or restart instruction to the target processor, so that it can resume execution in the context of the fault state.
6. The processor soft error fault mode analysis system according to claim 1, characterized in that, It also includes a data communication module, which is used to configure and establish serial, TCP, UDP and USB communication channels for the target processor and its peripheral devices. The data receiving module runs on these established channels for a long time, continuously receiving various feedback data from the target processor during normal operation and fault injection, and automatically archives and stores it.
7. The processor soft error fault mode analysis system according to claim 1, characterized in that, After the host of the data processing module receives the data from the target processor, the data processing module performs data parsing and integrity checks on the content returned by each communication channel according to the preset communication protocol, disassembles the original byte stream into valid messages, and adds timestamps, channel types, physical port or IP information and session identifier metadata to each message to form a structured record. These structured records are also pushed to the results display module in real time for statistical analysis, visualization, and comparison.
8. The processor soft error fault mode analysis system according to claim 1, characterized in that, The results display module includes real-time error trend charts, line charts, and pie charts, which are used to display the changes in the number of errors and the frequency of abnormal events over time, as well as to display the correlation between fault modes and system outputs based on the classification results and data type distribution information obtained from the data analysis module.
9. The processor soft error fault mode analysis system according to claim 6, characterized in that, The controlled operation module implements a TCP or UDP server on the host side, providing remote start, stop, and status monitoring functions; the controlled operation module is configured with a heartbeat monitoring mechanism to periodically check the connection status and provide alarms when abnormalities occur.
10. The processor soft error fault mode analysis system according to claim 1, characterized in that, The system's workflow is as follows: the fault generation module generates a fault sequence to be executed according to the user-configured target and flipping method, using either a traversal or random mode strategy; the fault injection module drives the target processor into an injection state and executes a "run-pause-inject-restart" loop according to the fault sequence; the data receiving module continuously collects logs, error codes, and status words returned by the target processor during normal operation and injection, and automatically archives them by session and channel; the data processing module parses and verifies the raw byte stream according to the protocol, decomposing it into structured records with timestamps, channel types, ports or IPs, and session identifiers. The results display module transforms the processing results of the data processing module into visual charts for display; the controlled operation module provides a remote control and monitoring entry point for the entire process.