Multi-path 2711 digital logic simulation architecture system based on Verilog HDL

Abstract

The invention discloses a multi-path 2711 digital logic simulation architecture system based on Verilog HDL (High Definition Language). The multi-path 2711 digital logic simulation architecture system comprises a demand module, a test case TESTCASE module and a 2711 model 2711 MOD module, according to the invention, the multi-path 2711 digital logic simulation architecture based on Verilog HDL is established, the problems that the application scene of the existing 2711 simulation architecture is single and needs to be continuously modified to be suitable for various application scenes of each project are solved, the multi-path 2711 digital logic simulation architecture is suitable for various application scenes of each project through parameter transmission and analysis, and the simulation verification efficiency of each project about various application scenes of 2711 is improved. According to the multi-path 2711 digital logic simulation architecture based on VerilogHDL, adaptive modification of requirements can be completed on a TESTCASE layer of a test case according to the requirements, and a lower-layer 2711 model 2711MOD does not need to be modified, so that the applicability of the lower-layer 2711 model 2711MOD is higher, and the application is more flexible.

Description

Technical Field

[0001] This invention relates to the field of simulation and testing technology, specifically to a multi-channel 2711 digital logic simulation architecture system based on VerilogHDL. Background Technology

[0002] Simulation verification is a necessary step in digital logic design testing and one of the effective means to ensure the quality of digital logic designs. The quality of the input data used for testing directly affects the test results. Test evaluation needs to comprehensively cover many application scenarios such as functionality, performance, and interface protocols, which requires the input data to have personalized characteristics. For example, when testing functionality, it is necessary to cover all data types in the interface protocol to confirm that all input 2711 data can be correctly received and parsed; when testing the interface protocol, it is necessary to specify bits and fields that violate the protocol to confirm that abnormal input data can be correctly processed and will not affect the reception and parsing of subsequent 2711 data.

[0003] The ease or difficulty of generating test input data directly impacts testing efficiency. Ignoring simulation time, the testing timeline is primarily divided into three stages: pre-test design understanding, in-test environment setup, and post-test data recording and organization. The most intuitive way to evaluate the user-friendliness of a simulation architecture is based on the ease or difficulty of generating test input data. Simulation architectures that can generate test input data with simple settings are more user-friendly, saving significant environment setup time. Simulation architectures that can generate input data for normal functional testing, abnormal input data for interface protocols, and variable data rates have a wider range of applications, saving not only testing time for a single project but also for a class of projects. With increasingly compressed testing timelines and in the foreseeable future, the need for such simulation architectures is even more urgent.

[0004] The existing 2711 simulation architecture suffers from a single application scenario, requiring continuous modification to adapt to various application scenarios in different projects. This severely impacts the efficiency of simulation verification and fails to meet diverse testing needs. Therefore, there is an urgent need for a multi-channel 2711 digital logic simulation architecture that can adapt to multiple projects and application scenarios, requires no frequent modifications, and improves the efficiency of simulation verification. Summary of the Invention

[0005] The purpose of this invention is to provide a multi-channel 2711 digital logic simulation architecture system based on VerilogHDL to solve the problems existing in the prior art.

[0006] To achieve the above objectives, the present invention provides the following technical solution: a multi-channel 2711 digital logic simulation architecture system based on VerilogHDL, including a requirements module, a test case module, and a 2711 model module 2711_MOD; The requirements module is used to provide data protocols, frame formats, 2711 data rates, and case requirements. The test case module is used to set the 2711 data and parameters according to the information provided by the requirement module, and then pass the set 2711 data and parameters to the 2711 model 2711_MOD module. The 2711_MOD module of the 2711 model is used to parse the information transmitted by the TESTCASE module, determine the 2711 data words to be sent and send them at the set rate, and also supports the generation and expansion of multiple independent data streams.

[0007] Preferably, the test case module includes a data setting unit and a parameter setting unit. The 2711 data setting unit is used to set the 2711 idle code IDLE, length LEN, and frame data WORD0~1023. The idle code IDLE is 16 bits, the length LEN is 32 bits, the high 16 bits are the number of test data frames, the low 16 bits are the number of words per frame, one word corresponds to two bytes, and the frame data array capacity is 1024 32-bit arrays. Of the 32 bits of the frame data, the high 12 bits are the data word sequence number, bits [19:18] are the frame format status identifier, and bits [17:16] are used to set the valid range of the 16 bits of data; The parameter setting unit is used to set words, and the word setting content includes frame check setting and frame sequence number setting.

[0008] Preferably, in the frame format status identifier, "01" indicates a data error, "11" indicates invalid data, and other values ​​indicate correct data; the data error includes data protocol error and input data frame format error. The data protocol error involves RKMSB, RKLSB, data start bit, data stop bit, and data free code, while the input data frame format error involves frame synchronization header, master header, and data area containing the words frame synchronization header.

[0009] Preferably, when the bits [17:16] are "11", all 16 bits in the lower 16 bits of data are K code; when they are "01", the higher 8 bits in the lower 16 bits of data are valid data and the lower 8 bits are K code; when they are "10", the higher 8 bits in the lower 16 bits of data are K code and the lower 8 bits are valid data; when they are "00", all 16 bits in the lower 16 bits of data are valid data.

[0010] Preferably, the frame verification settings include frame verification type, frame verification start and end word sequence number, and frame verification field start and end word sequence number; the frame sequence number settings include frame sequence number field start and end word sequence number, frame sequence number field start and end byte high and low bytes, counting step size, and counting start point.

[0011] Preferably, the 2711 model 2711_MOD module includes four sub-modules, each of which contains a word setting unit and a word sending unit; The word setting unit is used to implement frame sequence number setting and frame check setting; The transmitting word unit is used to determine the symbol rate of the transmitting word, parse relevant information and determine the specific content of the transmitting word data, and generate the transmitting data word for simulation testing.

[0012] Preferably, the frame sequence number setting is achieved by parsing the 32-bit frame sequence number setting parameter TNUM. In the 32-bit frame sequence number setting, the high 12 bits are the start word sequence number of the frame sequence number field, bits [19:18] are the high and low bytes of the start word of the frame sequence number field, bits [17:6] are the end word sequence number of the frame sequence number field, bits [5:4] are the high and low bytes of the end word of the frame sequence number field, bits [3:2] are the counting step size, and bits [1:0] are the counting start point.

[0013] Preferably, the frame verification setting is implemented by parsing three 32-bit frame verification setting parameters TCHK0 to TCHK2. TCHK0 is used to set the frame verification type, TCHK1 is used to set the frame verification start and end word sequence number, and TCHK2 is used to set the frame verification field start and end word sequence number.

[0014] Preferably, the transmitting word unit parses the 2711 idle code IDLE, length setting LEN, and frame data WORD0~1023, and determines the transmitting word data by combining the frame check value and the frame sequence number field content; when the frame data bits [19:18] are "11", it uses its own generated random data.

[0015] Preferably, the 2711_MOD module can generate four independent 2711 data streams simultaneously, or it can obtain n×4 independent 2711 data streams through multiple instantiation calls, where n is the number of instantiation calls.

[0016] Compared with the prior art, the beneficial effects of the present invention are: This invention establishes a multi-channel 2711 digital logic simulation architecture based on VerilogHDL, which solves the problem that the existing 2711 simulation architecture has a single application scenario and needs to be constantly modified to adapt to various application scenarios of various projects. Through parameter transmission and parsing, it can be adapted to multiple application scenarios of various projects, thereby improving the simulation verification efficiency of various application scenarios of 2711 in various projects.

[0017] The VerilogHDL-based multi-channel 2711 digital logic simulation architecture can adapt to requirements at the test case level without modifying the underlying 2711 model 2711_MOD, making the underlying 2711 model 2711_MOD more applicable and more flexible in application.

[0018] This invention only completes the adaptive modification of requirements at the test case level. Without considering simulation resources, all test requirements related to 2711 can be concentrated into one test case, making the test case more efficient.

[0019] This invention can provide up to 4 independent 2711 data streams for simulation testing, or obtain n×4 independent 2711 data streams through multiple (e.g., n) instantiation calls. Attached Figure Description

[0020] Figure 1 This is a simulation architecture diagram of the present invention; Figure 2 This is the 2711 protocol diagram of the present invention. Detailed Implementation

[0021] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0022] Please see Figure 1-2 This invention provides a multi-channel 2711 digital logic simulation architecture system based on VerilogHDL, including a requirements module, a test case module, and a 2711 model module 2711_MOD. The requirements module is used to provide the basic data and requirements information needed for 2711 digital logic simulation, including data protocol, frame format, 2711 data rate and case requirements; The TESTCASE module is used to set the 2711 data and parameters according to the information provided by the requirements module, and then pass the set 2711 data and parameters to the 2711 model 2711_MOD module. The 2711_MOD module is used to parse the information passed by the TESTCASE module, determine the 2711 data words to be sent and send them at the set rate, and also supports the generation and expansion of multiple independent data streams.

[0023] The TESTCASE module includes 2711 data setting units and parameter setting units: The 2711 data setting unit sets the 2711 idle code IDLE, length LEN, and frame data WORD0-1023 content according to the case requirements, data protocol, and frame format requirements. The idle code IDLE is set to 16 bits, and its content is the idle code specified in the protocol. The length LEN is set to a width of 32 bits, with the high 16 bits representing the number of test data frames to be sent and the low 16 bits representing the number of words in each frame (1 word corresponds to 2 bytes). The frame data array capacity is 1024 32-bit arrays, allowing a maximum of 1024 words (2048 bytes) of 2711 data to be set in one frame. In the 32 bits of the frame data, the high 12 bits are the data word sequence number, used to identify the position of the data word in the entire frame data; the sequence number of the first data word is 0x000. Bits [19:18] are the frame format status identifiers, used to set the frame status; "01" indicates a data error, including data protocol errors and input errors. According to the frame format error, the data protocol error specifically involves RKMSB, RKLSB, data start bit, data stop bit, and data free code. The input data frame format error specifically involves frame synchronization header, master header, and data area containing the words frame synchronization header. "11" indicates invalid data. This type of data is not passed to the 2711_MOD module of the 2711 model. Other values ​​indicate that the data is correct. Bit

[17] is RKMSB and bit

[16] is RKLSB, which are used to set the valid range of 16 bits of data. When bits [17:16] are "11", all 16 bits in the lower 16 bits of data are K code. When they are "01", the higher 8 bits in the lower 16 bits of data are valid data and the lower 8 bits are K code. When they are "10", the higher 8 bits in the lower 16 bits of data are K code and the lower 8 bits are valid data. When they are "00", all 16 bits in the lower 16 bits of data are valid data.

[0024] Table 1 2711 Data Settings The parameter setting unit only includes word settings. The word settings include frame check settings and frame sequence number settings. The frame check settings specifically include frame check type, frame check start and end word sequence number, and frame check field start and end word sequence number. The frame sequence number settings specifically include frame sequence number field start and end word sequence number, frame sequence number field start and end byte high and low bytes, count step size, and count start point. The test case module sets the word transmission rate according to the rate requirements and calls the 2711 model 2711_MOD module to pass the set 2711 data and parameters to the 2711 model 2711_MOD module.

[0025] The 2711_MOD module of the 2711 model includes four sub-modules. Each sub-module contains a word setting unit and a word sending unit. As a whole, it is used to parse the 2711 data, word setting parameters and data rate requirements passed from the test case module. Through word setting, it determines the 2711 data words to be sent that meet the test case requirements, including the location and content of error words that do not meet the data protocol or frame format, and sends the 2711 data words that meet the requirements at the set rate. The word setting unit is used to set the frame sequence number and frame checksum. Frame Sequence Number Setting: Parse the 32-bit frame sequence number setting parameter TNUM passed from the TESTCASE module to determine the start and end word sequence numbers, start and end byte high and low bytes, counting step size, and counting start point of the frame sequence number field. In the 32-bit frame sequence number setting, the high 12 bits, i.e., bits [31:20], are the start word sequence number of the frame sequence number field; bits [19:18] are the high and low bytes of the start word of the frame sequence number field, where "11" represents the high byte and the others represent the low byte; bits [17:6] are the end word sequence number of the frame sequence number field. The frame sequence number field is defined by the following bits: bits [5:4] represent the high and low bytes of the end word, where "11" indicates the high byte and the others indicate the low byte; bits [3:2] represent the counting step size, where "3" indicates incrementing by 3, "2" indicates incrementing by 2, "1" indicates incrementing by 1, and "0" indicates incrementing by 0; bits [1:0] represent the counting start point, where "3" indicates starting from 3, "2" indicates starting from 2, "1" indicates starting from 1, and "0" indicates starting from 0; the frame sequence number is calculated based on the parsed frame sequence number counting information, and the calculated frame sequence number value is filled into the frame sequence number field. Frame Check Configuration: Parse the three 32-bit frame check configuration parameters TCHK0~2 passed from the TESTCASE module to determine the frame check type, frame check start and end word sequence numbers, and frame check field start and end word sequence numbers. The first 32-bit TCHK0 is used to set the frame check type; when it is "1", the frame check method is set to CRC check, and the polynomial of this CRC check is x. 16 +x 12 +x 5 +1 indicates no frame check; other values ​​indicate no frame check. The high 16 bits of the second 32-bit TCHK1, i.e., bits [31:16], are used to set the start word number of the frame check, and the 16th bit, i.e., bits [15:0], is used to set the end word number of the frame check. Both are 0, indicating no frame check. The high 16 bits of the third 32-bit TCHK2, i.e., bits [31:16], are used to set the start word number of the frame check field, and the 16th bit, i.e., bits [15:0], is used to set the end word number of the frame check field. Both are 0, indicating no frame check field. Calculate the frame check value based on the parsed frame check information and fill the calculated frame check value into the check field.

[0026] The transmit word unit is used to determine the symbol rate of the transmit word according to the rate requirement, with one word corresponding to one symbol; it parses the 2711 idle code IDLE, length setting LEN, and frame data WORD0~1023 content passed from the test case TESTCASE module, and combines the frame check field frame check value and frame sequence number field content obtained from the word setting unit to determine the specific content of the word data to be transmitted; when the frame data bits [19:18] passed from the test case TESTCASE module are "11", the 2711 model 2711_MOD module does not receive the frame data, but uses its own generated random data; it generates transmit data words with a frame number of LEN[31:16] and a word number of LEN[15:0] per frame according to the length LEN setting parameter, for simulation testing.

[0027] The 2711_MOD module can simultaneously generate four independent 2711 data streams for simulation testing. Alternatively, it can obtain n×4 independent 2711 data streams by repeatedly calling the instantiation method, where n is the number of instantiation calls.

[0028] Table 2 Word Settings 1 Table 3 Word Settings 2 Example: Implementation process of the TESTCASE module: After the test case module starts, it first receives the basic information required for 2711 digital logic simulation from the requirements module, including data protocol, frame format, 2711 data rate and case requirements.

[0029] During the 2711 data setup phase, based on the case requirements, data protocol, and frame format requirements, the 2711 idle code IDLE, length LEN, and frame data WORD0-1023 are set. For example, if the protocol specifies the idle code as 0x5678, then the idle code IDLE is set to this value for padding between each frame of data; if 15 frames of test data need to be sent, each frame including the start and end of the frame, totaling 514 words (1028 bytes), then the length LEN is set to 32'h000F0202, where the high 16 bits 0x000F correspond to 15 frames, and the low 16 bits 0x0202 correspond to 514 words. For frame data WORD0~1023, set the high 12 bits of the sequence number according to the position of each data word in the whole frame data, and set the frame format status identifier of bits [19:18] according to the case requirements. If it is necessary to simulate the RKMSB error in the data protocol error, set the corresponding data word bits [19:18] to "01", set bits [17:16] to the corresponding error configuration, and fill the corresponding error data content in the low 16 bits. If a data word is invalid data, set bits [19:18] to "11", and the data word will not be passed to the 2711 model 2711_MOD module.

[0030] During the parameter setting phase, word settings are completed according to the case requirements and frame format, including frame check settings and frame sequence number settings. In the frame check settings, the TCHK0 parameter specifies whether CRC check is enabled; if enabled, TCHK0 is set to "1". The TCHK1 parameter sets the start and end word sequence numbers for the frame check, and the TCHK2 parameter sets the start and end word sequence numbers for the frame check field. In the frame sequence number settings, the TNUM parameter specifies the start and end word sequence numbers, start and end byte high and low bytes, counting step size, and counting start point for the frame sequence number field. Simultaneously, the word transmission rate is set according to the 2711 data rate provided by the requirements module. After all settings are completed, the TESTCASE module calls the 2711_MOD module, passing the configured 2711 data and parameters to that module.

[0031] Implementation process of the 2711 model and 2711_MOD module: After receiving the information from the TESTCASE module, the 2711_MOD module of the 2711 model starts working simultaneously, and each sub-module parses and sends data according to the same logic.

[0032] During the word setting phase, the word setting unit of each submodule parses the received parameters. For the frame sequence number setting parameter TNUM, it parses the various fields corresponding to its 32 bits to determine the start word number, start word high and low bytes, end word number, end word high and low bytes, counting step size, and counting start point of the frame sequence number field. Based on this information, it calculates the frame sequence number of each frame of data and fills it into the corresponding frame sequence number field. For example, if TNUM is 32'h004C0179, then the parsed frame sequence number field starts from the high byte of the 4th word and ends at the high byte of the 5th word, with a counting step size of 2 and a counting start point of 1. Therefore, the content of the frame sequence number field of the 1st frame is 0x000001, and the frame sequence numbers of subsequent frames increase by the step size. For the frame check setting parameters TCHK0~2, TCHK0 is parsed to determine whether CRC check is enabled. If enabled, TCHK1 is parsed to obtain the start and end word sequence numbers of the frame check, and TCHK2 is parsed to obtain the start and end word sequence numbers of the frame check field. The CRC check value of the corresponding area is calculated based on the start and end word sequence numbers of the frame check and then filled into the check field.

[0033] During the word transmission phase, each submodule's word transmission unit determines the symbol rate of the transmitted word, i.e., the transmission frequency of each word, based on the received 2711 data rate. Subsequently, it parses the received 2711 idle code IDLE, length setting LEN, and frame data WORD0-1023, combining this with the frame checksum value and frame sequence number field obtained during the word setting phase to determine the specific content of each word data to be transmitted. If bits [19:18] of a frame data are "11", the submodule does not use that frame data but instead generates random data as the transmission data; otherwise, it determines the transmission data according to the frame data settings. Based on the length LEN setting, it generates transmission data words corresponding to the number of frames and the number of words per frame, and transmits these data words according to the set symbol rate.

[0034] If the simulation test requires more than 4 independent 2711 data channels, it can be achieved by repeatedly calling the instantiated 2711_MOD module. Each call adds 4 independent data channels, and n calls will obtain n×4 independent 2711 data channels, which can meet the simulation test needs of different scales.

[0035] The collaborative working process of the overall system: The requirements module first clarifies the fundamental requirements for 2711 digital logic simulation, providing data support for the entire system. The test case module completes targeted settings based on these requirements, without modifying the underlying logic of the 2711_MOD module; requirement adaptation is achieved solely through parameter passing. After receiving the parameters, the 2711_MOD module automatically parses and generates compliant 2711 data words, sending them at the set rate. Throughout this process, all modules work collaboratively to ensure smooth simulation testing, while also supporting multi-channel data expansion to adapt to various application scenarios in different projects.

[0036] Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A multi-channel 2711 digital logic simulation architecture system based on Verilog HDL, characterized in that: This includes the requirements module, the test case module, and the 2711_MOD module; The requirements module is used to provide data protocols, frame formats, 2711 data rates, and case requirements. The test case module is used to set the 2711 data and parameters according to the information provided by the requirement module, and then pass the set 2711 data and parameters to the 2711 model 2711_MOD module. The 2711_MOD module of the 2711 model is used to parse the information transmitted by the TESTCASE module, determine the 2711 data words to be sent and send them at the set rate, and also supports the generation and expansion of multiple independent data streams.

2. The Verilog HDL-based multi-channel 2711 digital logic simulation architecture system according to claim 1, characterized in that: The test case module includes a data setting unit and a parameter setting unit. The 2711 data setting unit is used to set the 2711 idle code IDLE, length LEN, and frame data WORD0~1023. The idle code IDLE is 16 bits, the length LEN is 32 bits, the high 16 bits are the number of test data frames, the low 16 bits are the number of words per frame, one word corresponds to two bytes, and the frame data array capacity is 1024 32-bit arrays. Of the 32 bits of the frame data, the high 12 bits are the data word sequence number, bits [19:18] are the frame format status identifier, and bits [17:16] are used to set the valid range of the 16 bits of data; The parameter setting unit is used to set words, and the word setting content includes frame check setting and frame sequence number setting.

3. The Verilog HDL-based multi-channel 2711 digital logic simulation architecture system according to claim 2, characterized in that: In the frame format status identifier, "01" indicates a data error, "11" indicates invalid data, and other values ​​indicate correct data. The data error includes data protocol error and input data frame format error. Data protocol error involves RKMSB, RKLSB, data start bit, data stop bit, and data idle code. Input data frame format error involves frame synchronization header, master header, and data area containing the words "frame synchronization header".

4. The Verilog HDL-based multi-channel 2711 digital logic simulation architecture system according to claim 2, characterized in that: When the bits [17:16] are "11", all 16 bits in the lower 16 bits of data are K code; when they are "01", the higher 8 bits in the lower 16 bits of data are valid data and the lower 8 bits are K code; when they are "10", the higher 8 bits in the lower 16 bits of data are K code and the lower 8 bits are valid data; when they are "00", all 16 bits in the lower 16 bits of data are valid data.

5. The Verilog HDL-based multi-channel 2711 digital logic simulation architecture system according to claim 2, characterized in that: The frame verification settings include frame verification type, frame verification start and end word sequence number, and frame verification field start and end word sequence number; the frame sequence number settings include frame sequence number field start and end word sequence number, frame sequence number field start and end byte high and low bytes, counting step size, and counting start point.

6. The Verilog HDL-based multi-channel 2711 digital logic simulation architecture system according to claim 1, characterized in that: The 2711 model 2711_MOD module includes 4 sub-modules, each of which contains a word setting unit and a word sending unit; The word setting unit is used to implement frame sequence number setting and frame check setting; The transmitting word unit is used to determine the symbol rate of the transmitting word, parse relevant information and determine the specific content of the transmitting word data, and generate the transmitting data word for simulation testing.

7. The Verilog HDL-based multi-channel 2711 digital logic simulation architecture system according to claim 6, characterized in that: The frame sequence number setting is achieved by parsing the 32-bit frame sequence number setting parameter TNUM. In the 32-bit frame sequence number setting, the high 12 bits are the start word sequence number of the frame sequence number field, bits [19:18] are the high and low bytes of the start word of the frame sequence number field, bits [17:6] are the end word sequence number of the frame sequence number field, bits [5:4] are the high and low bytes of the end word of the frame sequence number field, bits [3:2] are the counting step size, and bits [1:0] are the counting start point.

8. The Verilog HDL-based multi-channel 2711 digital logic simulation architecture system according to claim 6, characterized in that: The frame check setting is achieved by parsing three 32-bit frame check setting parameters TCHK0 to TCHK2. TCHK0 is used to set the frame check type, TCHK1 is used to set the frame check start and end word sequence numbers, and TCHK2 is used to set the frame check field start and end word sequence numbers.

9. The Verilog HDL-based multi-channel 2711 digital logic simulation architecture system according to claim 6, characterized in that: The sending word unit parses the 2711 idle code IDLE, length setting LEN, and frame data WORD0~1023, and determines the sending word data by combining the frame check value and the frame sequence number field content; when the frame data bits [19:18] are "11", it uses its own generated random data.

10. The Verilog HDL-based multi-channel 2711 digital logic simulation architecture system according to claim 1, characterized in that: The 2711_MOD module of the 2711 model can generate four independent 2711 data streams simultaneously, and can also obtain n×4 independent 2711 data streams by calling the instantiation method multiple times, where n is the number of instantiation calls.

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