Solar cell, preparation method thereof and photovoltaic module

Abstract

The invention relates to the technical field of batteries, and discloses a solar battery, a preparation method thereof and a photovoltaic module. The solar cell includes: a silicon substrate; the passivation contact structure is arranged on the silicon substrate and comprises a first dielectric layer, a nano silicon layer, a second dielectric layer, a first doping layer, a first functional layer and a first electrode which are arranged in sequence; by arranging the nanometer silicon layer, light absorption can be improved, the passivation effect is enhanced, and the blocking effect on diffusion of doping elements in the first doping layer to the silicon substrate is enhanced; by sequentially arranging the first dielectric layer and the laminated structure formed by the nanometer silicon layer and the second dielectric layer, the double-layer protection effect is achieved, the depth and the concentration of doping elements diffused to the silicon substrate in the first doping layer are reduced, the situation that local thin-thickness positions of the dielectric layers or the first doping layer are burnt through by slurry can be effectively avoided, and the service life of the silicon substrate is prolonged. Therefore, the proportion of bright and dark pieces in luminescence detection is reduced, and the product yield and efficiency are improved.

Description

Technical Field

[0001] This invention relates to the field of battery technology, and in particular to a solar cell, its preparation method, and a photovoltaic module. Background Technology

[0002] Passivated contact solar cells are a type of solar cell that uses an ultrathin oxide layer as the passivation layer structure. Compared with the previous generation PERC (Passivated Emitter and Rear Cell) cells, passivated contact solar cells use an N-type silicon wafer as the substrate, with an added tunneling oxide layer and a doped polycrystalline silicon layer deposited on the back side. This changes the passivation path, allowing carriers to be separated and transported without the need for openings, achieving carrier-selective passivation contacts. This minimizes recombination or losses at the contact between the back metal electrode and the crystalline silicon wafer, thus improving conversion efficiency.

[0003] Currently, because the equipment for manufacturing tunneling oxide layers and doped polysilicon layers is in its early stages, the prepared tunneling oxide layers and doped polysilicon layers have problems such as poor film density and uneven film thickness. Local thin areas in the tunneling oxide layer or doped polysilicon layer lead to slurry burn-through and phosphorus diffusion problems, which will cause them to lose their passivation properties and result in a large number of uneven light and dark phenomena in luminescence detection, leading to a decrease in yield and efficiency. Summary of the Invention

[0004] This invention provides a solar cell, its preparation method, and a photovoltaic module, which can solve the problems of thin local areas of the dielectric layer or doped layer being easily burned through by the paste and the problem of inward expansion of doped elements in the doped layer, thereby reducing the ratio of bright and dark plates in light emission detection and improving product yield and efficiency.

[0005] To solve the above-mentioned technical problems, one technical solution adopted by the present invention is to provide a solar cell, comprising: a silicon substrate, wherein the silicon substrate is doped with a first conductivity type;

[0006] A passivated contact structure is provided on the first surface of the silicon substrate.

[0007] The passivated contact structure includes a first dielectric layer, a nano-silicon layer, a second dielectric layer, a first doped layer, a first functional layer, and a first electrode, which are sequentially disposed from the first surface of the silicon substrate toward the side away from the silicon substrate. The conductivity type of the first doped layer is the same as or opposite to that of the silicon substrate, and the conductivity type of the nano-silicon layer is the same as that of the first doped layer.

[0008] Optionally, the thickness of the nano-silicon layer is 5 nm to 7 nm, and / or the thickness uniformity of the nano-silicon layer is within 3%.

[0009] Optionally, the sheet resistance of the first doped layer is 43 to 47 Ω / sq, and / or the uniformity of the sheet resistance of the first doped layer is within 5%.

[0010] Optionally, the first doped layer includes a first doped sublayer disposed on the side of the second dielectric layer away from the nano-silicon layer and a second doped sublayer disposed on the side of the first doped layer away from the second dielectric layer, wherein the thickness of the first doped sublayer is 40 nm to 50 nm and the thickness of the second doped sublayer is 60 nm to 80 nm.

[0011] Optionally, the doping concentration of the second doped sublayer is greater than the doping concentration of the first doped sublayer.

[0012] Optionally, the doping concentration of the first doped sublayer is 3e19cm. -3 ~4e19cm -3 The doping concentration of the second doped sublayer is 4e21cm. -3 ~5e21cm -3 .

[0013] Optionally, the first conductivity type is N-type or P-type;

[0014] And / or, the thickness of the first dielectric layer and the second dielectric layer is 1nm to 2nm, and the thickness uniformity of the first dielectric layer and the second dielectric layer is within 3%;

[0015] And / or, the solar cell further includes an emitter layer, a passivation layer, a second functional layer, and a second electrode, which are sequentially disposed from the second surface of the silicon substrate toward the side away from the silicon substrate, wherein the conductivity type of the emitter layer is opposite to that of the first doped layer, and the second surface is disposed opposite to the first surface.

[0016] To solve the above-mentioned technical problems, another technical solution adopted by the present invention is: to provide a method for preparing the above-mentioned solar cell, the method comprising:

[0017] A first dielectric layer is deposited on the first surface of a silicon substrate;

[0018] A nano-silicon layer is deposited on the side of the first dielectric layer away from the silicon substrate;

[0019] A second dielectric layer is deposited on the side of the nano-silicon layer away from the silicon substrate;

[0020] A first doped layer is deposited on the side of the second dielectric layer away from the silicon substrate;

[0021] A first functional layer is deposited on the side of the first doped layer away from the silicon substrate;

[0022] A first electrode is fabricated on the side of the first functional layer away from the silicon substrate.

[0023] Optionally, the nano-silicon layer is prepared by plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, laser-induced vapor deposition, or atomic layer deposition.

[0024] And / or, depositing a first doped layer on the side of the second dielectric layer away from the silicon substrate includes:

[0025] A first doped sublayer is deposited on the side of the second dielectric layer away from the silicon substrate;

[0026] A second doped sublayer is deposited on the side of the first doped sublayer away from the silicon substrate;

[0027] And / or, the preparation method further includes:

[0028] The silicon substrate is texturized on its second surface to form a silicon substrate with a textured surface on the second surface, wherein the second surface is disposed opposite to the first surface;

[0029] An emitter layer is formed on the second surface of the silicon substrate;

[0030] A passivation layer is deposited on the side of the emitter layer away from the silicon substrate;

[0031] A second functional layer is deposited on the side of the passivation layer away from the silicon substrate;

[0032] A second electrode is fabricated on the side of the second functional layer away from the silicon substrate;

[0033] And / or, the preparation method further includes:

[0034] The solar cell is sintered to allow the dopant elements in the first doped layer to diffuse into the nano-silicon layer.

[0035] To solve the above-mentioned technical problems, another technical solution adopted by the present invention is to provide a photovoltaic module, including the above-mentioned solar cell.

[0036] The beneficial effects of this invention are as follows: by setting a nano-silicon layer, the absorption of light can be improved, the passivation effect can be enhanced, and the barrier effect on the diffusion of dopants in the first doped layer to the silicon substrate can be enhanced; by sequentially setting a first dielectric layer and a stacked structure formed by the nano-silicon layer and the second dielectric layer, a double-layer protection effect is achieved, reducing the depth and concentration of dopants in the first doped layer to diffuse into the silicon substrate, and effectively preventing the dielectric layer or the thinner parts of the first doped layer from being burned through by the paste, thereby reducing the ratio of bright and dark plates in light emission detection and improving product yield and efficiency. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of a solar cell according to an embodiment of the present invention;

[0038] Figure 2 This is a schematic diagram of another embodiment of a solar cell according to one embodiment of the present invention;

[0039] Figure 3 This is a schematic flowchart of a method for preparing a solar cell according to an embodiment of the present invention;

[0040] Figure 4 This is a schematic flowchart of another embodiment of the method for preparing a solar cell according to one embodiment of the present invention;

[0041] Figure 5 This is a PL test result diagram of the solar cell in Embodiment 1 of the present invention;

[0042] Figure 6 This is a PL test result diagram of the solar cell of Comparative Example 1 of the present invention;

[0043] Figure 7 This is an EL test result diagram of the photovoltaic module of Embodiment 2 of the present invention;

[0044] Figure 8 This is an EL test result diagram of the photovoltaic module of Comparative Example 2 of the present invention.

[0045] The meanings of the labels in the attached diagram are as follows:

[0046] 100 - Solar cell; 10 - Silicon substrate; 20 - First contact structure; 30 - Passivation contact structure; 21 - Textured structure; 22 - Emitter layer; 23 - Passivation layer; 24 - Second functional layer; 25 - Second electrode; 31 - First dielectric layer; 32 - Nano silicon layer; 33 - Second dielectric layer; 34 - First doped layer; 341 - First doped sublayer; 342 - Second doped sublayer; 35 - First functional layer; 36 - First electrode. Detailed Implementation

[0047] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0048] The terms "first," "second," and "third" used in this invention are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this invention are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0049] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0050] One embodiment of the present invention provides a solar cell 100, please refer to [link / reference]. Figure 1 As shown, the solar cell 100 includes a silicon substrate 10 and a passivated contact structure 30.

[0051] The silicon substrate 10 has a first surface 11 and a second surface 12 disposed opposite to each other, and the silicon substrate 10 is doped with a first conductivity type. For example, the silicon substrate 10 may have a first dopant element, which is of a first conductivity type.

[0052] The passivation contact structure 30 is disposed on the first surface 11 of the silicon substrate 10. In the direction from the first surface 11 of the silicon substrate 10 toward the side away from the silicon substrate 10, the passivation contact structure 30 includes a first dielectric layer 31, a nano-silicon layer 32, a second dielectric layer 33, a first doped layer 34, a first functional layer 35, and a first electrode 36 disposed sequentially.

[0053] In this embodiment, the passivated contact structure 30 can effectively prevent metal recombination problems caused by direct contact between the metal paste and the first surface 11 of the silicon substrate 10, thereby improving the open-circuit voltage and short-circuit current of the battery.

[0054] In this embodiment, the nano-silicon layer 32 can improve the absorption of light and enhance the passivation effect, preventing the dopant elements in the first doped layer 34 from diffusing into the silicon substrate 10; the nano-silicon layer 32 can also reduce the recombination of charge carriers and defects, thereby improving the mobility of charge carriers.

[0055] The conductivity type of the first doped layer 34 is the same as or opposite to that of the silicon substrate 10. For example, the first doped layer 34 has a second doping element, which may be of the first conductivity type or of the opposite conductivity type.

[0056] The conductivity type of the nano-silicon layer 32 is the same as that of the first doped layer 34.

[0057] In this embodiment, by setting a nano-silicon layer, light absorption can be improved, passivation can be enhanced, and the barrier effect against the diffusion of dopants from the first doped layer into the silicon substrate can be strengthened. The stacked structure formed by the sequentially set first dielectric layer, nano-silicon layer, and second dielectric layer provides double-layer protection, reducing the depth and concentration of dopants from the first doped layer into the silicon substrate. It also effectively prevents the dielectric layer or thinner areas of the first doped layer from being burned through by the paste, thereby reducing the ratio of bright to dark areas in the light emission detection and improving product yield and efficiency. As one implementation, the thickness of the nano-silicon layer 32 is 5nm to 7nm. In this embodiment, by controlling the thickness of the nano-silicon layer within the above range, the blocking effect is achieved without affecting the output efficiency of the solar cell.

[0058] In one embodiment, the thickness uniformity of the nano-silicon layer 32 is less than or equal to 3%. In this embodiment, by controlling the thickness uniformity of the nano-silicon layer within the above range, it is possible to avoid the formation of locally thinner areas on the nano-silicon layer that are easily burned through by the slurry. This is beneficial for further reducing the ratio of bright and dark films in luminescence detection and further improving product yield and efficiency.

[0059] In some embodiments, the thickness uniformity of the nano-silicon layer 32 can be characterized by sheet resistance uniformity. After depositing the nano-silicon layer 32, the sheet resistance values ​​at multiple different locations of the nano-silicon layer 32 are detected to obtain multiple sheet resistance values. The sheet resistance uniformity of the nano-silicon layer 32 is calculated based on these multiple sheet resistance values, and the sheet resistance uniformity is used as the thickness uniformity of the nano-silicon layer 32. For example, sheet resistance uniformity... Among them, R max R is the maximum value among multiple sheet resistance values. min It is the minimum value among multiple square resistance values.

[0060] As one implementation method, please refer to Figure 2As shown, the second surface 12 of the silicon substrate 10 has a textured structure 21. The solar cell 100 also includes a first contact structure 20 disposed on the second surface 12 of the silicon substrate 10. The first contact structure 20 includes an emitter layer 22, a passivation layer 23, a second functional layer 24, and a second electrode 25 disposed sequentially from the second surface 12 of the silicon substrate 10 toward the side away from the silicon substrate 10. The conductivity type of the emitter layer 22 is opposite to the conductivity type of the first doped layer 34.

[0061] In one embodiment, the doping of the nano-silicon layer 32 can be formed by the diffusion of the doping element of the first doped layer 34 into the nano-silicon layer 32. In this embodiment, it is not necessary to dop the raw material for fabricating the nano-silicon layer or to inject doping elements after the nano-silicon layer is deposited. The doping of the nano-silicon layer is achieved by the diffusion of the doping element in the first doped layer 34, which can enhance the barrier effect of the nano-silicon layer and further reduce the diffusion of doping elements into the silicon substrate.

[0062] As one embodiment, the first conductivity type can be N-type or P-type, and the silicon substrate 10 has N-type or P-type doping. For example, the silicon substrate 10 can be N-type crystalline silicon with a resistivity of 0.6 Ω·cm to 1.6 Ω·cm and a thickness of 100 μm to 150 μm.

[0063] In one embodiment, the thickness of the first dielectric layer 31 is 1 nm to 2 nm, and the thickness uniformity is within 3%. This embodiment controls the thickness uniformity of the first dielectric layer to within 3%, which solves the problems of paste burn-through and dopant diffusion into the silicon substrate caused by locally thin areas, thereby improving passivation performance. Exemplarily, the thickness uniformity of the first dielectric layer 31 can be sheet resistance uniformity, and the testing method is similar to that of the thickness uniformity of the nano-silicon layer 32, which will not be elaborated here.

[0064] In one embodiment, the thickness of the second dielectric layer 33 is 1 nm to 2 nm, and the thickness uniformity is within 3%. This embodiment controls the thickness uniformity of the second dielectric layer to within 3%, which solves the problems of paste burn-through and dopant diffusion into the silicon substrate caused by locally thin areas, thereby improving passivation performance. Exemplarily, the thickness uniformity of the second dielectric layer 33 can be sheet resistance uniformity, and the testing method is similar to that of the thickness uniformity of the nano-silicon layer 32, which will not be elaborated here.

[0065] In one embodiment, the solar cell 100 can be a tunnel oxide passivating contact (TOPCon) solar cell. The silicon substrate 10 is an N-type silicon substrate, the first dielectric layer 31 and the second dielectric layer 33 are tunnel oxide layers, the first doped layer 34 is N-type doped, and the nano-silicon layer 32 is also N-type doped, for example, the first doped layer 34 is phosphorus doped. In this embodiment, electrons tunnel sequentially from the first dielectric layer 31 into the nano-silicon layer 32, from the nano-silicon layer 32 into the second dielectric layer 33, and from the second dielectric layer 33 into the first doped layer 34. The electrons are then laterally transported in the first doped layer 34 and collected by the metal (first electrode 36). At the same time, the first dielectric layer 31, the N-type doped nano-silicon layer 32, and the second dielectric layer 33 can block hole recombination, thereby greatly reducing the metal contact recombination current and improving the open-circuit voltage and short-circuit current of the cell.

[0066] For example, the first dielectric layer 31 and the second dielectric layer 33 may be silicon oxide layers, respectively.

[0067] As one embodiment, the solar cell 100 can be rectangular or square. For example, taking a rectangular shape as an example, the length of the solar cell 100 is 180mm to 230mm, the width is 180mm to 230mm, and the thickness is 100μm to 150μm.

[0068] As one embodiment, the sheet resistance of the first doped layer 34 can be 43-47 Ω / sq, for example, 45 Ω / sq; the uniformity of the sheet resistance of the first doped layer 34 is within 5%. This embodiment controls the sheet resistance uniformity of the first doped layer to within 5%, which can improve the stability and reliability of the first doped layer 34. Exemplarily, the first doped layer 34 can be a polycrystalline silicon layer.

[0069] As one example, please refer to Figure 3 The first doped layer 34 includes a first doped sublayer 341 disposed on the side of the second dielectric layer 33 away from the nano-silicon layer 32 and a second doped sublayer 342 disposed on the side of the first doped sublayer 341 away from the second dielectric layer 33. The thickness of the first doped sublayer 341 is 40 nm to 50 nm, and the thickness of the second doped sublayer 342 is 60 nm to 80 nm. For example, the first doped layer 34 can be a polycrystalline silicon layer, and the first doped sublayer 341 and the second doped sublayer 342 can each be a polycrystalline silicon layer.

[0070] The doping concentration of the second doped sublayer 342 is greater than that of the first doped sublayer 341.

[0071] Specifically, the doping concentration of the first doped sublayer 341 is 3e19cm.-3 ~4e19cm -3 The doping concentration of the second doped sublayer 342 is 4e21cm. -3 ~5e21cm -3 In this embodiment, the first doped sublayer 341 has a low doping concentration, which can reduce the diffusion depth and concentration of dopants in the first doped sublayer 341, and further reduce parasitic absorption in the long wavelength range, thereby improving the short-circuit current of the battery. The second doped sublayer 342 has a high doping concentration, which can reduce the contact resistivity with the metal, while also improving the fill factor, greatly reducing the ratio of bright and dark spots in light emission detection, and improving the yield and efficiency of the product.

[0072] In other embodiments, concentration gradient doping can also be performed within the first doped sublayer and / or the second doped sublayer. For example, when preparing the first doped layer 34, phosphorus doping with different concentration gradients can be performed to form a first doped sublayer 341 with a lower doping concentration. This can be understood as follows: within the first doped sublayer 341, the concentration gradient increases from the side closer to the second dielectric layer 33 towards the side closer to the second doped sublayer 342, which is beneficial for reducing the depth and concentration of phosphorus diffusion from the first doped sublayer 341 into the silicon substrate 10. For example, when preparing the first doped layer 34, phosphorus doping with different concentration gradients can be performed to form a second doped sublayer 342 with a higher doping concentration. This can be understood as follows: within the second doped sublayer 342, the concentration gradient increases from the side closer to the first doped sublayer 341 towards the side closer to the first functional layer 35, which is beneficial for reducing the contact resistivity with the metal.

[0073] As one embodiment, the emitter layer 22 is a boron-doped P+ type emitter.

[0074] As one embodiment, the passivation layer 23 is an aluminum oxide layer with a thickness of 3nm-4nm.

[0075] As one embodiment, both the second functional layer 24 and the first functional layer 35 can be silicon nitride layers.

[0076] In one embodiment, the second electrode 25 is an Ag / Al gate electrode, and the first electrode 36 is an Ag gate electrode.

[0077] An embodiment of the present invention also provides a method for preparing a solar cell, used to prepare the solar cell 100 of the above embodiment. Please refer to [link to previous text]. Figure 4 As shown, the method for fabricating this solar cell includes the following steps:

[0078] Step S01: Deposit a first dielectric layer on the first surface of the silicon substrate;

[0079] Step S02: Deposit a nano-silicon layer on the side of the first dielectric layer away from the silicon substrate;

[0080] Step S03: Deposit a second dielectric layer on the side of the nano-silicon layer away from the silicon substrate;

[0081] Step S04: Deposit a first doped layer on the side of the second dielectric layer away from the silicon substrate;

[0082] Step S05: Deposit a first functional layer on the side of the first doped layer away from the silicon substrate;

[0083] Step S06: Fabricate a first electrode on the side of the first functional layer away from the silicon substrate.

[0084] In this embodiment, by depositing a nano-silicon layer, the absorption of light can be improved, the passivation effect can be enhanced, and the barrier effect on the diffusion of dopants in the first doped layer to the silicon substrate can be enhanced. By sequentially setting the first dielectric layer and the stacked structure formed by the nano-silicon layer and the second dielectric layer, a double-layer protection effect is achieved, which reduces the depth and concentration of dopants in the first doped layer to diffuse into the silicon substrate, and can effectively prevent the dielectric layer or the thinner parts of the first doped layer from being burned through by the paste, thereby reducing the ratio of bright and dark plates in the light emission detection and improving product yield and efficiency.

[0085] In one embodiment, in step S02, the nano-silicon layer is prepared by plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), laser-induced chemical vapor deposition (LCVD), or atomic layer deposition (ALD).

[0086] As one implementation method, step S04 specifically includes the following steps:

[0087] Step S04a: Deposit a first doped sublayer on the side of the second dielectric layer away from the silicon substrate;

[0088] Step S04b: Deposit a second doped sublayer on the side of the first doped sublayer away from the silicon substrate.

[0089] In this embodiment, the first doped sublayer has a low doping concentration, which can reduce the diffusion depth and concentration of dopants in the first doped sublayer, and further reduce parasitic absorption in the long wavelength range, thereby increasing the short-circuit current of the battery; the second doped sublayer has a high doping concentration, which can reduce the contact resistivity with the metal, while also improving the fill factor, greatly reducing the ratio of bright and dark spots in light emission detection, and improving the yield and efficiency of the product.

[0090] As one implementation method, the solar cell fabrication method of this embodiment further includes the following steps:

[0091] A texturing process is performed on the second surface of a silicon substrate to form a silicon substrate with a texturing structure on the second surface, wherein the second surface is disposed opposite to the first surface;

[0092] An emitter layer is fabricated on the second surface of a silicon substrate;

[0093] A passivation layer is deposited on the side of the emitter layer away from the silicon substrate;

[0094] A second functional layer is deposited on the side of the passivation layer away from the silicon substrate;

[0095] A second electrode is fabricated on the side of the second functional layer away from the silicon substrate.

[0096] As one implementation method, the solar cell fabrication method of this embodiment further includes the following steps:

[0097] The solar cell is sintered to allow the dopant elements in the first doped layer to diffuse into the nano-silicon layer.

[0098] In this embodiment, there is no need to dop the raw materials for fabricating the nano-silicon layer or inject dopant elements after the nano-silicon layer is deposited. The nano-silicon layer is doped by the diffusion of dopant elements in the first doped layer, which can enhance the barrier effect of the nano-silicon layer and further reduce the diffusion of dopant elements into the silicon substrate.

[0099] As one implementation method, the fabrication method of this solar cell includes the following steps:

[0100] Step S1: A textured structure and an emitter layer are sequentially fabricated on the front side of the silicon substrate.

[0101] Specifically, N-type crystalline silicon with a resistivity of 0.6 Ω·cm to 1.6 Ω·cm and a thickness of 100 μm to 150 μm was selected. First, a texturing machine was used for pre-cleaning and texturing to prepare a textured structure. Then, on the texturized silicon substrate, a P+ type emitter, i.e., the emitter layer, was prepared by diffusion of BCl3 and oxygen at a temperature of 950℃ to 1020℃, with a sheet resistance of 425 Ω / sq.

[0102] Step S2: The back side and edges of the silicon substrate are cleaned using a wet cleaning method and then subjected to alkaline polishing.

[0103] Step S3: A first dielectric layer, a nano-silicon layer, a second dielectric layer, and a first doped layer are sequentially deposited on the back side of the silicon substrate using PECVD deposition.

[0104] Specifically, the silicon substrate, after alkaline polishing, enters a PECVD (Plasma Enhanced Chemical Vapor Deposition) furnace, where a first dielectric layer, a nano-silicon layer, a second dielectric layer, and a first doped layer are sequentially deposited on the back side of the silicon substrate. The nano-silicon layer has a thickness of 5 nm to 7 nm, with a thickness uniformity within 3%. The first dielectric layer is silicon oxide, with a thickness of 1 nm to 2 nm, and a thickness uniformity within 3%. The second dielectric layer is also silicon oxide, with a thickness of 1 nm to 2 nm, and a thickness uniformity within 3%. The sheet resistance of the first doped layer is 45 Ω / sq, with a sheet resistance uniformity within 5%. This embodiment controls the thickness uniformity of the nano-silicon layer, the first dielectric layer, and the second dielectric layer to within 3%, which solves the problem of paste burn-through and phosphorus diffusion caused by locally thin dielectric layers, thereby improving passivation performance.

[0105] As one embodiment, the first doped layer includes a first doped sublayer and a second doped sublayer. In step S3, a first dielectric layer, a nano-silicon layer, a second dielectric layer, a first doped sublayer, and a second doped sublayer are sequentially deposited on the back side of the silicon substrate using PECVD deposition. The thickness of the first doped sublayer is 40 nm to 50 nm, and the thickness of the second doped sublayer is 60 nm to 80 nm. The doping concentration of the second doped sublayer is greater than that of the first doped sublayer. Specifically, the doping concentration of the first doped sublayer is 3e19 cm⁻¹. -3 ~4e19cm -3 The doping concentration of the second doped sublayer is 4e21cm. -3 ~5e21cm -3 In other embodiments, concentration gradient doping may also be performed within the first doped sublayer and / or the second doped sublayer.

[0106] Step S4: Clean the first dielectric layer, the second dielectric layer, and the first doped layer that are coated around the edge and front of the silicon substrate using hydrofluoric acid and sodium hydroxide.

[0107] Step S5: A passivation layer is prepared on the side of the emitter layer away from the textured structure using atomic layer deposition.

[0108] Specifically, the passivation layer is aluminum oxide with a thickness of 3nm-4nm.

[0109] Step S6: Deposit a second functional layer on the side of the passivation layer away from the emitter layer using tubular PECVD, and deposit a first functional layer on the side of the first doped layer away from the second dielectric layer.

[0110] Specifically, both the second functional layer and the first functional layer are silicon nitride, with the second functional layer having a thickness of 63nm-83nm and the first functional layer having a thickness of 73nm-107nm.

[0111] Step S7: The first electrode is printed on the back side of the silicon substrate using screen printing, and the second electrode is printed on the front side of the silicon substrate. Then, the first electrode and the second electrode are sequentially processed through sintering, light injection, and laser-assisted sintering to form silver-silicon contacts with the silicon substrate.

[0112] Specifically, Ag paste for back and front electrodes is printed on the back side of the silicon substrate using screen printing; after sintering, good ohmic contact is formed; defects in the cell body and surface are repaired by light injection; and charge carriers are excited by laser-assisted sintering, thereby improving the cell conversion efficiency and fill factor. The second electrode is an Ag / Al grid electrode, and the first electrode is an Ag grid electrode.

[0113] This invention also provides a photovoltaic module, including the aforementioned solar cell 100. The photovoltaic module of this embodiment, by setting a nano-silicon layer, can improve light absorption, enhance passivation, and strengthen the barrier against the diffusion of dopant elements from the first doped layer into the silicon substrate. By sequentially setting a first dielectric layer and a stacked structure formed by the nano-silicon layer and the second dielectric layer, a double-layer protection is achieved, reducing the depth and concentration of dopant elements from the first doped layer into the silicon substrate. It can also effectively prevent the dielectric layer or areas where the first doped layer is locally thin from being burned through by the paste, thereby reducing the ratio of bright to dark areas in the light emission detection and improving product yield and efficiency.

[0114] Example 1

[0115] The solar cell 100 prepared by the above-described method of preparing a solar cell using steps S1 to S6 includes: a silicon substrate, a front structure disposed on the front side of the silicon substrate, and a passivation contact structure disposed on the back side of the silicon substrate; the front structure includes a textured structure, an emitter layer, a passivation layer, a second functional layer, and a second electrode sequentially disposed from the front side of the silicon substrate toward the side away from the silicon substrate; the passivation contact structure includes a first dielectric layer, a nano-silicon layer, a second dielectric layer, a first doped sublayer, a second doped sublayer, a first functional layer, and a first electrode sequentially disposed from the back side of the silicon substrate toward the side away from the silicon substrate.

[0116] The structural parameters are as follows:

[0117] The solar cell is 182mm long, 210mm wide, and 130μm thick;

[0118] Silicon substrate: N-type crystalline silicon, resistivity 0.6 Ω·cm~1.6 Ω·cm, thickness 130 μm;

[0119] Emitter layer: Sheet resistance is 425Ω / sq;

[0120] First dielectric layer: 1.2 nm thick;

[0121] Nano-silicon layer: 5.5 nm thick;

[0122] Second dielectric layer: 1.2 nm thick;

[0123] First doped sublayer: 45 nm thick, doping concentration 3e19cm -3 ;

[0124] Second doped sublayer: 70 nm thick, doping concentration 4e21cm -3 ;

[0125] Passivation layer: made of aluminum oxide, with a thickness of 3.5nm;

[0126] Second functional layer: made of silicon nitride, with a thickness of 73nm;

[0127] First functional layer: made of silicon nitride, with a thickness of 90nm.

[0128] Example 2

[0129] The solar cell of Example 1 is applied in a photovoltaic module.

[0130] Comparative Example 1

[0131] The solar cell was prepared using the same preparation method. The difference from Example 1 is that in step S3, only one dielectric layer and one first doped layer were prepared. Other structural parameters were the same as in Example 1.

[0132] Comparative Example 2

[0133] The solar cells of Comparative Example 1 are applied in photovoltaic modules.

[0134] test

[0135] Photoluminescence (PL) tests were performed on the solar cells of Example 1 and Comparative Example 1, respectively, and the results were as follows: Figure 5-6 The diagram shows a contrast between light and dark areas; EL (Electroluminescence) tests were performed on the photovoltaic modules of Example 2 and Comparative Example 2, respectively, and the results are as follows. Figure 7-8The diagram shows the contrast between light and dark areas. Test results show that the solar cell of Example 1, by incorporating a nano-silicon layer, can improve light absorption, act as a passivator, and prevent phosphorus in the first doped layer from diffusing into the silicon substrate. The combination of the nano-silicon layer and the second dielectric layer provides double-layer protection, further reducing the depth and concentration of phosphorus diffusion into the silicon substrate. This solves the problem of paste burn-through and phosphorus inward diffusion caused by localized thinness in the dielectric layer or the first doped layer, thereby reducing the proportion of bright and dark areas in the light emission detection. Similarly, compared to Comparative Example 2, the photovoltaic module of Example 2 also effectively reduces the proportion of bright and dark areas in the light emission detection.

[0136] The above are merely embodiments of the present invention and do not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A solar cell, characterized in that, include: A silicon substrate, wherein the silicon substrate is doped with a first conductivity type; A passivated contact structure is provided on the first surface of the silicon substrate. The passivated contact structure includes a first dielectric layer, a nano-silicon layer, a second dielectric layer, a first doped layer, a first functional layer, and a first electrode, which are sequentially disposed from the first surface of the silicon substrate toward the side away from the silicon substrate. The conductivity type of the first doped layer is the same as or opposite to that of the silicon substrate, and the conductivity type of the nano-silicon layer is the same as that of the first doped layer.

2. The solar cell according to claim 1, characterized in that, The thickness of the nano-silicon layer is 5nm to 7nm, and / or the thickness uniformity of the nano-silicon layer is within 3%.

3. The solar cell according to claim 1, characterized in that, The sheet resistance of the first doped layer is 43 to 47 Ω / sq, and / or the uniformity of the sheet resistance of the first doped layer is within 5%.

4. The solar cell according to claim 3, characterized in that, The first doped layer includes a first doped sublayer disposed on the side of the second dielectric layer away from the nano-silicon layer and a second doped sublayer disposed on the side of the first doped layer away from the second dielectric layer. The thickness of the first doped sublayer is 40nm to 50nm, and the thickness of the second doped sublayer is 60nm to 80nm.

5. The solar cell according to claim 4, characterized in that, The doping concentration of the second doped sublayer is greater than that of the first doped sublayer.

6. The solar cell according to claim 5, characterized in that, The doping concentration of the first doped sublayer is 3e19cm. -3 ~4e19cm -3 The doping concentration of the second doped sublayer is 4e21cm. -3 ~5e21cm -3 .

7. The solar cell according to claim 1, characterized in that, The first conductivity type is N-type or P-type; And / or, the thickness of the first dielectric layer and the second dielectric layer is 1nm to 2nm, and the thickness uniformity of the first dielectric layer and the second dielectric layer is within 3%; And / or, the solar cell further includes an emitter layer, a passivation layer, a second functional layer, and a second electrode, which are sequentially disposed from the second surface of the silicon substrate toward the side away from the silicon substrate, wherein the conductivity type of the emitter layer is opposite to that of the first doped layer, and the second surface is disposed opposite to the first surface.

8. A method for preparing a solar cell as described in any one of claims 1-7, characterized in that, The preparation method includes: A first dielectric layer is deposited on the first surface of a silicon substrate; A nano-silicon layer is deposited on the side of the first dielectric layer away from the silicon substrate; A second dielectric layer is deposited on the side of the nano-silicon layer away from the silicon substrate; A first doped layer is deposited on the side of the second dielectric layer away from the silicon substrate; A first functional layer is deposited on the side of the first doped layer away from the silicon substrate; A first electrode is fabricated on the side of the first functional layer away from the silicon substrate.

9. The method for preparing a solar cell according to claim 8, characterized in that, The nano-silicon layer is prepared by plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, laser-induced vapor deposition, or atomic layer deposition. And / or, depositing a first doped layer on the side of the second dielectric layer away from the silicon substrate includes: A first doped sublayer is deposited on the side of the second dielectric layer away from the silicon substrate; A second doped sublayer is deposited on the side of the first doped sublayer away from the silicon substrate; And / or, the preparation method further includes: The silicon substrate is texturized on its second surface to form a silicon substrate with a textured surface on the second surface, wherein the second surface is disposed opposite to the first surface; An emitter layer is formed on the second surface of the silicon substrate; A passivation layer is deposited on the side of the emitter layer away from the silicon substrate; A second functional layer is deposited on the side of the passivation layer away from the silicon substrate; A second electrode is fabricated on the side of the second functional layer away from the silicon substrate; And / or, the preparation method further includes: The solar cell is sintered to allow the dopant elements in the first doped layer to diffuse into the nano-silicon layer.

10. A photovoltaic module, characterized in that, Including the solar cell as described in any one of claims 1-7.

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