Memory access methods, multi-core systems, processors and system-on-a-chip

Abstract

This application discloses a memory access method, a multi-core system, a processor, and a system-on-a-chip, relating to the field of processors. The method includes: in response to a received atomic operation, determining the memory address carried in the atomic operation; based on the memory address, determining the address layout state of first data in memory, wherein the address layout state characterizes whether the memory address crosses the cache line boundary or data page boundary of any processing unit; if the address layout state characterizes that the memory address crosses the cache line boundary or data page boundary, splitting the atomic operation into multiple first sub-operations, wherein different first sub-operations carry different sub-addresses; and based on the sub-addresses carried by the multiple first sub-operations, accessing the first data stored in memory through the cache of any processing unit. This application solves the technical problem of low processing efficiency in multi-core systems caused by improper control of unaligned atomic operations.

Description

Technical Field

[0001] This application relates to the field of processors, and more specifically, to a memory access method, a multi-core system, a processor, and a system-on-a-chip. Background Technology

[0002] Server-side CPUs (Central Processing Units) typically require multiple processing units to work collaboratively, often necessitating the use of atomic operations to ensure that memory operations performed by a single processing unit are not affected by those of other processing units. Unaligned atomic operations are a type of atomic operation that refers to situations where the operands of an atomic operation span multiple cache segments.

[0003] In current common technical solutions, to prevent other processors from accessing memory during unaligned atomic operations, a LOCK prefix is ​​inserted before the instruction executing the unaligned atomic operation. However, this method locks memory. While it ensures that other processors cannot access the cache segment corresponding to the unaligned atomic operation, it also prevents other cache segments in memory from being accessed by other processors, leading to a decrease in the processing efficiency of multi-core systems.

[0004] There is currently no effective solution to the above problems. Summary of the Invention

[0005] This application provides a memory access method, a multi-core system, a processor, and a system-on-a-chip to at least solve the technical problem of low processing efficiency in multi-core systems caused by improper control of unaligned atomic operations.

[0006] According to one aspect of the embodiments of this application, a memory access method is provided, applied to any processing unit in a multi-core system, the multi-core system including at least: multiple processing units and memory, the method comprising: in response to a received atomic operation, determining a memory address carried in the atomic operation, wherein the memory address is used to characterize the address in memory where first data to be accessed by the atomic operation is stored; based on the memory address, determining an address layout state in memory for the first data, wherein the address layout state is used to characterize whether the memory address crosses a cache line boundary or a data page boundary of any processing unit; if the address layout state characterizes that the memory address crosses a cache line boundary or a data page boundary, splitting the atomic operation into multiple first sub-operations, wherein different first sub-operations carry different sub-addresses; and based on the sub-addresses carried by the multiple first sub-operations, accessing the first data stored in memory through the cache of any processing unit.

[0007] According to another aspect of the embodiments of this application, a multi-core system is also provided, including: memory for storing data; a plurality of processing units connected to the memory, each processing unit including a cache for interacting with the memory, and each processing unit for executing the memory access method described above.

[0008] According to another aspect of the embodiments of this application, a processor is also provided, including: a plurality of processing units, any one of which is used to execute the methods in the various embodiments of this application.

[0009] According to another aspect of the embodiments of this application, a system-on-a-chip is also provided, including: memory and processor.

[0010] According to another aspect of the embodiments of this application, a computing device is also provided, including: a memory; a storage device storing an executable program; and a processor for running the program, wherein the processor includes a plurality of processing units, and the program implements the methods according to the various embodiments of this application when executed by any one of the processing units.

[0011] According to another aspect of the embodiments of this application, a computer-readable storage medium is also provided, the computer-readable storage medium including a stored executable program, wherein the methods according to various embodiments of this application are implemented when the executable program is executed by a processor.

[0012] According to another aspect of the embodiments of this application, a computer program product is also provided, including computer instructions that, when executed by a processor, implement the methods in various embodiments of this application.

[0013] According to another aspect of the embodiments of this application, a computer program product is also provided, including a non-volatile computer-readable storage medium storing a computer program that, when executed by a processor, implements the methods in various embodiments of this application.

[0014] According to another aspect of the embodiments of this application, a computer program is also provided, which, when executed by a processor, implements the methods of the various embodiments of this application.

[0015] In this embodiment, in response to a received atomic operation, the memory address carried in the atomic operation is determined; based on the memory address, the address layout state of the first data in memory is determined; when the address layout state indicates that the memory address crosses a cache line boundary or a data page boundary, the atomic operation is split into multiple first sub-operations; based on the sub-addresses carried in the multiple first sub-operations, the first data stored in memory is accessed through the cache of any processing unit. It is readily apparent that by distinguishing the address layout state of the first data to be accessed by the atomic operation using the memory address, and splitting the atomic operation into multiple first sub-operations according to the address layout state, since the atomic operation has been split into multiple first sub-operations, it is only necessary to ensure that the storage space corresponding to the sub-address is not accessed by other processing units when the first sub-operation accesses the sub-address. It is not necessary to lock the entire memory. Furthermore, accessing the first data stored in memory based on the sub-addresses in the multiple sub-operations still ensures the smooth execution of the atomic operation. By avoiding locking the entire memory, the goal of not restricting access to other processing units is achieved, thereby improving the processing efficiency of processing units in a multi-core system. This solves the technical problem of low processing efficiency in multi-core systems caused by improper control of unaligned atomic operations.

[0016] It is worth noting that the general description above and the detailed description that follow are merely for illustrative purposes and do not constitute a limitation on this application. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0018] Figure 1 This is a hardware structure block diagram of a RISC-V system for implementing a memory access method according to an embodiment of this application;

[0019] Figure 2 This is a method of using the above according to an embodiment of this application. Figure 1 A schematic diagram of a RISC-V architecture on-chip system is shown.

[0020] Figure 3 This is a flowchart of a memory access method according to an embodiment of this application;

[0021] Figure 4 This is a schematic diagram of a processing unit accessing storage space in an optional multi-core system according to an embodiment of this application;

[0022] Figure 5 This is a flowchart of an optional atomic operation for accessing memory according to an embodiment of this application;

[0023] Figure 6 This is a flowchart of a method for accessing memory when the address of data corresponding to an optional atomic operation crosses a cache line boundary, according to an embodiment of this application.

[0024] Figure 7 This is a schematic diagram illustrating the correspondence between an optional atomic operation and a virtual data page and a cache line according to an embodiment of this application;

[0025] Figure 8 This is a schematic diagram of a multi-core system according to an embodiment of this application;

[0026] Figure 9 This is a structural block diagram of an electronic device according to an embodiment of this application. Detailed Implementation

[0027] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0028] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0029] First, some nouns or terms that appear in the description of the embodiments of this application shall be interpreted as follows:

[0030] Atomic operation: One or a series of operations whose execution cannot be interrupted.

[0031] Near-atomic operations: Atomic operations performed internally by the requesting node that maintains consistency are called near-atomic operations.

[0032] Unaligned atomic operations: In atomic operations, the operands span multiple cache segments, potentially across cache lines or even pages. In unaligned atomic operations, the address and size of the target data are not aligned to specific bytes.

[0033] cache: A storage device that enables high-speed data exchange.

[0034] Cache line: The smallest unit of operation in the cache.

[0035] Physical address: The memory address of a specific storage unit in main memory that can be accessed by the data bus.

[0036] Additionally, it should be noted that in the embodiments of this application, the concept of "core" is equivalent to "processing unit".

[0037] Example 1

[0038] According to an embodiment of this application, a memory access method is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0039] The method embodiment provided in Embodiment 1 of this application can be used in various multi-core systems, such as RISC-V (Reduced Instruction Set Computing-Five) systems, x86 (a processor architecture) systems, ARM (a processor architecture) systems, etc., but is not limited thereto. Figure 1 A hardware block diagram of a RISC-V system for implementing memory access methods is shown. Figure 1As shown, the RISC-V system 100 can be divided into the following layers from bottom to top: Reduced Instruction Set Architecture 101 (including the basic instruction set 101-1 and the extended instruction set 101-2), hardware layer 102 (including processor 102-1, peripheral hardware circuits 102-2, etc.), interface layer 103, operating system layer 104 (supporting multiple operating systems 104-1, 104-2, ..., 104-n, such as Linux, FreeSBD, RT-Tread, etc.), middleware and library layer 105 (including system library 105-1, API 105-2 and middleware services 105-3) and application layer 106 (including multiple user programs and services 106-1, 106-2, ..., 106-n). The RISC-V system 100 also includes a toolchain 107 that runs from the underlying hardware to the application layer. This toolchain may include compilers and assemblers 107-1, linkers 107-2, debuggers 107-3, simulators and emulators 107-4, integrated development environments 107-5, hardware description language tools 107-6, performance analysis tools 107-7, and version control systems 107-8, etc.

[0040] The instruction set architecture 101 defines the basic operations and instruction sets supported by the processor 102-1, including the basic instruction set and the extended instruction set. The basic instruction set represents the basic integer instruction set, such as RV32I and RV64I, while the extended instruction set can be floating-point, primitive suboperations, compressed instructions, etc.

[0041] Interface layer 103 includes the specific design of the processor, such as pipeline design, cache structure, execution units, branch prediction, etc. This layer is the process of mapping abstract instructions to physical hardware.

[0042] The operating system layer 104 sits above the hardware, providing a hardware abstraction layer and management mechanisms, enabling applications to interact with the hardware through system calls. The operating system is responsible for managing processor resources, memory, device drivers, task scheduling, and more.

[0043] The middleware and library layer 105 provides a rich set of services and interfaces to help applications run more efficiently. For example, the standard library provides functions such as file operations and mathematical calculations, while middleware can provide complex services such as network communication and graphical user interfaces.

[0044] The application layer 106 utilizes the functions and services provided by the lower layer to implement specific application logic. These applications can be command-line tools, graphical interface applications, server-side services, etc.

[0045] Toolchain 107 is a key component connecting the underlying hardware to the upper-level software. The various tools in toolchain 107 play a role at different levels to support the entire process from hardware design to software development, ensuring the coherence and effectiveness of the entire system design.

[0046] It should be noted that the layered design of the RISC-V architecture allows for decoupling between different layers, enabling each layer to be developed and optimized independently.

[0047] In one alternative embodiment, Figure 2 The above demonstrates the use of Figure 1 The diagram shows a System-on-a-Chip (SOC) based on the RISC-V architecture. Figure 2 As shown, the SOC contains at least one RISC-V core 202 (only one is shown in the figure). The RISC-V core 202 is connected to peripheral devices via bus 204, including but not limited to ROM 206, RAM 208, timer 210, UART (Universal Asynchronous Receiver / Transmitter) 212, GPIO (General Purpose Input / Output) 214, SPI (Serial Peripheral Interface Bus) 216, etc.

[0048] Under the aforementioned operating environment, this application provides the following: Figure 3 The memory access method shown. Figure 3 This is a flowchart of a memory access method according to an embodiment of this application, the method as follows: Figure 3 As shown:

[0049] Step S302: In response to the received atomic operation, determine the memory address carried in the atomic operation, wherein the memory address is used to characterize the address in memory where the first data to be accessed by the atomic operation is stored.

[0050] The atomic operations described above are operations that cannot be interrupted during execution and are the smallest indivisible unit of operation. In this embodiment, the atomic operation refers to an unaligned atomic operation, meaning that the object of the atomic operation spans multiple cache segments, potentially across cache lines or even pages.

[0051] The memory address in the above steps is used to uniquely identify the location of data stored in memory, and the data stored in memory can be accessed through the memory address.

[0052] The first data in the above steps is the data that the atomic operation needs to access during the atomic operation. The first data is stored in memory and can be accessed according to the memory address carried in the atomic operation.

[0053] In one optional embodiment, after the atomic operation enters the load queue, the address of the first data to be accessed carried in the atomic operation is obtained. The address of the first data can be a logical address or a physical address. If the address of the first data is a logical address, address translation is performed based on the logical address to convert it into the corresponding physical address, i.e., a memory address. If the address of the first data is a physical address, no address translation is required, and the physical address of the first data can be directly used as a memory address.

[0054] Step S304: Based on the memory address, determine the address layout state of the first data in memory, wherein the address layout state is used to characterize whether the memory address crosses the cache line boundary or data page boundary of any processing unit.

[0055] The address layout state in the above steps can characterize whether memory addresses are in the same cache line or the same data page. If memory addresses are not in the same data page, the address layout state crosses the data page boundary; if memory addresses are in the same data page, and are not in the same cache line, the address layout state crosses the cache line boundary; if memory addresses are in the same cache line, the address layout state neither crosses the data page boundary nor the cache line boundary.

[0056] In one optional embodiment, the location of the first data in memory can be determined based on the memory address. Memory typically contains multiple data pages, and each data page typically contains multiple cache lines. The first data may be stored in the same cache, or it may be stored across cache lines; it may be stored in a single data page, or it may be stored across multiple data pages. If the first data crosses the cache line boundary or data page boundary of a processing unit in memory, it also indicates that the atomic operation corresponding to the first data is an unaligned atomic operation.

[0057] After obtaining the memory address, the cache line size and data page size of the processing unit can be determined according to the processing unit's manual, thereby determining the addresses corresponding to the cache line boundaries and data page boundaries. By comparing the memory address with the addresses corresponding to the cache line boundaries and data page boundaries, the address layout status of the first data in memory can be determined.

[0058] Step S306: When the address layout state indicates that the memory address crosses the cache line boundary or data page boundary, the atomic operation is split into multiple first sub-operations, wherein the sub-addresses carried in different first sub-operations are different.

[0059] The first sub-operation in the above steps can access a portion of the first data, and the union of the data accessed by all the first sub-operations is the entire first data.

[0060] The sub-address in the above steps is the address corresponding to a portion of the data in the first data that can be accessed by the first sub-operation.

[0061] In one optional embodiment, when the address layout state indicates that the memory address crosses a cache line boundary or a data page boundary, the data access operation between the starting address corresponding to the first data and the address corresponding to the cache line boundary or data page boundary is divided into a first sub-operation; the data access operation between the address corresponding to the cache line boundary or data page boundary and the ending address corresponding to the first data is divided into another first sub-operation. The address that needs to be accessed in each first sub-operation is recorded as a sub-address within the first sub-operation.

[0062] It should be noted that the above-mentioned splitting of atomic operations refers to splitting the process of atomic operations accessing data, that is, splitting the process of atomic operations accessing data into multiple operations, rather than splitting the execution process of atomic operations after accessing data.

[0063] Step S308: Based on the sub-address carried in the multiple first sub-operations, access the first data stored in memory through the cache of any processing unit.

[0064] The caching mentioned above is a technique for temporarily storing data to speed up data access. It is typically used to store frequently accessed data to reduce the number of memory accesses, thereby improving system responsiveness. When the CPU accesses data in memory, it first checks if the data is in the cache. If it is, there is no need to continue accessing memory; the data can be retrieved from the cache. If not, the CPU continues to search for the data in memory and retrieves it from memory.

[0065] In one optional embodiment, each first sub-operation accesses memory based on the carried sub-address to obtain a portion of the data in the first data. Specifically, the first sub-operation searches the index table in the cache based on the sub-address. If the sub-address is found in the index table, the data corresponding to the sub-address, i.e., a portion of the data in the first data, can be directly retrieved from the cache.

[0066] After multiple first sub-operations access memory to obtain data, the data obtained from the memory accesses of multiple sub-operations are concatenated to obtain the first data.

[0067] In this embodiment, in response to a received atomic operation, the memory address carried in the atomic operation is determined; based on the memory address, the address layout state of the first data in memory is determined; when the address layout state indicates that the memory address crosses a cache line boundary or a data page boundary, the atomic operation is split into multiple first sub-operations; based on the sub-addresses carried in the multiple first sub-operations, the first data stored in memory is accessed through the cache of any processing unit. It is readily apparent that by distinguishing the address layout state of the first data to be accessed by the atomic operation using the memory address, and splitting the atomic operation into multiple first sub-operations according to the address layout state, since the atomic operation has been split into multiple first sub-operations, it is only necessary to ensure that the storage space corresponding to the sub-address is not accessed by other processing units when the first sub-operation accesses the sub-address. It is not necessary to lock the entire memory. Furthermore, accessing the first data stored in memory based on the sub-addresses in the multiple sub-operations still ensures the smooth execution of the atomic operation. By avoiding locking the entire memory, the goal of not restricting access to other processing units is achieved, thereby improving the processing efficiency of processing units in a multi-core system. This solves the technical problem of low processing efficiency in multi-core systems caused by improper control of unaligned atomic operations.

[0068] In the above embodiments of this application, accessing the first data stored in memory through the cache of any processing unit based on the sub-address carried in multiple first sub-operations includes: determining the storage state of the first sub-data corresponding to any first sub-operation in the cache based on the sub-address carried in any first sub-operation; reading the first sub-data corresponding to multiple first sub-operations from the cache when the storage state of the first sub-data corresponding to multiple first sub-operations in the cache is a preset state; and combining the first sub-data corresponding to multiple first sub-operations to obtain the first data.

[0069] The first sub-data in the above steps is the data that the first sub-operation needs to obtain from the sub-address it carries.

[0070] The storage state in the above steps is used to characterize the state of the first sub-data in the cache. The storage state can be a preset state or not a preset state.

[0071] The preset states in the above steps are pre-set storage states that can be preset according to actual application conditions. The specific content of the preset states is not limited here. For example, the preset state can be an M (Modified) state, meaning the data in the cache has been modified and is the latest version, but it is not limited to this. It can also be an E (Exclusive) state, an S (Shared) state, an I (Invalid) state, etc.

[0072] In one optional embodiment, taking the preset state as M as an example, the sub-address carried in the first sub-operation is searched in the index table of the cache. If the sub-address is found in the index table, the first sub-data corresponding to the sub-address is determined in the cache. Then, the storage state of the first sub-data in the cache is determined. Specifically, the state flag of the first sub-data can be checked. If the state flag is M, the state of the first sub-data can also be determined to be M.

[0073] When the cache state of the first sub-data corresponding to multiple first sub-operations is M, multiple first sub-data are retrieved from the cache based on the sub-addresses carried in the multiple first sub-operations. The multiple first sub-data are then concatenated according to the order of their sub-addresses to obtain the first data.

[0074] In the above embodiments of this application, when the storage state of the first sub-data corresponding to any first sub-operation in the cache is not a preset state, the method further includes: determining at least one target sub-operation from a plurality of first sub-operations, wherein the storage state of the first sub-data corresponding to at least one target sub-operation in the cache is not a preset state; obtaining the first sub-data corresponding to at least one target sub-operation stored in memory, and storing the first sub-data corresponding to at least one target sub-operation in the cache; updating the storage state of the first sub-data corresponding to at least one target sub-operation in the cache to a preset state; and reading the first sub-data corresponding to a plurality of first sub-operations from the cache.

[0075] In one optional embodiment, taking the preset state as M as an example, if the cached state of the first sub-data corresponding to multiple first sub-operations is not all in the M state, it is necessary to update the first sub-data in the cache that is not in the M state so that all the data in the cache is in the M state, and then perform the operation of reading multiple first sub-data from the cache.

[0076] Specifically, during the update of the first sub-data in the cache that is not in the M state, the target sub-operation is determined based on which first sub-data in the cache is not in the M state. That is, the first sub-operation corresponding to the first sub-data in the cache that is not in the M state is identified as the target sub-operation. Then, the first sub-data corresponding to the target sub-operation is searched and retrieved from memory, and the first sub-data in the cache is replaced with the first sub-data retrieved from memory. In this way, the first sub-data in the cache that was originally not in the M state is modified and is the latest version. Therefore, the storage state can be updated to the M state.

[0077] After the update operation is executed, the cache state of the first sub-data corresponding to multiple first self-operations is M, and the operation of reading the first sub-data corresponding to multiple first self-operations from the cache can be performed.

[0078] In the above embodiments of this application, obtaining the first sub-data corresponding to at least one target sub-operation stored in memory includes: when a target sub-operation is determined from a plurality of first sub-operations, obtaining the first sub-data corresponding to the target sub-operation stored in memory; when a plurality of target sub-operations are determined from a plurality of first sub-operations, sequentially obtaining the first sub-data corresponding to the plurality of target sub-operations stored in memory in ascending order of the sub-addresses corresponding to the plurality of target sub-operations, wherein, after the storage state of the first sub-data corresponding to any target sub-operation in the cache is updated to a preset state, obtaining the first sub-data corresponding to the next target sub-operation stored in memory.

[0079] In an alternative embodiment, when there is only one target sub-operation, the first sub-data corresponding to the target sub-operation can be directly obtained from memory, and then the first sub-data can be updated in the cache.

[0080] In another optional embodiment, when there are only multiple target sub-operations, the acquisition and updating of multiple first sub-data corresponding to multiple target sub-operations can be performed in the following order: the multiple target sub-operations are arranged in ascending order of sub-address; first, the first sub-data of the target sub-operation ranked first is retrieved from memory, and then the first sub-data of the target sub-operation ranked first is updated in the cache; then, the first sub-data of the target sub-operation ranked second is retrieved from memory, and then the first sub-data of the target sub-operation ranked second is updated in the cache, and so on, until the first sub-data of all target sub-operations has been updated.

[0081] In the above embodiments of this application, when determining a target sub-operation from a plurality of first sub-operations, the method further includes: when the sub-address corresponding to the target sub-operation is greater than the sub-address corresponding to other sub-operations, controlling the storage state of the first sub-data corresponding to the other sub-operations in the cache to remain in a preset state, wherein the other sub-operations are used to represent any first sub-operation other than the target sub-operation among the plurality of first sub-operations; when the sub-address corresponding to the target sub-operation is less than the sub-address corresponding to other sub-operations, allowing the storage state of the first sub-data corresponding to the other sub-operations in the cache to be updated to a non-preset state before the storage state of the first sub-data corresponding to the target sub-operation in the cache is updated to the preset state.

[0082] In one optional embodiment, taking the preset state as M as an example, when a target sub-operation is determined from multiple first sub-operations, that is, when only one of the target sub-operations has a first sub-data that is not in the M state, whether to update the first sub-data of other sub-operations in the cache to the M state depends on the size of the sub-address corresponding to the target sub-operation.

[0083] If the sub-address corresponding to the target sub-operation is greater than the sub-address corresponding to other sub-operations, then the first sub-data corresponding to the other sub-operations can remain in the M state.

[0084] If the sub-address corresponding to the target sub-operation is less than the sub-address corresponding to other sub-operations, then before the first sub-data corresponding to the target sub-operation is updated to the M state, the first sub-data corresponding to other sub-operations can be updated to the non-M state first.

[0085] For example, if an atomic operation is split into two first sub-operations, namely A and B, with A having a larger sub-address and B having a smaller sub-address, then if A is in a non-M state and B is in an M state, B will remain in the M state until A is also updated to the M state. If A is in the M state and B is in a non-M state, then A needs to be converted to a non-M state before B is updated to the M state, and A will only be updated to the M state after B is updated to the M state.

[0086] In the above embodiments of this application, the method further includes: performing operations on the first data based on the operation logic corresponding to the atomic operation to obtain the second data; splitting the second data to obtain multiple second sub-data; splitting the atomic operation to obtain the second sub-operations corresponding to the multiple second sub-data; and storing any one of the second sub-data in the cache based on the sub-address carried in the second sub-operation corresponding to any one of the second sub-data.

[0087] The second data in the above steps is obtained by processing the first data using atomic operations, and the second data can be written back to the cache.

[0088] The second sub-data in the above steps is a part of the second data. By splitting the second data into second sub-data, the second data can be written back to the cache in batches.

[0089] The second sub-operation in the above steps can write the second sub-data back to the cache.

[0090] In one optional embodiment, the atomic operation includes three steps: reading data, data manipulation, and writing back data. The first data is the data that the atomic operation needs to read. After reading the data, the first data needs to be processed based on the operation logic corresponding to the atomic operation, which is the data manipulation step. The second data is obtained through data manipulation, and then the step of writing back the second data needs to be performed.

[0091] When writing back the second data, it is split into multiple sub-data items. Simultaneously, the atomic operations are also split, so that each sub-operation corresponds to one sub-data item, resulting in multiple sub-operations. The sub-operations are executed sequentially according to the order of their sub-addresses, ensuring that the multiple sub-data items are stored in the cache sequentially, thus completing the atomic data write-back.

[0092] It should be noted that the above-mentioned splitting of atomic operations refers to splitting the process of writing data back to atomic operations, that is, performing the process of writing data back to atomic operations in multiple steps, rather than splitting the execution process of atomic operations after writing data back.

[0093] In the above embodiments of this application, determining the address layout state of the first data in memory based on the memory address includes: converting the memory address into a physical address when the memory address is a virtual address; and determining the address layout state of the first data in memory based on the physical address, wherein the address layout state is used to characterize whether the physical address crosses the cache line boundary or data page boundary of any processing unit.

[0094] The virtual address mentioned above is an address managed by the operating system that can be directly accessed and used by applications without considering the actual physical memory address. The virtual address space is an abstract address space that can be translated into actual physical addresses using page tables and address mapping techniques.

[0095] In one optional embodiment, address translation can be performed based on the virtual address. Specifically, the page number and offset corresponding to the virtual address are separated, the page table entry corresponding to the page number is searched in the page table of the memory management unit, the physical page frame number corresponding to the page number is obtained, and the physical page frame number and offset are combined to obtain the physical address corresponding to the virtual address.

[0096] Based on the physical address and the size of the first data, determine the start and end addresses of the first data storage. According to the processing unit's manual, determine the addresses corresponding to cache line boundaries and data page boundaries. Based on whether the addresses corresponding to the cache line boundaries or data page boundaries are located between the start and end addresses, determine the address layout state of the first data in memory.

[0097] In the above embodiments of this application, when the address layout state characterizes that the memory address does not cross the cache line boundary and the data page boundary, the method further includes: when the memory address crosses the cache access granularity, splitting the atomic operation to obtain multiple third sub-operations, and accessing the first data stored in memory through the cache of any processing unit based on the sub-address carried in the multiple third sub-operations; when the memory address does not cross the cache access granularity, accessing the first data stored in memory through the cache of any processing unit based on the memory address.

[0098] The third sub-operation in the above steps is an operation obtained by splitting the atomic operation when the memory address crosses the cache access granularity. The third sub-operation can access part of the data in the first data, and the union of the data accessed by all the third sub-operations is the entire first data.

[0099] The cache access granularity in the above steps can characterize how many bits of data a processing unit can read or write from the cache at one time. For example, it can be 64 bits or 128 bits, but is not limited to this.

[0100] In one optional embodiment, when the memory address spans the cache access granularity, the processing unit cannot retrieve all the first data at once during the execution of an atomic operation. In this case, the atomic operation can be split based on the access granularity to obtain multiple third sub-operations. The first data stored in the cache is retrieved based on the sub-address carried in the multiple third sub-operations. For example, if the access granularity is 64 bits, and the first data corresponding to the atomic operation is bytes 4 to 11, that is, bytes 32 to 95, then it needs to be split into two first sub-operations: reading bytes 0 to 7 and reading bytes 8 to 15.

[0101] If the memory address does not cross the cache access granularity, there is no need to split it; you can directly read the first data from the cache based on the memory address.

[0102] The following description uses a preferred embodiment. Figure 4 This is a schematic diagram illustrating how a processing unit in an optional multi-core system accesses storage space according to an embodiment of this application, as shown below. Figure 4As shown, a multi-core system contains multiple processing units: processing unit 0, processing unit 1, ..., processing unit n. All processing units can access the memory in the multi-core system. The following explanation uses the process of processing unit 0 accessing storage space as an example. Memory access instructions from processing units are sent from the problem queue to the load queue and the storage queue. Memory access instructions sent to the load queue are used to load data from storage space, and memory access instructions sent to the storage queue are used to write data into storage space. After the memory access instructions enter the load queue, they need to undergo address translation in the storage queue. The address translation module converts the virtual address accessed by the memory access instruction into a physical address. If it is already a physical address, no translation is needed. During atomic operations, the data required for the atomic operation is loaded from storage space using the memory access instructions in the load queue. At this point, it is determined whether the memory address of the data required for the atomic operation crosses a cache line boundary, a data page boundary, or the cache access granularity. If the memory address of the data required for the atomic operation crosses any one of these boundaries, a request is split. Data is retrieved based on the split requests, and then the data is combined to obtain the data required for the atomic operation. Then, the atomic operation execution unit processes the data required for the atomic operation to obtain the data generated by the atomic operation. The data generated by the atomic operation is written to the storage space through memory access instructions in the storage queue. During the write operation, the data generated by the atomic operation is split, and the write operation is split into requests. Based on the split requests, the split data is written to the data cache separately. It should be noted that when loading data, the memory access instructions in the loading queue first access the data cache. If the data to be loaded by the memory access instruction is in the data cache, it is loaded directly from the data cache; if the data to be loaded is not in the data cache, it is accessed from memory through the bus interface to retrieve the data.

[0103] Figure 5 This is a flowchart of an optional atomic operation for accessing memory according to an embodiment of this application, such as... Figure 5 As shown, when the atomic operation is an unaligned atomic operation, the memory access instruction of the unaligned atomic operation enters the load queue. Address translation is performed on the data required by the unaligned atomic operation, converting the virtual address of the data into a physical address. It is determined whether the data required by the unaligned atomic operation crosses the data cache access granularity. If not, the data cache is accessed directly to obtain the data; if so, the request to obtain the data for the unaligned atomic operation is split, and the data cache is accessed twice to obtain the data.

[0104] When directly accessing the data cache, it's necessary to further determine if the data in the cache is in a modified state. If so, the data required for the unaligned atomic operation can be directly retrieved. Otherwise, memory must be requested first, and the data in the cache updated using the data in memory, making the data in the cache modified. Only then can the data required for the unaligned atomic operation be retrieved. After retrieving the data required for the unaligned atomic operation, the atomic operation is executed, resulting in the data generated by the unaligned atomic operation. Then, the memory access instruction for the unaligned atomic operation enters the storage queue, writing the data generated by the unaligned atomic operation into the data cache.

[0105] When a request to retrieve data in an unaligned atomic operation is split, the request is divided into two, requiring two accesses to the data cache. During the data cache access, it's necessary to determine if the data corresponding to both requests in the cache is in a modified state. If so, the required data can be retrieved directly; otherwise, a memory access request is first made, and the data in the cache is updated using the data in memory to ensure the cached data is in a modified state before retrieving the required data. The data obtained from the two cache accesses is combined to obtain all the data required by the unaligned atomic operation. After retrieving all the data required by the unaligned atomic operation, the atomic operation is executed, resulting in the data generated by the unaligned atomic operation. Then, the memory access instruction for the unaligned atomic operation enters the storage queue, splits the data generated by the unaligned atomic operation, and also splits the data storage request. The split requests are then used to store the split data separately, thus writing all the data generated by the unaligned atomic operation into the data cache.

[0106] Figure 6 This is a flowchart illustrating a method for accessing memory when the address of data corresponding to an optional atomic operation crosses a cache line boundary, according to an embodiment of this application. Figure 6As shown, after the memory access instruction corresponding to the unaligned atomic operation enters the load queue, address translation is performed on the data required by the unaligned atomic operation, converting the virtual address of the data into a physical address. When the address of the data corresponding to the atomic operation crosses the cache line boundary, the request to retrieve data for the unaligned atomic operation is split into two requests, accessing the data cache twice to obtain the data. During the access to the data cache, it is necessary to determine whether the data corresponding to the two requests in the data cache is both in a modified state. If so, the required data can be directly retrieved from the data cache; otherwise, memory must be requested first, and the data in the data cache must be updated using the data in memory to ensure the data in the data cache is in a modified state before retrieving the required data from the data cache. The data obtained from the two accesses to the data cache are combined to obtain all the data required by the unaligned atomic operation. After obtaining all the data required by the unaligned atomic operation, the atomic operation is executed, resulting in the data generated by the unaligned atomic operation. Then, the memory access instruction of the unaligned atomic operation enters the storage queue, splits the data generated by the unaligned atomic operation, and also splits the data storage request. The split requests are used to store the split data separately, thus writing all the data generated by the unaligned atomic operation into the data cache.

[0107] Figure 7 This is a schematic diagram illustrating the correspondence between an optional atomic operation and a virtual data page and cache line according to an embodiment of this application, as shown below. Figure 7 As shown, virtual data page 0 and virtual data page 2 correspond to the same physical data page. Therefore, the cache lines in virtual data page 0 and virtual data page 2 are cache line 0 and cache line 1, respectively, and the physical address of cache line 0 is less than the physical address of cache line 1. The cache lines in virtual data page 1 are cache line 2 and cache line 3, and the physical address of cache line 2 is less than the physical address of cache line 3. The physical address of virtual data page 1 is smaller, meaning it is less than the physical address of virtual data page 0, while the physical address of virtual data page 0 is equal to the physical address of virtual data page 2. Atomic operations 0, 1, 2, and 3 are issued by processing unit 0, processing unit 1, processing unit 2, and processing unit 3, respectively. In this process, atomic operation 0 requires data located within virtual data page 0, specifically in cache line 0 and cache line 1; atomic operation 1 requires data located in cache line 1 of virtual data page 0 and cache line 2 of virtual data page 1, crossing the boundary of the virtual data page; atomic operation 2 requires data located within virtual data page 1, specifically in cache line 2 and cache line 3; and atomic operation 3 requires data located in cache line 3 of virtual data page 1 and cache line 0 of virtual data page 2, crossing the boundary of the virtual data page. When retrieving data, the rule of requesting the smaller physical address should be followed. Therefore, the order in which the processing unit requests cache lines is as follows:

[0108] Atomic operation 0 does not cross pages. According to the address size of the cache line, processing unit 0 first requests cache line 0, and then requests cache line 1.

[0109] Atomic operation 1 spans pages. According to the physical address size of the virtual data page, processing unit 1 first requests cache line 2, and then requests cache line 1.

[0110] Atomic operation 2 does not cross pages. According to the address size of the cache line, processing unit 2 first requests cache line 2, and then requests cache line 3.

[0111] Atomic operation 3 spans pages. Based on the physical address size of the virtual data page, processing unit 3 first requests cache line 3, and then requests cache line 0.

[0112] In this scenario, no deadlock occurs, and there is always a processing unit that can access both cache lines simultaneously.

[0113] The scheme proposed in this application allows other processing units to access memory regions outside the cache lines locked by atomic operations, thereby improving the execution efficiency of multi-core systems. By performing unaligned atomic operations within the cache of processing units, atomic operations across cache lines are supported, ensuring high execution speed and low hardware complexity, with minimal impact on system execution speed and guaranteeing system processing efficiency.

[0114] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of the relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation portals are provided for users to choose to authorize or refuse.

[0115] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0116] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, they can also be implemented by hardware. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several computer instructions to cause the processing unit to execute the methods described in the various embodiments of this application.

[0117] Example 2

[0118] According to embodiments of this application, a plurality of systems for implementing the above-described memory access method are also provided. Figure 8 This is a schematic diagram of a multi-core system according to an embodiment of this application, such as... Figure 8 As shown, the device includes:

[0119] 80 MB of memory is used for data storage;

[0120] Multiple processing units 82 are used to connect to memory. Each processing unit includes a cache for data interaction with memory, and each processing unit is used to execute the memory access method described above.

[0121] The memory in the above steps can be accessed by multiple processing units so that multiple processing units can retrieve data from memory or store data in memory.

[0122] The cache in the above steps can be accessed in atomic operations so that the atomic operation can retrieve the first data from the cache or store the second data in the cache. When an atomic operation of one of the processing units operates on a cache line in the cache, the cache line is locked by the atomic operation, but other cache lines in the cache and memory can still be accessed by other processing units.

[0123] In the above embodiments of this application, any processing unit further includes: a loading queue, connected to a cache, for storing atomic operations, multiple first sub-operations, first sub-data corresponding to the multiple first sub-operations, and first data; an execution unit, connected to the loading queue, for performing operations on the first data based on the operation logic corresponding to the atomic operations to obtain second data; and a storage queue, connected to the execution unit, for storing second data, multiple second sub-data, and sub-operations corresponding to the multiple second sub-data.

[0124] The queue used in the above steps is the atomic operation that retrieves the required data from the cache when loading the queue, and the queue used when storing the second data after the atomic operation generates the second data.

[0125] In the above embodiments of this application, the address translation unit, connected to the load queue and the storage queue, is used to translate the memory address into a physical address when the memory address is a virtual address.

[0126] It should be noted that the preferred implementation schemes involved in the above embodiments of this application are the same as the schemes, application scenarios and implementation processes provided in Embodiment 1, but are not limited to the schemes provided in Embodiment 1.

[0127] Example 3

[0128] Embodiments of this application may provide a processor, including: multiple processing units, any one of which is used to execute the memory access method in Embodiment 1 above.

[0129] Example 4

[0130] Embodiments of this application may provide a system-on-a-chip, including: memory and the processor in embodiment 3 above.

[0131] Example 5

[0132] Embodiments of this application may provide a computing device, which may be any one of a group of computing devices. Optionally, in this embodiment, the computing device may also be replaced by a terminal device such as a mobile terminal.

[0133] Optionally, in this embodiment, the computing device described above may be located in at least one of a plurality of network devices in a computer network.

[0134] In this embodiment, the computing device described above can execute the program code in the method.

[0135] Optionally, Figure 9 This is a structural block diagram of a computing device according to an embodiment of this application. Figure 9 As shown, the electronic device A may include: one or more (only one is shown in the figure) processors 902, memory 904, and bus 906, wherein the bus is connected to the radio frequency module, audio module and access device.

[0136] The memory can be used to store software programs and modules, such as the program instructions / modules corresponding to the methods and apparatus in the embodiments of this application. The processor executes various functional applications and data processing by running the software programs and modules stored in the memory, thereby implementing the methods in the above embodiments. The memory may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory may further include memory remotely located relative to the processor, and these remote memories can be connected to terminal A via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0137] The processor can invoke information and application programs stored in memory via a transmission device to perform the following steps: In response to a received atomic operation, determine the memory address carried in the atomic operation, wherein the memory address is used to characterize the address in memory where the first data to be accessed by the atomic operation is stored; Based on the memory address, determine the address layout state of the first data in memory, wherein the address layout state is used to characterize whether the memory address crosses the cache line boundary or data page boundary of any processing unit; If the address layout state characterizes that the memory address crosses the cache line boundary or data page boundary, split the atomic operation into multiple first sub-operations, wherein the sub-addresses carried in the different first sub-operations are different; Based on the sub-addresses carried in the multiple first sub-operations, access the first data stored in memory through the cache of any processing unit.

[0138] Optionally, the processor may also execute program code with the following steps: accessing the first data stored in memory through the cache of any one processing unit based on the sub-address carried in multiple first sub-operations, including: determining the storage state of the first sub-data corresponding to any one first sub-operation in the cache based on the sub-address carried in any one first sub-operation; reading the first sub-data corresponding to multiple first sub-operations from the cache when the storage state of the first sub-data corresponding to multiple first sub-operations in the cache is a preset state; and combining the first sub-data corresponding to multiple first sub-operations to obtain the first data.

[0139] Optionally, the processor may also execute program code with the following steps: when the storage state of the first sub-data corresponding to any first sub-operation in the cache is not a preset state, the method further includes: determining at least one target sub-operation from multiple first sub-operations, wherein the storage state of the first sub-data corresponding to at least one target sub-operation in the cache is not a preset state; obtaining the first sub-data corresponding to at least one target sub-operation stored in memory, and storing the first sub-data corresponding to at least one target sub-operation in the cache; updating the storage state of the first sub-data corresponding to at least one target sub-operation in the cache to a preset state; and reading the first sub-data corresponding to multiple first sub-operations from the cache.

[0140] Optionally, the processor may also execute program code with the following steps: obtaining first sub-data corresponding to at least one target sub-operation stored in memory, including: when a target sub-operation is determined from multiple first sub-operations, obtaining the first sub-data corresponding to the target sub-operation stored in memory; when multiple target sub-operations are determined from multiple first sub-operations, sequentially obtaining the first sub-data corresponding to the multiple target sub-operations stored in memory in ascending order of the sub-addresses corresponding to the multiple target sub-operations, wherein, after the storage state of the first sub-data corresponding to any target sub-operation in the cache is updated to a preset state, obtaining the first sub-data corresponding to the next target sub-operation stored in memory.

[0141] Optionally, the processor may also execute program code with the following steps: when determining a target sub-operation from multiple first sub-operations, the method further includes: when the sub-address corresponding to the target sub-operation is greater than the sub-address corresponding to other sub-operations, controlling the storage state of the first sub-data corresponding to the other sub-operations in the cache to remain in a preset state, wherein the other sub-operations are used to represent any first sub-operation other than the target sub-operation among the multiple first sub-operations; when the sub-address corresponding to the target sub-operation is less than the sub-address corresponding to other sub-operations, allowing the storage state of the first sub-data corresponding to the other sub-operations in the cache to be updated to a non-preset state before the storage state of the first sub-data corresponding to the target sub-operation in the cache is updated to the preset state.

[0142] Optionally, the processor may also execute program code with the following steps: The method further includes: operating on the first data based on the operation logic corresponding to the atomic operation to obtain the second data; splitting the second data to obtain multiple second sub-data; splitting the atomic operation to obtain the second sub-operations corresponding to the multiple second sub-data; and storing any second sub-data in the cache based on the sub-address carried in the second sub-operation corresponding to any second sub-data.

[0143] Optionally, the processor may also execute program code that performs the following steps: determining the address layout state of the first data in memory based on the memory address, including: converting the memory address to a physical address if the memory address is a virtual address; determining the address layout state of the first data in memory based on the physical address, wherein the address layout state is used to characterize whether the physical address crosses the cache line boundary or data page boundary of any processing unit.

[0144] Optionally, the processor may also execute program code with the following steps: when the address layout state characterizes the memory address as not crossing cache line boundaries and data page boundaries, the method further includes: when the memory address crosses the cache access granularity, splitting the atomic operation to obtain multiple third sub-operations, and accessing the first data stored in memory through the cache of any processing unit based on the sub-address carried in the multiple third sub-operations; when the memory address does not cross the cache access granularity, accessing the first data stored in memory through the cache of any processing unit based on the memory address.

[0145] In this embodiment, in response to a received atomic operation, the memory address carried in the atomic operation is determined; based on the memory address, the address layout state of the first data in memory is determined; when the address layout state indicates that the memory address crosses a cache line boundary or a data page boundary, the atomic operation is split into multiple first sub-operations; based on the sub-addresses carried in the multiple first sub-operations, the first data stored in memory is accessed through the cache of any processing unit. It is readily apparent that by distinguishing the address layout state of the first data to be accessed by the atomic operation using the memory address, and splitting the atomic operation into multiple first sub-operations according to the address layout state, since the atomic operation has been split into multiple first sub-operations, it is only necessary to ensure that the storage space corresponding to the sub-address is not accessed by other processing units when the first sub-operation accesses the sub-address. It is not necessary to lock the entire memory. Furthermore, accessing the first data stored in memory based on the sub-addresses in the multiple sub-operations still ensures the smooth execution of the atomic operation. By avoiding locking the entire memory, the goal of not restricting access to other processing units is achieved, thereby improving the processing efficiency of processing units in a multi-core system. This solves the technical problem of low processing efficiency in multi-core systems caused by improper control of unaligned atomic operations.

[0146] Those skilled in the art will understand that the structure shown in the figure is merely illustrative and does not limit the structure of the computing device described above. For example, computing device A may include more or fewer components (such as network interfaces, display devices, etc.) than shown in the figure, or have a different configuration than shown in the figure.

[0147] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing the hardware related to the terminal device. The program can be stored in a computer-readable storage medium, which may include: flash drive, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0148] Example 6

[0149] Embodiments of this application also provide a computer-readable storage medium. Optionally, in this embodiment, the computer-readable storage medium can be used to store program code executed by the method provided in the above embodiments.

[0150] Optionally, in this embodiment, the storage medium may be located in any one of the electronic devices in the group of electronic devices in the computer network, or in any one of the mobile terminals in the group of mobile terminals.

[0151] Optionally, in this embodiment, the computer-readable storage medium is configured to store program code for performing the following steps: in response to a received atomic operation, determining the memory address carried in the atomic operation, wherein the memory address is used to characterize the address in memory where the first data to be accessed by the atomic operation is stored; based on the memory address, determining the address layout state of the first data in memory, wherein the address layout state is used to characterize whether the memory address crosses the cache line boundary or data page boundary of any processing unit; if the address layout state characterizes that the memory address crosses the cache line boundary or data page boundary, splitting the atomic operation into multiple first sub-operations, wherein the sub-addresses carried in the different first sub-operations are different; based on the sub-addresses carried in the multiple first sub-operations, accessing the first data stored in memory through the cache of any processing unit.

[0152] Optionally, the computer-readable storage medium is further configured to store program code for performing the following steps: accessing the first data stored in memory through the cache of any one processing unit based on the sub-address carried in a plurality of first sub-operations, including: determining the storage state of the first sub-data corresponding to any one of the first sub-operations in the cache based on the sub-address carried in any one of the first sub-operations; reading the first sub-data corresponding to the plurality of first sub-operations from the cache when the storage state of the first sub-data corresponding to the plurality of first sub-operations in the cache is a preset state; and combining the first sub-data corresponding to the plurality of first sub-operations to obtain the first data.

[0153] Optionally, the computer-readable storage medium is further configured to store program code for performing the following steps: when the storage state of the first sub-data corresponding to any first sub-operation in the cache is not a preset state, the method further includes: determining at least one target sub-operation from a plurality of first sub-operations, wherein the storage state of the first sub-data corresponding to the at least one target sub-operation in the cache is not a preset state; acquiring the first sub-data corresponding to the at least one target sub-operation stored in memory, and storing the first sub-data corresponding to the at least one target sub-operation in the cache; updating the storage state of the first sub-data corresponding to the at least one target sub-operation in the cache to a preset state; and reading the first sub-data corresponding to the plurality of first sub-operations from the cache.

[0154] Optionally, the computer-readable storage medium is further configured to store program code for performing the following steps: obtaining first sub-data corresponding to at least one target sub-operation stored in memory, including: if a target sub-operation is determined from a plurality of first sub-operations, obtaining the first sub-data corresponding to the target sub-operation stored in memory; if a plurality of target sub-operations are determined from a plurality of first sub-operations, sequentially obtaining the first sub-data corresponding to the plurality of target sub-operations stored in memory in ascending order of the sub-addresses corresponding to the plurality of target sub-operations, wherein, after the storage state of the first sub-data corresponding to any one target sub-operation in the cache is updated to a preset state, obtaining the first sub-data corresponding to the next target sub-operation stored in memory.

[0155] Optionally, the computer-readable storage medium is further configured to store program code for performing the following steps: when determining a target sub-operation from a plurality of first sub-operations, the method further includes: when the sub-address corresponding to the target sub-operation is greater than the sub-address corresponding to other sub-operations, controlling the storage state of the first sub-data corresponding to the other sub-operations in the cache to remain in a preset state, wherein the other sub-operations are used to represent any first sub-operation other than the target sub-operation among the plurality of first sub-operations; when the sub-address corresponding to the target sub-operation is less than the sub-address corresponding to other sub-operations, allowing the storage state of the first sub-data corresponding to the other sub-operations in the cache to be updated to a non-preset state before the storage state of the first sub-data corresponding to the target sub-operation in the cache is updated to the preset state.

[0156] Optionally, the computer-readable storage medium is further configured to store program code for performing the following steps: the method further includes: operating on the first data based on the operation logic corresponding to the atomic operation to obtain the second data; splitting the second data to obtain multiple second sub-data; splitting the atomic operation to obtain the second sub-operations corresponding to the multiple second sub-data; and storing any one of the second sub-data in a cache based on the sub-address carried in the second sub-operation corresponding to any one of the second sub-data.

[0157] Optionally, the computer-readable storage medium is further configured to store program code for performing the following steps: determining the address layout state of first data in memory based on a memory address, including: converting the memory address to a physical address if the memory address is a virtual address; determining the address layout state of the first data in memory based on the physical address, wherein the address layout state is used to characterize whether the physical address crosses the cache line boundary or data page boundary of any processing unit.

[0158] Optionally, the computer-readable storage medium is further configured to store program code for performing the following steps: when the address layout state characterizes that the memory address does not cross cache line boundaries and data page boundaries, the method further includes: when the memory address crosses the cache access granularity, splitting the atomic operation into multiple third sub-operations, and accessing the first data stored in memory through the cache of any processing unit based on the sub-addresses carried in the multiple third sub-operations; and when the memory address does not cross the cache access granularity, accessing the first data stored in memory through the cache of any processing unit based on the memory address.

[0159] Example 7

[0160] Embodiments of this application also provide a computer program product. Optionally, in this embodiment, the computer program product may include a computer program that, when executed by a processor, implements the methods provided in the embodiments described above.

[0161] Example 8

[0162] Embodiments of this application also provide a computer program product. Optionally, the computer program product may include a non-volatile computer-readable storage medium, which can be used to store a computer program that, when executed by a processor, implements the method provided in the above embodiments.

[0163] Example 9

[0164] Embodiments of this application also provide a computer program. Optionally, in this embodiment, when the computer program is executed by a processor, it implements the method provided in the above embodiments.

[0165] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0166] In the above embodiments of this application, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0167] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling, direct coupling, or communication connection may be through some interfaces; the indirect coupling or communication connection between units or modules may be electrical or other forms.

[0168] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0169] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0170] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard drive, magnetic disk, or optical disk.

[0171] The above description is only a preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A memory access method, characterized in that, The method is applied to any processing unit in a multi-core system, wherein the multi-core system includes at least: multiple processing units and memory, and the method includes: In response to a received atomic operation, a memory address carried in the atomic operation is determined, wherein the memory address is used to characterize the address in memory where the first data to be accessed by the atomic operation is stored; Based on the memory address, the address layout state of the first data in the memory is determined, wherein the address layout state is used to characterize whether the memory address crosses the cache line boundary or data page boundary of any of the processing units; When the address layout state indicates that the memory address crosses the cache line boundary or the data page boundary, the atomic operation is split into multiple first sub-operations, wherein the sub-addresses carried in different first sub-operations are different. Based on the sub-address carried in the plurality of first sub-operations, the first data stored in memory is accessed through the cache of any of the processing units.

2. The method according to claim 1, characterized in that, The step of accessing the first data stored in memory through the cache of any one of the processing units based on the sub-address carried in the plurality of first sub-operations includes: Based on the sub-address carried in any first sub-operation, determine the storage state of the first sub-data corresponding to any first sub-operation in the cache; If the storage state of the first sub-data corresponding to the plurality of first sub-operations in the cache is a preset state, the first sub-data corresponding to the plurality of first sub-operations is read from the cache. The first data is obtained by combining the first sub-data corresponding to the plurality of first sub-operations.

3. The method according to claim 2, characterized in that, If the storage state of the first sub-data corresponding to any first sub-operation in the cache is not the preset state, the method further includes: At least one target sub-operation is determined from the plurality of first sub-operations, wherein the storage state of the first sub-data corresponding to the at least one target sub-operation in the cache is not the preset state; Obtain the first sub-data corresponding to the at least one target sub-operation stored in the memory, and store the first sub-data corresponding to the at least one target sub-operation in the cache; Update the storage state of the first sub-data corresponding to the at least one target sub-operation in the cache to the preset state; Read the first sub-data corresponding to the plurality of first sub-operations from the cache.

4. The method according to claim 3, characterized in that, The step of obtaining the first sub-data corresponding to the at least one target sub-operation stored in the memory includes: If a target sub-operation is determined from the plurality of first sub-operations, the first sub-data corresponding to the target sub-operation stored in memory is obtained; When multiple target sub-operations are determined from the multiple first sub-operations, the first sub-data corresponding to the multiple target sub-operations stored in the memory are sequentially obtained in ascending order of the sub-addresses corresponding to the multiple target sub-operations. After the storage state of the first sub-data corresponding to any target sub-operation in the cache is updated to the preset state, the first sub-data corresponding to the next target sub-operation stored in the memory is obtained.

5. The method according to claim 3, characterized in that, When determining a target sub-operation from the plurality of first sub-operations, the method further includes: When the sub-address corresponding to the target sub-operation is greater than the sub-address corresponding to other sub-operations, the storage state of the first sub-data corresponding to the other sub-operations in the cache is controlled to remain in the preset state, wherein the other sub-operations are used to represent any one of the multiple first sub-operations other than the target sub-operation; If the sub-address corresponding to the target sub-operation is less than the sub-address corresponding to the other sub-operations, before the storage state of the first sub-data corresponding to the target sub-operation in the cache is updated to the preset state, it is allowed to update the storage state of the first sub-data corresponding to the other sub-operations in the cache to a state other than the preset state.

6. The method according to any one of claims 1 to 5, characterized in that, The method further includes: Based on the operation logic corresponding to the atomic operation, the first data is operated on to obtain the second data; The second data is split into multiple second sub-data; The atomic operation is broken down to obtain the second sub-operations corresponding to the plurality of second sub-data; Based on the sub-address carried in the second sub-operation corresponding to any second sub-data, the arbitrary second sub-data is stored in the cache.

7. The method according to any one of claims 1 to 5, characterized in that, Determining the address layout state of the first data in memory based on the memory address includes: If the memory address is a virtual address, the memory address is translated into a physical address; Based on the physical address, the address layout state of the first data in the memory is determined, wherein the address layout state is used to characterize whether the physical address crosses the cache line boundary or data page boundary of any of the processing units.

8. The method according to any one of claims 1 to 5, characterized in that, When the address layout state indicates that the memory address does not cross the cache line boundary and the data page boundary, the method further includes: When the memory address spans the access granularity of the cache, the atomic operation is split into multiple third sub-operations. Based on the sub-addresses carried in the multiple third sub-operations, the first data stored in the memory is accessed through the cache of any one of the processing units. If the memory address does not cross the access granularity of the cache, the first data stored in the memory is accessed through the cache of any one of the processing units based on the memory address.

9. A multi-core system, characterized in that, include: Memory is used to store data; Multiple processing units are connected to the memory, each processing unit includes a cache for data interaction with the memory, and each processing unit is used to execute the memory access method according to any one of claims 1 to 8.

10. The multi-core system according to claim 9, characterized in that, Each of the processing units further includes: A loading queue, connected to the cache, is used to store the atomic operation, the plurality of first sub-operations, the first sub-data corresponding to the plurality of first sub-operations, and the first data; An execution unit, connected to the loading queue, is used to operate on the first data based on the operation logic corresponding to the atomic operation to obtain the second data. A storage queue, connected to the execution unit, is used to store the second data, multiple second sub-data, and sub-operations corresponding to the multiple second sub-data.

11. The multi-core system according to claim 10, characterized in that, Each of the processing units further includes: The address translation unit, connected to the load queue and the storage queue, is used to translate the memory address into a physical address when the memory address is a virtual address.

12. A processor, characterized in that, include: Multiple processing units, any one of which is used to execute the method described in any one of claims 1 to 11.

13. A system-on-a-chip, characterized in that, include: The memory and the processor as described in claim 12.

14. A computing device, characterized in that, include: Memory; Memory, which stores executable programs; A processor for running the program, wherein the processor includes a plurality of processing units, and the program, when executed by any one of the processing units, implements the method according to any one of claims 1 to 8.

15. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a stored executable program, wherein the executable program, when executed by a processor, implements the method according to any one of claims 1 to 8.

16. A computer program product, characterized in that, Includes computer instructions that, when executed by a processor, implement the method according to any one of claims 1 to 8.

Images