Chip verification method, system, device, readable storage medium and program product

Abstract

This application relates to a chip verification method, apparatus, computer device, computer-readable storage medium, and computer program product. The method includes: configuring a dynamic storage structure accessible via a handle in a global control unit of the verification environment; an excitation generator, while driving a transaction request to the module under test (DUT), writing the page table entry corresponding to the transaction into the dynamic storage structure; a reference model receiving the transaction request and performing a cache matching test; when a missing state is determined, sampling the internal state signal of the DUT and entering a blocking waiting state until timing synchronization with the DUT is completed; finally, the reference model obtaining the page table entry from the dynamic storage structure and calculating the expected result, comparing it with the DUT. This invention solves the stability and completeness problems of the model under complex random states through a blocking sampling mechanism of a cacheless reference model, improving the verification efficiency and coverage of the translation cache unit.

Description

Technical Field

[0001] This application relates to the field of integrated circuit verification technology, specifically to a chip verification method, system, computer equipment, computer-readable storage medium, and computer program product. Background Technology

[0002] During chip design, chip verification is crucial to ensure the correctness of the design. This ensures that the manufactured chip meets the design objectives and expected functions in subsequent chip production stages. The System Memory Management Unit (SMMU) is the core component that implements address translation between peripherals and main memory. The Translation Buffer Unit (TBU), as the front-end core module of the SMMU, directly determines the reliability of system memory access based on its logical correctness. Therefore, functional verification of the TBU is of paramount importance.

[0003] When using white-box verification strategies to functionally verify a TBU, it is typically necessary to build a reference model (RM) to simulate hardware behavior, and then compare the output of the reference model with the output of the Design Under Test (DUT) on a scoreboard (SCB). Existing white-box verification methods often suffer from the following problems:

[0004] Because the TBU integrates multiple state machines and caches, its internal states during runtime exhibit strong randomness. If the reference model completely replicates these hardware-level functional modules, it will lead to a significant decrease in the stability of the reference model itself. However, to ensure the stability of the reference model, current technologies generally adopt an oversimplified design scheme, only performing page table lookup tasks. Ultimately, this results in the reference model failing to cover the core verification scenarios of the TBU and making it difficult to meet the completeness requirements of unit testing.

[0005] Furthermore, when performing page table lookup tasks, the reference model typically needs to access the page table at the top level of the verification test case via pointers, but this page table cannot flexibly configure various attributes. If there are many page tables that need to be configured, centralized management is impossible. Moreover, the process of dynamically updating the page table is lengthy and prone to timing delays, resulting in the page table state of the module under test being out of sync with that of the reference model. Summary of the Invention

[0006] Based on this, it is necessary to provide a chip verification method, apparatus, computer equipment, computer-readable storage medium, and computer program product for synchronizing a reference model with TBU blocking, in order to address the above-mentioned technical problems.

[0007] Firstly, this application provides a chip verification method, including:

[0008] Configure a dynamic storage structure in the global control unit of the verification environment, and establish an access handle pointing to the dynamic storage structure;

[0009] A transaction request is generated using an excitation generator, the transaction request is sent to the module under test, and the write method is called synchronously to fill the page table entry corresponding to the transaction request into the dynamic storage structure.

[0010] The transaction request is synchronously sent to the reference model, the reference model is used to calculate the index identifier based on the virtual address in the transaction request, and the tag field of the virtual address is matched with the tag field in the cache line corresponding to the index identifier in the reference model for matching test;

[0011] The state synchronization of the internal cache replacement logic of the reference model is performed according to the matching test result. When the matching test result is determined to be in a missing state, the reference model is triggered to enter a blocking waiting state until the cache replacement bit of the module under test is detected to be updated and then the blocking is released. The state synchronization is completed using the updated cache replacement bit.

[0012] Using the reference model, the page table entry corresponding to the transaction request is obtained from the dynamic storage structure through the access handle, and the expected output result of address translation is calculated based on the page table entry;

[0013] The expected output result is compared with the output result of the module under test.

[0014] In one embodiment, the dynamic storage structure is an associative array; the associative array is configured with a write method and a read method, the write method being invoked when the stimulus generator drives a transaction request to populate a single page table entry, and the read method being invoked by the reference model to read without changing the contents of the associative array.

[0015] In one embodiment, before calculating the index identifier based on the virtual address in the transaction request using the reference model, the method further includes:

[0016] Determine whether the virtual address of the transaction request is within a preset bypass address range;

[0017] If so, it is determined to be in a bypass state, the virtual address is output as the physical address, and the subsequent processing of the transaction request in the reference model is terminated.

[0018] In one embodiment, the method further includes a multi-level process comparison step:

[0019] During the process of the reference model processing the transaction request, the determination of the bypass state, the missing state, and the acquisition of the page table entry corresponding to the transaction request are key verification nodes.

[0020] At each of the key verification nodes, the intermediate state data generated by the reference model is compared with the real-time state data of the module under test at the corresponding node.

[0021] If the comparison results of any of the key verification nodes are inconsistent, an error report will be output and the running log of the current simulation moment will be recorded.

[0022] In one embodiment, the state synchronization of executing the internal cache replacement logic of the reference model based on the matching test result includes:

[0023] If the matching test result is determined to be a hit, the reference model is used to update its own cache replacement priority state according to the cache line position of this hit;

[0024] If the matching test result is determined to be in a missing state, after the blocking waiting state is lifted, the reference model synchronously updates its own cache replacement priority state based on the updated cache replacement bit of the module under test, so as to maintain the same cache line replacement order as the module under test.

[0025] In one embodiment, triggering the reference model to enter a blocked waiting state until the cache replacement bit of the module under test is updated is detected and the blocking is lifted includes:

[0026] When the result of the matching test is the missing state, the processing of the reference model is suspended to enter the blocked waiting state;

[0027] Monitor the cache replacement bit status of the module under test;

[0028] When the cache replacement bit undergoes a state transition, and at least one valid bit exists in the cache replacement bit after the transition, the unblocking condition is determined to be met.

[0029] Resume the processing of the reference model and return the cache replacement bit of the module under test at the current moment as the monitoring result.

[0030] Secondly, this application also provides a chip verification method system, including:

[0031] A global control module is used to configure a dynamic storage structure in the global control unit of the verification environment and to establish an access handle pointing to the dynamic storage structure.

[0032] The stimulus generation module, connected to the module under test and the global control module, is used to generate a transaction request and send the transaction request to the module under test, and synchronously call the write method to fill the page table entry corresponding to the transaction request into the dynamic storage structure.

[0033] The reference model module, connected to the global control module, is used to receive the transaction request, calculate an index identifier based on the virtual address of the transaction request, and perform a matching test between the tag field of the virtual address and the tag field in the cache line corresponding to the index identifier in the reference model.

[0034] When the matching test result is determined to be in a missing state, the state synchronization of the internal cache replacement logic of the reference model is executed according to the matching test result. Specifically, when the matching test result is determined to be in a missing state, the reference model is triggered to enter a blocking waiting state until the cache replacement bit of the module under test is detected to be updated, and then the blocking is released. The updated cache replacement bit is used to complete the state synchronization.

[0035] Using the reference model, the page table entry corresponding to the transaction request is obtained from the dynamic storage structure through the access handle, and the expected output result of address translation is calculated based on the page table entry;

[0036] The scoring board module, connected to the reference model module and the module under test, is used to compare the expected output result with the output result of the module under test.

[0037] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the following steps:

[0038] Configure a dynamic storage structure in the global control unit of the verification environment, and establish an access handle pointing to the dynamic storage structure;

[0039] A transaction request is generated using an excitation generator, the transaction request is sent to the module under test, and the write method is called synchronously to fill the page table entry corresponding to the transaction request into the dynamic storage structure.

[0040] The transaction request is synchronously sent to the reference model, the reference model is used to calculate the index identifier based on the virtual address in the transaction request, and the tag field of the virtual address is matched with the tag field in the cache line corresponding to the index identifier in the reference model for matching test;

[0041] The state synchronization of the internal cache replacement logic of the reference model is performed according to the matching test result. When the matching test result is determined to be in a missing state, the reference model is triggered to enter a blocking waiting state until the cache replacement bit of the module under test is detected to be updated and then the blocking is released. The state synchronization is completed using the updated cache replacement bit.

[0042] Using the reference model, the page table entry corresponding to the transaction request is obtained from the dynamic storage structure through the access handle, and the expected output result of address translation is calculated based on the page table entry;

[0043] The expected output result is compared with the output result of the module under test.

[0044] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, performs the following steps:

[0045] Configure a dynamic storage structure in the global control unit of the verification environment, and establish an access handle pointing to the dynamic storage structure;

[0046] A transaction request is generated using an excitation generator, the transaction request is sent to the module under test, and the write method is called synchronously to fill the page table entry corresponding to the transaction request into the dynamic storage structure.

[0047] The transaction request is synchronously sent to the reference model, the reference model is used to calculate the index identifier based on the virtual address in the transaction request, and the tag field of the virtual address is matched with the tag field in the cache line corresponding to the index identifier in the reference model for matching test;

[0048] The state synchronization of the internal cache replacement logic of the reference model is performed according to the matching test result. When the matching test result is determined to be in a missing state, the reference model is triggered to enter a blocking waiting state until the cache replacement bit of the module under test is detected to be updated and then the blocking is released. The state synchronization is completed using the updated cache replacement bit.

[0049] Using the reference model, the page table entry corresponding to the transaction request is obtained from the dynamic storage structure through the access handle, and the expected output result of address translation is calculated based on the page table entry;

[0050] The expected output result is compared with the output result of the module under test.

[0051] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, performs the following steps:

[0052] Configure a dynamic storage structure in the global control unit of the verification environment, and establish an access handle pointing to the dynamic storage structure;

[0053] A transaction request is generated using an excitation generator, the transaction request is sent to the module under test, and the write method is called synchronously to fill the page table entry corresponding to the transaction request into the dynamic storage structure.

[0054] The transaction request is synchronously sent to the reference model, the reference model is used to calculate the index identifier based on the virtual address in the transaction request, and the tag field of the virtual address is matched with the tag field in the cache line corresponding to the index identifier in the reference model for matching test;

[0055] The state synchronization of the internal cache replacement logic of the reference model is performed according to the matching test result. When the matching test result is determined to be in a missing state, the reference model is triggered to enter a blocking waiting state until the cache replacement bit of the module under test is detected to be updated and then the blocking is released. The state synchronization is completed using the updated cache replacement bit.

[0056] Using the reference model, the page table entry corresponding to the transaction request is obtained from the dynamic storage structure through the access handle, and the expected output result of address translation is calculated based on the page table entry;

[0057] The expected output result is compared with the output result of the module under test.

[0058] The aforementioned chip verification method, apparatus, computer equipment, computer-readable storage medium, and computer program product utilize an optimized reference model verification architecture design, coupled with a sampling blocking mechanism for missing states. The reference model eliminates the need for internally maintaining complex instruction queues or mirrored state machines. Instead, it achieves timing synchronization with the module under test (DUT) by sampling the DUT's internal state signals in real time and employing blocking and waiting. This significantly reduces the development difficulty and operational risk of the reference model, ensuring its stability. Simultaneously, by sampling real hardware states, the model can accurately simulate the behavior of the TBU in complex scenarios such as missing page table entries, thus achieving complete coverage of the core TBU verification scenarios.

[0059] Furthermore, this invention configures a dynamic storage structure (such as an associative array) accessible via handles in the global control unit, and this structure is synchronously populated by the stimulus generator while driving transactions. On the one hand, this allows page table configuration items to be flexibly passed and centrally managed via handles, supporting on-demand dynamic allocation of massive page table entries and saving memory resources. On the other hand, since page table population and transaction driving are triggered synchronously at the stimulus end, and the reference model directly shares access to the same data object, the page table state delay between the module under test and the reference model is completely eliminated, ensuring data consistency between the two at any simulation moment and avoiding false errors caused by data asynchrony. Attached Figure Description

[0060] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0061] Figure 1 This is a flowchart illustrating a chip verification method in one embodiment;

[0062] Figure 2 This is a flowchart illustrating a reference model in one embodiment;

[0063] Figure 3 This is a flowchart illustrating the reference model in another embodiment;

[0064] Figure 4 This is a structural block diagram of a chip verification device in one embodiment;

[0065] Figure 5 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0066] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0067] It should be noted that when one element is considered to be "connected" to another element, it can be directly connected to the other element or connected to the other element through an intermediary element. Furthermore, in the following embodiments, "connection" should be understood as "electrical connection," "communication connection," etc., if there is an exchange of electrical signals or data between the connected objects.

[0068] The Translation Buffer Unit (TBU) is one of the core sub-modules of the Memory Management Unit (MMU) that enables fast translation of virtual addresses to physical addresses. Its core function is to store page table information that may be frequently accessed, so as to optimize transaction processing and improve the address translation efficiency when accessing memory.

[0069] In general-purpose graphics processing unit (GPU) systems, the Translation Unit (TBU) often works in conjunction with a Translation Control Unit (TCU) module. Multiple TBUs are connected to a single TCU via synchronous or asynchronous bridges. These modules together form a System Memory Management Unit (SMMU) subsystem. As the front-end submodule of the SMMU, the TBU is responsible for functions including, but not limited to, translating entry caching, address match testing, page table attribute checking, interactive request passing, and standard protocol conversion.

[0070] The Bus Function Model (BFM) simulates the behavior of the TCU, responding to all interactive and coordination requests from the TBU, parsing the request type, and driving the corresponding data to the corresponding interface. The TCU-BFM's functions include, but are not limited to, returning page table entries, configuring synchronization registers, replacing synchronization page tables, and identifying abnormal requests.

[0071] Based on the architecture distribution of TBUs within the chip, a unit-level test beach (UT) needs to be built to conduct comprehensive testing, covering all functions and scenarios of the TBU. Considering the reliability of verification and the difficulty of environment implementation, TBU verification strategies typically employ white-box verification or gray-box verification. White-box verification requires that the verification process not only focus on the correctness of the input and output of the module under test, but also on the correctness of the internal data paths, emphasizing the visibility and adjustability of the internal signals of the module under test (DUT).

[0072] UTs (Understanding and Testing) are typically built using the architecture of the Universal Verification Methodology (UVM). They require the implementation of environmental functional objects including transaction sequence generation units, stimulus driving units, stimulus monitoring units, bus proxy units, bus functional models, reference models, and comparison result scoreboards. UTs using white-box verification usually include a reference model, which is a prediction of the DUT's ideal state. Its core function is to provide the DUT with comparable expected results and internal states. The reference model includes functions such as, but is not limited to, data bypass detection, address matching testing, internal tag field (Tag) updates, page table entry detection, and anomaly handling. A complete page table needs to be configured in the UT. This page table is shared between the BFM (Browsing, Functional, and Component Module) and the Model. The page table can be viewed, deleted, and modified. Configuration items for the page table include, but are not limited to, virtual function access attributes, security access attributes, bypass attributes, and page table size.

[0073] This invention is primarily applied in system-on-a-chip (SoC) design to perform functional verification of the core hardware module TBU (Telematics Unit) responsible for virtual address to physical address translation. This verification environment typically includes the following key components:

[0074] The stimulus generation side consists of a UVM sequencer and a driver / BFM, which simulates a master device such as a CPU, GPU, or DMA to initiate read and write access requests to the TBU.

[0075] Reference model side: Includes a software-built reference model to simulate the TBU's address translation logic (including TLB cache lookup, page table traversal, permission checks, etc.) to produce the expected standard results;

[0076] The scoring board side is used to collect data on the actual output of the DUT and compare it with the expected output of the reference model in real time.

[0077] In one exemplary embodiment, such as Figure 1 As shown, a chip verification method is provided, including the following steps S110 to S160. Wherein:

[0078] Step S110: Configure the dynamic storage structure in the global control unit of the verification environment and establish an access handle pointing to the dynamic storage structure. First, initialize the verification environment. Instantiate a dynamic storage structure in the global control unit of the verification environment to simulate the page table storage space in memory. At the same time, create an access handle pointing to the dynamic storage structure and publish or pass the access handle to other components in the verification environment (such as the reference model, stimulus generator) to achieve shared access to the storage structure.

[0079] In this context, the global control unit refers to the component responsible for global configuration management, clock control, or virtual sequence scheduling in the verification environment. In this embodiment, it may specifically refer to the Virtual Sequencer (vsqr) in the UVM environment, or an entity with global access attributes such as a global configuration object or a top-level environment class.

[0080] Dynamic storage structures refer to data structures that can dynamically allocate memory space based on data insertion needs. Their memory usage increases linearly with the number of stored elements, rather than being fixed. Compared to static arrays, they are more suitable for storing sparse data. It should be understood that dynamic storage structures can also be configured as hash tables, red-black trees, dynamic linked lists, or associative containers from the standard template library. As long as the structure supports dynamic lookup and insertion of data via key-value pairs (such as virtual addresses), it falls within the scope of this invention. Dynamic storage structures can simulate single-level page tables or multi-level page tables simulated by nested associative arrays. For example, the first-level array stores page directory entries, and its contents point to the second-level array.

[0081] An access handle refers to a pointer, reference variable, or interface object used to reference or point to the aforementioned dynamic storage structure. Through this handle, different software modules can access the same physical memory region. The passing of access handles is not limited to the UVM p_sequencer mechanism. Optionally, they can be globally distributed through a configuration database (u_vm_config_db), or accessed through a static method in a global static class built using the singleton pattern.

[0082] For example, at the beginning of the simulation, the associative array is empty. Subsequently, the handle p_sequencer of vsqr is passed to the reference model and the bus function model so that they can both access the same array through p_sequencer.page_table.

[0083] In step S120, a transaction request is generated using the stimulus generator, sent to the module under test, and the write method is synchronously called to fill the page table entry corresponding to the transaction request into the dynamic storage structure. Since the page table entry is written directly to the shared storage area by the stimulus generator at the source, the risk of data inconsistency between the module under test and the reference model due to configuration delays is eliminated, ensuring that the data subsequently obtained by the reference model is absolutely reliable.

[0084] In this context, the stimulus generator refers to the set of components in the verification environment responsible for generating stimulus signals, typically including a test sequence generation unit (such as Sequence) and a bus driver unit (such as Driver / BFM), simulating the behavior of the master device. A transaction request refers to a complete description of a bus operation, including but not limited to information such as operation type (read / write), target virtual address, data length, burst type, and permission attributes. A write method refers to a function or interface specifically designed for inserting data into a dynamic storage structure (such as put_pte). This method is designed to be "write-only" and is typically called only by the stimulus generator. A page table entry refers to a data unit describing the mapping relationship between virtual and physical addresses, typically including the physical page frame number, access permission bits, and cache attribute bits.

[0085] During the simulation run, the stimulus generator in the verification environment is responsible for initiating the specific test process. The stimulus generator first generates a transaction request containing a virtual address according to a preset test strategy. Then, the stimulus generator performs a bidirectional synchronous operation: on the one hand, it sends the transaction request to the module under test (DUT) through a physical interface to drive the hardware logic; on the other hand, simultaneously with the transmission, it immediately calls a predefined write method to generate a corresponding page table entry based on the attributes of the transaction request, and directly writes this page table entry into the dynamic storage structure within the global control unit. It should be understood that "simultaneously with the transmission" is not limited to completion within the same clock cycle. Optionally, the write can be completed during the preprocessing phase before sending the transaction request, or during the handshake phase after transmission, as long as the data is written before the reference model reads the page table entry.

[0086] For example, the sequence unit of the stimulus generator randomly generates a read operation transaction containing a specific virtual address (e.g., 0x1000_0000). Simultaneously, based on verification requirements, the sequence unit configures the corresponding physical address (e.g., 0x8000_0000) and permission attributes (e.g., "read and write") for this virtual address, combining them into a standard page table entry data packet. On one hand, the stimulus generator packages the aforementioned read operation transaction containing the virtual address, converts it into an electrical signal conforming to the bus protocol through the driver unit, and sends it to the input port of the module under test (DUT). The DUT receives this signal and begins internal processing. On the other hand, the stimulus generator calls the write method of the global control unit through a handle. This method uses the virtual address (0x1000_0000) as the index key to store the generated page table entry data packet into the dynamic storage structure. At this point, a new, defined mapping record is added to the dynamic storage structure.

[0087] The generation logic for page table entries can be based on more than just the current transaction. Optionally, the write method can include randomization logic to automatically generate physical addresses and attributes according to a global configuration strategy; alternatively, the write method can read configuration information from a preloaded external file to populate page table entries. Although the example describes one write per transaction, in some high-performance verification scenarios, the stimulus generator can adopt a batch prefetch mode, that is, generate a group of transactions with consecutive addresses at once and call the write method at once to populate a continuous area of ​​page table entries, which is also within the scope of protection of this step.

[0088] Step S130: The transaction request is synchronously sent to the reference model. The reference model is used to calculate the index identifier based on the virtual address in the transaction request, and the label field of the virtual address is matched with the label field in the cache line of the corresponding index identifier in the reference model.

[0089] The reference model acquires the same transaction requests as the module under test (DUT) by monitoring the bus or receiving distributions. Upon receiving the request, the reference model first extracts the virtual address and, based on the DUT's hardware architecture algorithm, performs bit-field splitting and operations on the virtual address to calculate an index identifier (set_id) used to locate the cache group. The method for calculating the index identifier is not limited to XOR hashing. Optionally, it can be direct bit truncation, modulo operation, or other complex cryptographic hash algorithms. The only requirement is that the algorithm used by the reference model is consistent with the DUT's specifications.

[0090] The index identifier is the group number obtained after the virtual address is calculated using a hash algorithm. Its function is to quickly locate the target group of the virtual address in the TBU. This application's reference model supports testing in both hash-enabled and hash-disabled modes to ensure that the generated set_id matches expectations in both modes, and that the overall functionality of the TBU remains unaffected and consistent with the reference model's behavior during mode switching. When hashing is enabled, a specific field of the virtual address is calculated using a hash algorithm to obtain the set_id. The hash algorithm can evenly map virtual addresses to various groups within the TBU, preventing frequent access to certain groups and improving the TBU's hit rate. When hashing is disabled (bypass mode), a fixed field of the virtual address is directly used as the set_id, without hash calculation. Disabling hashing simplifies the set_id generation logic, allows for independent verification of the query function of entries within TBU groups, and is particularly useful for systems with extremely high deterministic requirements for address mapping. The randomness of hash algorithms can lead to unpredictable address mapping; disabling hashing makes the set_id generation rules completely transparent.

[0091] Subsequently, the reference model extracts the high-order bits of the virtual address as a tag field and, based on the calculated index identifier, locates the corresponding cache line in the simulated cache structure maintained within the model. Finally, a match test is performed between the extracted tag field and the tag field stored in the cache line to determine if a cache hit has occurred. The match test can include more complex conditions. Optionally, in addition to tag matching, permission bits or security bits can also be checked simultaneously. That is, a true hit is only considered to have occurred when both the tag and permission checks pass.

[0092] Step S140: Execute state synchronization of the internal cache replacement logic of the reference model according to the matching test result. When the matching test result is determined to be in a missing state, the reference model is triggered to enter a blocking waiting state until the cache replacement bit of the module under test is detected to be updated and then the blocking is lifted. The updated cache replacement bit is used to complete the state synchronization.

[0093] When the matching test result is determined to be missing, it indicates that the required page table entry has not yet been loaded into the reference model's internal cache. At this point, the reference model suspends its current computation and performs a sampling operation. The reference model actively enters a blocking wait state, suspending its own execution thread to continuously monitor the state of the module under test. When a cache replacement bit is detected to have been updated and the updated state contains at least one valid bit, the reference model unblocks and resumes execution, thereby achieving timing synchronization with the module under test.

[0094] Specifically, a missing state refers to a situation where no matching tag is found or the matching item is invalid during the cache lookup process, meaning that data must be retrieved from lower-level storage (such as system memory or L2 cache). Sampling operation refers to the behavior of the reference model actively acquiring values ​​of key logic nodes within the module under test. Internal state signals refer to key signals within the module under test used to maintain logical consistency. In this embodiment, it specifically refers to the cache replacement priority state (e.g., cache replacement bit, pseudo least recently used bit, aging bit, etc.) used to indicate the cache line replacement order; of course, depending on verification requirements, other auxiliary signals such as the current state of the state machine may also be included. A blocking wait state refers to a mechanism where the reference model suspends processing the current transaction until a specific wake-up condition is met before continuing operation. In software implementation, this is usually manifested as a wait() statement or event waiting. The triggering condition for blocking mainly corresponds to the missing state detected by the matching test; while the unblocking condition no longer depends on a single transaction completion flag signal or a general bus handshake signal, but is configured to monitor the update event of the cache replacement priority state. The criterion for unblocking is: detecting a value jump in the cache replacement bit, and the updated value containing a valid bit. Alternatively, to prevent deadlock, a time-based timeout mechanism can be used as an auxiliary means of resolution.

[0095] The reference model in this embodiment does not need to simulate a complex FIFO to buffer requests, nor does it need to simulate the state machine transition logic of the hardware. It only needs to stop and wait for the DUT to complete its action, and then sample the state of the DUT. This ensures that when the reference model processes the next transaction, its internal cache state is consistent with the hardware, thereby avoiding false positive errors caused by model prediction errors.

[0096] Step S150: Using the reference model, obtain the page table entry corresponding to the transaction request from the dynamic storage structure through the access handle, and calculate the expected output result of address translation based on the page table entry.

[0097] In this step, the Page Table Entry (PTE) specifically refers to the truth data stored in the dynamic storage structure. It is filled in by the stimulus generator in step S120 and represents the correct configuration expected in this simulation. The expected output result refers to the correct result that the reference model calculates based on the PTE, theoretically the correct result that the module under test should output. It typically includes the physical address (PA), response status (e.g., OKAY / ERROR), and attributes.

[0098] For example, after completing the above synchronization process, the reference model continues to execute transaction processing. Using a pre-acquired access handle, the reference model initiates a query request to the dynamic storage structure within the global control unit, directly reading the page table entry stored therein using the virtual address in the transaction request as an index. Subsequently, the reference model parses the physical base address and attribute bits in the page table entry, combines them with the page offset of the virtual address, performs bit concatenation and logical operations, and calculates the final physical address and permission check result, which serves as the expected output of the address translation. Simultaneously, the reference model uses this page table entry to update its internal simulated cache state.

[0099] If the corresponding page table entry cannot be found in the dynamic storage structure (e.g., the stimulus generator failed to write it), the reference model can be configured to throw a severe verification environment error or simulate a page fault and generate the corresponding exception response. If it is a multi-level page table, the reference model may access the dynamic storage structure multiple times (simulating multiple memory accesses), obtaining the Page Directory Entry (PDE) and Page Entries (PTE) respectively, and finally calculating the physical address.

[0100] Step S160: Compare the expected output with the output of the module under test.

[0101] For example, the scoreboard receives the expected output generated by the reference model and the actual output of the module under test. The scoreboard first performs a point-by-point consistency comparison of the core elements of both (such as physical address and response status). Furthermore, to ensure the completeness of the verification, the verification environment also performs process data comparison checks at multiple key nodes in the processing flow and records the comparison results and key status information in the simulation run log for subsequent coverage analysis and problem debugging. The comparison process is not only used for error checking but also for collecting functional coverage data, such as counting the number of occurrences of scenarios like Miss with page crossings or Hit with read-only permissions, to assess the adequacy of the verification.

[0102] Specifically, after the module under test (DUT) completes address translation, it outputs the actual physical address and response signal via the bus. These signals are captured by the bus monitor and sent to the scoring board. The scoring board also receives the expected object calculated by the reference model. The scoring board executes a comparison function; if there is a discrepancy, an error is immediately reported. When the reference model determines that the current address is bypassed, the verification environment simultaneously checks whether the DUT has set the bypass_en signal. If the reference model considers it a bypass but the hardware has not set it, a "bypass logic error" is recorded. When the reference model determines it is a miss and blocks, the scoring board checks whether the DUT has actually issued a line fill request for that address. This can effectively discover hidden bugs where the hardware misses but falsely hits. The reference model can compare the original PTE attributes obtained from the shared page table with the PTE attributes in the DUT's internal cache to ensure that the hardware has not incorrectly modified the permission bits.

[0103] The aforementioned chip verification method employs a reference model that samples the internal state signals of the module under test (DUT) and enters a blocking and waiting state until synchronization is achieved. Through this blocking and waiting mechanism, the reference model avoids replicating complex hardware instruction queues or predicting hardware timing on the software side; instead, it directly utilizes the hardware's own timing as a synchronization benchmark. By sampling the internal state, the reference model directly obtains the hardware's decision-making results under randomness (such as PLRU replacement bits). This design eliminates the need for complex software state machine development, fundamentally removing the risk of model collapse due to improper replication of hardware logic and significantly improving model stability. Furthermore, because the model accurately follows the hardware's blocking and recovery behavior in Miss scenarios, it can fully cover the timing verification requirements of the TBU under complex conditions such as address bypass, cache misses, and page refilling, overcoming the shortcomings of existing technologies that simplify the model to only focus on the result and ignore the process.

[0104] Furthermore, a dynamic storage structure within the global control unit and a mechanism for the stimulus generator to synchronously call the write method to populate page table entries were established. Accessing the dynamic storage structure (such as an associative array) via a global handle breaks the physical address limitation of traditional top-level pointers. This allows the verification environment to allocate massive virtual address spaces on demand and flexibly pass configuration attributes through handles, solving the problems of rigid page table configuration and lack of centralized management. This invention binds the page table filling action and the transaction driving action to the same stimulus source for synchronous triggering. This means that at the same simulation moment when the module under test receives the transaction request, the truth library shared by the reference model has been atomically updated. This mechanism completely eliminates the time difference caused by bus configuration delays or multi-level transmission in traditional processes, ensuring that the PTE obtained by the reference model is absolutely consistent with the PTE currently being processed by the module under test, effectively avoiding false verification errors caused by timing asynchrony.

[0105] In one embodiment, the dynamic storage structure is an associative array. This associative array employs a sparse storage strategy, using virtual addresses or their hash values ​​as index keys and page table entry structures as storage values. Compared to traditional static arrays, which require pre-allocating large blocks of contiguous physical memory, associative arrays allocate memory space only when data is written. Using associative arrays avoids allocating memory for unaccessed address spaces, thereby significantly reducing host memory consumption during simulation and improving simulation performance.

[0106] To ensure data security and consistency, the associative array is not directly exposed to all components. Instead, it is encapsulated in a global control unit and provides strictly defined access interfaces. The associative array is configured with write and read methods. The write method is called when the stimulus generator drives a transaction request to populate a single page table entry. When called, this method receives a virtual address and configured page table entry attributes as parameters. It first checks if the key-value pair already exists in the associative array; if it does, it updates it; otherwise, it creates a new entry. This operation is typically atomic, ensuring immediate data updates. The read method is used when called by the reference model to read the contents of the associative array without modifying them. When the reference model needs to query the page table, it calls this method and passes in the virtual address. This method finds the corresponding page table entry in the associative array and returns a copy. This architectural approach eliminates the risk of the reference model accidentally tampering with page table data, enhancing the robustness of the verification environment.

[0107] In one preferred embodiment, such as Figure 2 As shown, when the reference model receives a transaction request, and before performing any complex index calculations or cache lookups, it first performs a bypass detection step:

[0108] During the initialization phase, the verification environment loads a preset bypass address range through a global configuration object or register model. The reference model extracts the virtual address and possible attribute identifiers from the current transaction request and compares them with the preset bypass address range or attribute rules. If the result is yes (i.e., it falls within the bypass range), the reference model determines that the current transaction is in a bypass state and immediately performs the following operations: directly uses the input virtual address as the output physical address (PA = VA) and retains the original transaction attributes (such as read and write permissions). It immediately terminates the subsequent address translation processing flow of the transaction request in the reference model. That is, the reference model will not continue to calculate the index identifier, will not search the associative array, and will not trigger any miss judgment or blocking wait logic. If the result is no, the reference model continues to execute the subsequent normal process, i.e., enters the steps of calculating the index identifier (set_id) and performing cache matching tests.

[0109] Bypass addresses are special virtual addresses that do not require TBU address translation. The translation rules for these addresses are fixed and directly mapped by the hardware, eliminating the need to look up TBU entries or navigate memory page tables. White-box verification requires comparing the output of each step between the modified reference model and the original model. If bypass addresses continue through the subsequent processes, it generates a large amount of meaningless intermediate data comparisons, increasing the complexity and time cost of verification. Therefore, upon identifying a bypass address, the result is directly output and the process terminates, only performing subsequent steps for non-bypass addresses. This mechanism not only conforms to the actual behavior of the hardware TBU in bypass mode (low-latency pass-through) but also avoids invalid table lookups in non-translation regions of the reference model, thereby improving the model's operating efficiency.

[0110] In one exemplary embodiment, such as Figure 3 As shown, based on an embodiment that includes a bypass detection step, the method further includes a multi-level process comparison step:

[0111] During the reference model's processing of transaction requests, key verification nodes are defined as the determination of bypass status, missing status, and the acquisition of page table entries corresponding to the transaction request. At each key verification node, the intermediate state data generated by the reference model is compared with the real-time state data of the module under test at the corresponding node for consistency.

[0112] When the reference model completes bypass detection, it compares its own bypass (Is_Bypass) flag with the bypass enable signal (such as bypass_active or trans_en) inside the module under test (DUT). This prevents logical discrepancies where the model identifies a bypass but the hardware is performing a conversion or vice versa. When the reference model determines the state and prepares to block, the verification environment (scoreboard or monitor) checks the bus interface of the DUT to confirm whether a refill request for the missing address has been generated. This ensures that the hardware has indeed detected the miss and is attempting to repair it, preventing false hits that could lead to the use of expired data. When the reference model retrieves page table entries from the shared associative array and the DUT completes the refill operation, the verification environment compares the original PTE attributes (such as permission bits R / W / X) in the shared page table with the cached PTE attributes actually stored in the DUT's internal cache (TLB). This verifies whether the DUT correctly decodes and stores the attribute bits during the page table entry loading process, preventing bit flipping or truncation errors.

[0113] If the comparison results of any key verification node are inconsistent, an error report is output and the runtime log of the current simulation moment is recorded. The verification environment outputs an error report (UVM_ERROR / FATAL) through the UVM reporting mechanism, indicating the name of the node that malfunctioned, the expected value of the reference model, and the actual value of the module under test. Alternatively, the system automatically records a detailed runtime log of the current simulation moment. The log content includes the virtual address of the current transaction, the global timestamp, the internal state of the reference model (such as the PLRU tree state, set_id), and a snapshot of the relevant registers of the module under test.

[0114] In one embodiment, state synchronization of the reference model's internal cache replacement logic based on the matching test results includes:

[0115] If the matching test result indicates a hit, the cache replacement priority status is updated using the reference model based on the location of the cache line that was hit.

[0116] The cache replacement priority state refers to the logical state in the cache controller used to determine which row of data should be replaced when the cache is full. In an architecture using the pseudo-Least Recently Used (PLRU) algorithm, this state is typically represented as a binary tree register group that changes after each cache hit or miss.

[0117] Cache replacement bits are obtained by reading registers or memory arrays that indicate the cache line replacement strategy. These bits record the access history of each path in the current group, determining which path will be overwritten by new data when the next missing line occurs. For example, when the reference model finds a matching cache line internally, it needs to immediately update its replacement logic. The model flips the corresponding node bit in the binary tree according to the PLRU algorithm based on the currently hit `way_id`. This ensures that the aging state inside the model is synchronized with the aging state of the DUT due to this hit, preventing subsequent prediction bias. This process does not trigger blocking.

[0118] The reference model updates its replacement logic based on cache replacement bits to maintain a consistent cache line replacement order with the module under test. Instead of running its own independent replacement algorithm (because slight differences in hardware and software access sequences could cause algorithm state deviations), the reference model directly copies the sampled hardware bits into the corresponding simulated structure within the model. Based on the copied cache replacement bits, the reference model calculates the specific target replacement path. For example, if the PLRU bit indicates that Way 2 is the least used, the reference model decides to fill the newly acquired page table entry into the Way 2 position of the simulated cache. Through this synchronization mechanism, the reference model forces its cache line layout to be consistent with the module under test. When processing subsequent transaction requests, the reference model's Hit / Miss judgments and the path in which the Hit occurs are always synchronized with the hardware, completely eliminating false failures in verification caused by model prediction bias.

[0119] If the matching test result indicates a missing state, after the blocking and waiting state is lifted, the reference model is used to synchronously update its own cache replacement priority state based on the updated cache replacement bits of the module under test, so as to maintain the same cache line replacement order as the module under test.

[0120] For example, the cache replacement bits collected from the DUT are input into the replacement algorithm unit of the reference model to refresh the PLRU tree state inside the reference model. After synchronization is complete, the reference model uses the previously established access handle to obtain the expected page table entry from the dynamic storage structure of the global control unit, completes the address translation calculation, and sends the result to the comparator.

[0121] In one embodiment, the reference model is triggered to enter a blocked waiting state until the cache replacement bit of the module under test is detected to be updated, after which the blocking is released, including:

[0122] When the result of the matching test is missing, the processing of the reference model is suspended to enter a blocked waiting state; the cache replacement bit status of the module under test is monitored.

[0123] For example, when the reference model determines that a missing operation is detected, it identifies this as an operation that may cause a change in the internal state of the DUT. At this time, the model suspends the current transaction processing thread, enters a blocked waiting state, starts the monitoring interface, and begins to read the signals inside the DUT in real time.

[0124] When a cache replacement bit undergoes a state transition, and at least one valid bit exists in the transitioned cache replacement bit, the unblocking condition is determined to be met; the processing of the reference model is resumed, and the cache replacement bit of the module under test at the current moment is returned as the monitoring result.

[0125] The valid bit refers to the flag bit in the internal signal of the module under test (DUT) used to indicate the validity of the current cache line or replacement bit data. Monitoring this bit is to prevent the reference model from acquiring invalid random data during DUT reset or when the data is unstable. A transition refers to a change in the current replacement bit value compared to the value at the previous (or initial) time step.

[0126] When both of the above conditions are met, it means that the DUT has completed its internal processing of the transaction, allocated new entries, and updated the replacement tree. At this point, the model unblocks, latches the currently acquired DUT cache replacement bits, and resumes the execution of the main thread. The reference model then assumes that the hardware has completed the data update and proceeds with subsequent operations to acquire the PTE and update the internal state. Through this mechanism, the reference model successfully aligns its software execution flow with the hardware timing flow of the module under test.

[0127] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0128] Based on the same inventive concept, this application also provides a chip verification apparatus for implementing the chip verification method described above. The solution provided by this apparatus is similar to the implementation described in the above method; therefore, the specific limitations in one or more chip verification apparatus embodiments provided below can be found in the limitations of the chip verification method described above, and will not be repeated here.

[0129] In one exemplary embodiment, such as Figure 4 As shown, a chip verification device is provided, including: a global control module 410, an excitation generation module 420, a module under test (DUT) unit 430, a reference model module 440, and a scoring board module 450, wherein:

[0130] The global control module 410 is used to configure the dynamic storage structure in the global control unit of the verification environment and to establish an access handle pointing to the dynamic storage structure.

[0131] The stimulus generation module 420 is connected to the global control module 410 and the module under test unit 430. It is used to generate transaction requests and send the transaction requests to the module under test, and synchronously call the write method to fill the page table entries corresponding to the transaction requests into the dynamic storage structure.

[0132] The reference model module 440 is connected to the global control module 410. It is used to receive transaction requests, calculate index identifiers based on the virtual address of the transaction request, and perform matching tests between the label field of the virtual address and the label field in the cache line of the corresponding index identifier in the reference model.

[0133] The state synchronization of the internal cache replacement logic of the reference model is performed based on the matching test results. When the matching test result is determined to be a missing state, the reference model is triggered to enter a blocking waiting state until the cache replacement bit of the module under test is detected to be updated, and then the blocking is lifted and the updated cache replacement bit is used to complete the state synchronization.

[0134] Using the reference model, the page table entry corresponding to the transaction request is obtained from the dynamic storage structure through the access handle, and the expected output result of address translation is calculated based on the page table entry;

[0135] The scoring board module 450 is connected to the module under test unit 430 and the reference model module 440, and is used to compare the output results of the module under test with the expected output results.

[0136] Specifically, the global control module 410 provides shared storage resources and global configuration management for the verification environment. Internally, it has a dynamic storage structure, which in a preferred embodiment is an associative array. This associative array simulates page tables in physical memory and supports dynamic allocation of storage space on demand. The module provides access handles to this associative array and encapsulates write and read interfaces for it. The write interface is configured to be called only during the stimulus-driven phase to atomically fill a single page table entry; the read interface is configured to only allow reading without modifying the array content, allowing other modules to query it.

[0137] The output of the stimulus generation module 420 is connected to the input interface of the module under test (DUT) unit 430 and the write interface of the global control module 410, respectively, for generating and driving test stimuli. It includes a sequence generation unit (Sequence) and a driver / BFM unit, configured to generate transaction requests containing virtual addresses and send them to the DUT via a bus interface. In some embodiments, this module is configured to have synchronous dual-write functionality. While sending a transaction request to the DUT unit 430, it uses an access handle to call the write interface of the global control module 410 to write the page table entry corresponding to the transaction request into the associative array in real time.

[0138] The reference model module 440 is connected to the global control module 410 (via access handle), the stimulus generation module 420 (receiving transactions), and the module under test (monitoring status). It is used to simulate address translation logic and produce expected results, and is configured as a bufferless architecture, not maintaining an instruction queue. Specific functional units include:

[0139] The bypass detection unit is used to determine whether the virtual address is within a preset bypass address range before processing a transaction. If so, the address is directly passed through and subsequent processing is terminated.

[0140] The matching test unit calculates the index identifier and compares the label of the virtual address with the internal cache line to generate a matching test result. If the comparison is successful, a hit status signal is generated. If the comparison fails, a missing status signal is generated.

[0141] The synchronization control unit is configured as follows:

[0142] If the matching test result indicates a hit, update its own cache replacement priority status according to the position of the cache line hit this time;

[0143] If the matching test result indicates a missing state, after the blocking and waiting state is lifted, the cache replacement priority state is synchronously updated based on the updated cache replacement bit of the module under test, so as to maintain the same cache line replacement order as the module under test.

[0144] Furthermore, when the result of the matching test is a missing state, the processing of the reference model is suspended to enter a blocked waiting state;

[0145] Monitor the status of the cache replacement bit in the module under test;

[0146] When the cache replacement bit undergoes a state transition, and at least one valid bit exists in the cache replacement bit after the transition, the unblocking condition is determined to be met.

[0147] Resume the processing of the reference model and return the cache replacement bit of the module under test at the current moment as the monitoring result.

[0148] Specifically, when the reference model is determined to be in a missing state during the matching test, the execution thread of the reference model is directly suspended to enter a blocked state, and a monitoring mechanism for the module under test is initiated. The cache replacement bit of the module under test is read in real time through the backdoor access or monitoring interface. The module under test is continuously monitored until a value update is detected, and the updated value indicates the existence of a valid item. At this point, it is determined that the module under test has completed the replacement logic update corresponding to the current transaction, the blocking is lifted, and the latest sampled cache replacement bit is used to synchronize the cache replacement priority state inside the reference model. The pre-filled page table entry is obtained from the dynamic storage structure of the global control module 410 through the access handle, and the final physical address is calculated.

[0149] The input terminals of the scoring board module 450 are connected to the output terminals of the reference model module 440 and the module under test, respectively, for data comparison and verification result determination. Specific functional units include:

[0150] The result comparison unit is used to compare the expected results output by the reference model with the actual results output by the module under test.

[0151] In some embodiments, a multi-level process inspection unit is also included, which is used to perform real-time comparison of intermediate state data at key nodes of the verification process (such as bypass decision points, missing request initiation points, and page table attribute acquisition points).

[0152] Specifically, during the reference model's processing of transaction requests, the multi-level process inspection unit serves as a key verification node for determining bypass status, missing status, and obtaining the page table entry corresponding to the transaction request. At each key verification node, the intermediate state data generated by the reference model is compared with the real-time state data of the module under test at the corresponding node. If the comparison result of any key verification node is inconsistent, an error report is output and the running log of the current simulation moment is recorded.

[0153] The logging unit is used to output error reports when the comparison fails and to record simulation run logs containing the status of key nodes.

[0154] Each module in the aforementioned chip verification device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0155] In one exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 5 As shown, this computer device includes a processor, memory, input / output interfaces (I / O), and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operating system and computer programs stored in the non-volatile storage media. The database stores chip verification data. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements a chip verification method.

[0156] Those skilled in the art will understand that Figure 5 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0157] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0158] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0159] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0160] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0161] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0162] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0163] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A chip verification method, characterized in that, The method includes: Configure a dynamic storage structure in the global control unit of the verification environment, and establish an access handle pointing to the dynamic storage structure; A transaction request is generated using an excitation generator, the transaction request is sent to the module under test, and the write method is called synchronously to fill the page table entry corresponding to the transaction request into the dynamic storage structure. The transaction request is synchronously sent to the reference model, the reference model is used to calculate the index identifier based on the virtual address in the transaction request, and the tag field of the virtual address is matched with the tag field in the cache line corresponding to the index identifier in the reference model for matching test; The state synchronization of the internal cache replacement logic of the reference model is performed according to the matching test result. When the matching test result is determined to be a missing state, the reference model is triggered to sample the internal state signal of the module under test and enter a blocking waiting state until the cache replacement bit of the module under test is detected to be updated, and then the blocking is released and the state synchronization is completed using the updated cache replacement bit. Using the reference model, the page table entry corresponding to the transaction request is obtained from the dynamic storage structure through the access handle, and the expected output result of address translation is calculated based on the page table entry; The expected output result is compared with the output result of the module under test.

2. The method according to claim 1, characterized in that, The dynamic storage structure is an associative array; the associative array is configured with a write method and a read method, the write method is used to fill a single page table entry when the stimulus generator drives a transaction request, and the read method is used to read the contents of the associative array when called by the reference model without changing the contents of the associative array.

3. The method according to claim 1, characterized in that, Before calculating the index identifier based on the virtual address in the transaction request using the reference model, the method further includes: Determine whether the virtual address of the transaction request is within a preset bypass address range; If so, it is determined to be in a bypass state, the virtual address is output as the physical address, and the subsequent processing of the transaction request in the reference model is terminated.

4. The method according to claim 3, characterized in that, The method further includes: During the process of the reference model processing the transaction request, the determination of the bypass state, the missing state, and the acquisition of the page table entry corresponding to the transaction request are key verification nodes. At each of the key verification nodes, the intermediate state data generated by the reference model is compared with the real-time state data of the module under test at the corresponding node. If the comparison results of any of the key verification nodes are inconsistent, an error report will be output and the running log of the current simulation moment will be recorded.

5. The method according to claim 1, characterized in that, The state synchronization of executing the internal cache replacement logic of the reference model based on the matching test results includes: If the matching test result is determined to be a hit, the reference model is used to update its own cache replacement priority state according to the cache line position of this hit; If the matching test result is determined to be in a missing state, after the blocking waiting state is lifted, the reference model synchronously updates its own cache replacement priority state based on the updated cache replacement bit of the module under test, so as to maintain the same cache line replacement order as the module under test.

6. The method according to claim 5, characterized in that, The step of triggering the reference model to enter a blocked waiting state until the cache replacement bit of the module under test is updated is detected and the blocking is lifted includes: When the result of the matching test is the missing state, the processing of the reference model is suspended to enter the blocked waiting state; Monitor the cache replacement bit status of the module under test; When the cache replacement bit undergoes a state transition, and at least one valid bit exists in the cache replacement bit after the transition, the unblocking condition is determined to be met. Resume the processing of the reference model and return the cache replacement bit of the module under test at the current moment as the monitoring result.

7. A chip verification method system, characterized in that, include: A global control module is used to configure a dynamic storage structure in the global control unit of the verification environment and to establish an access handle pointing to the dynamic storage structure. The stimulus generation module is connected to the module under test and the global control module. It is used to generate a transaction request and send the transaction request to the module under test, and synchronously call the write method to fill the page table entry corresponding to the transaction request into the dynamic storage structure. The reference model module, connected to the global control module, is used to receive the transaction request, calculate the index identifier based on the virtual address of the transaction request, and perform a matching test between the label field of the virtual address and the label field in the cache line corresponding to the index identifier in the reference model. The state synchronization of the internal cache replacement logic of the reference model is performed according to the matching test result. When the matching test result is determined to be in a missing state, the reference model is triggered to enter a blocking waiting state until the cache replacement bit of the module under test is detected to be updated and then the blocking is released. The state synchronization is completed using the updated cache replacement bit. Using the reference model, the page table entry corresponding to the transaction request is obtained from the dynamic storage structure through the access handle, and the expected output result of address translation is calculated based on the page table entry; The scoring board module, connected to the reference model module and the module under test, is used to compare the expected output result with the output result of the module under test.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

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