Anti-radiation ldmos device structure and preparation method thereof, and electronic equipment

Abstract

The application discloses an anti-radiation LDMOS device structure and a preparation method thereof and electronic equipment. A plurality of uniformly distributed metal grooves are introduced in a second-conductivity-type drift region, the metal grooves are surrounded by a first-conductivity-type heavily doped region in the second-conductivity-type drift region, the metal grooves are connected to a source metal electrode and a drain metal electrode through a polysilicon resistor, the potential of the metal electrode in the drift region is regulated through voltage division of the polysilicon resistor, when a single particle is incident, a large number of free carriers are generated in the drift region, the carriers are attracted by the nearest metal groove under the action of an electric field, a new path is provided for the discharge of holes, the hole current is prevented from gathering to the source to lift the body region potential, and thus a parasitic bipolar transistor is prevented from being triggered to be turned on, and thus the SEB resistance of the LDMOS device is improved.

Description

Technical Field

[0001] This application relates to the field of power device technology, specifically to a radiation-resistant LDMOS device structure and its fabrication method, and electronic equipment. Background Technology

[0002] In applications such as commercial aerospace, satellite communications, high-energy physics experiments, and high-altitude aircraft, electronic systems are constantly exposed to high-energy cosmic rays and particle radiation, making the reliability of electronic devices increasingly prominent. Among these, the Single Event Effect (SEE) is one of the key factors affecting the functional safety of semiconductor devices. When high-energy particles pass through sensitive areas of semiconductor devices, they generate a large number of electron-hole pairs locally, causing current transients, latch-up, or even permanent burnout, seriously threatening the stable operation of the system.

[0003] Lateral double-diffused metal-oxide-semiconductor (LDMOS) devices are widely used in high-voltage power management and power drive circuits due to their high breakdown voltage, good power density, and compatibility with standard complementary metal-oxide-semiconductor (CMOS) processes. However, traditional LDMOS structures exhibit significant vulnerability in radiated environments: their long drift regions and uneven surface electric field distribution make them highly susceptible to single-event transients (SET), single-event gate breakdowns (SEGR), or even more severe single-event burnouts (SEB) under single-event bombardment. Particularly under high-voltage bias conditions, transient currents generated by particle tracks can trigger parasitic bipolar transistors to conduct, leading to avalanche multiplication and thermal runaway, causing irreversible damage. Summary of the Invention

[0004] In view of the above problems, this application provides a radiation-resistant LDMOS device structure and its fabrication method, as well as an electronic device, aiming to reduce the probability of device failure under single-particle irradiation.

[0005] A first aspect of this application provides a radiation-resistant LDMOS device structure, the radiation-resistant LDMOS device structure comprising:

[0006] First conductivity type substrate (110); A second conductivity type drift region (112) and a first conductivity type body region (111) are formed on the first conductivity type substrate (110). A drain doped region (113) is formed in the second conductivity type drift region (112) and extends into the first conductivity type substrate (110); wherein the drain doped region (113) is located on the side of the second conductivity type drift region (112) away from the first conductivity type body region (111); A bulk ohmic contact region (115) is formed within the second conductivity type drift region (112) and extends into the first conductivity type substrate (110); the bulk ohmic contact region (115) contacts the first conductivity type bulk region (111), and the bulk ohmic contact region (115) is located on the side of the first conductivity type bulk region (111) away from the second conductivity type drift region (112); A source doped region (114) is formed between the first conductivity type body region (111) and the body region ohmic contact region (115); the source doped region (114) has a second conductivity type; Multiple first conductivity type heavily doped regions (116) are formed inside the second conductivity type drift region (112). Gate oxide (121) formed above the first conductivity type body region (111). Field oxide (123) formed above the drift region (112) of the second conductivity type; Polysilicon (122) is formed over the gate oxide (121) and the field oxide (123), the polysilicon (122) completely covering the gate oxide (121) and partially covering the field oxide (123); the polysilicon (122) is connected to the gate electrode (G). Interlayer dielectric (120) formed on the first conductivity type substrate (110), the bulk ohmic contact region (115), the source doped region (114), the first conductivity type bulk region (111), the field oxide (123), the drain doped region (113), and the second conductivity type drift region (112). A source metal trench (118) is formed in the source doped region (114) and the interlayer dielectric (120); wherein the portion of the source metal trench (118) within the source doped region (114) is surrounded by the source doped region (114); A drain metal trench (117) is formed in the drain doped region (113) and the interlayer dielectric (120); wherein the portion of the drain metal trench (117) within the drain doped region (113) is surrounded by the drain doped region (113); Multiple drift region metal trenches (119) are formed in the first conductivity type heavily doped region (116) and the interlayer medium (120); wherein, the multiple drift region metal trenches (119) correspond to multiple first conductivity type heavily doped regions (116), and the lower half of each drift region metal trench (119) extends into the first conductivity type heavily doped region (116); A source metal electrode (132) is formed above the source metal trench (118); the source metal electrode (132) is electrically connected to the source metal trench (118) and the source electrode (S); A drain metal electrode (131) is formed above the drain metal trench (117); the drain metal electrode (131) is electrically connected to the drain metal trench (117) and the drain electrode (D); A drift region metal electrode (133) is formed above the drift region metal trench (119); the drift region metal electrode (133) is electrically connected to the drift region metal trench (119); A polysilicon resistor (134) is formed between adjacent drift region metal electrodes (133), and the two ends of the polysilicon resistor (134) are electrically connected to the adjacent drift region metal electrodes (133).

[0007] In some embodiments, the well depth of the drain doped region (113) is greater than the well depth of the second conductivity type drift region (112), and the difference between the well depth of the drain doped region (113) and the well depth of the second conductivity type drift region (112) is less than one-fifth of the well depth of the drain doped region (113).

[0008] In some embodiments, the depth of the body ohmic contact region (115) is greater than the depth of the first conductivity type body region (111), and the difference between the depth of the body ohmic contact region (115) and the depth of the first conductivity type body region (111) is less than one-fifth of the depth of the body ohmic contact region (115).

[0009] In some embodiments, the well depth of the first conductivity type heavily doped region (116) is greater than the well depth of the second conductivity type drift region (112), and the difference between the well depth of the first conductivity type heavily doped region (116) and the well depth of the second conductivity type drift region (112) is less than one-fifth of the well depth of the first conductivity type heavily doped region (116).

[0010] In some embodiments, each of the first conductivity type heavily doped regions (116) is provided with a plurality of drift region metal trenches (119), and the portion of each drift region metal trench (119) within the first conductivity type heavily doped region (116) is surrounded by the first conductivity type heavily doped region (116).

[0011] In some embodiments, a plurality of first conductivity type heavily doped regions (116) are spaced apart inside the second conductivity type drift region (112), and the first conductivity type heavily doped regions (116) extend into the first conductivity type substrate (110).

[0012] In some embodiments, the polysilicon resistors (134) are arranged in a continuous, zigzag pattern.

[0013] In some embodiments, the distance between two adjacent drift region metal electrodes (133) in the lateral position is the same, and the length of the polysilicon resistor (134) between two adjacent drift region metal electrodes (133) in the lateral position is the same.

[0014] A second aspect of this application also provides a method for fabricating the radiation-resistant LDMOS device structure described in any of the above claims, the method comprising: Obtain a substrate (110) having a first conductivity type; Ion implantation is performed on one surface of the substrate (110), followed by annealing to form a drift region (112) of the second conductivity type and a body region (111) of the first conductivity type. High-quality oxide is dry-grown on the surface of the device structure, and the oxide above the body region (111) is used as the gate oxide (121) of the LDMOS device. Wet oxidation growth field oxide (123) is performed above the drift region (112) of the second conductivity type. Polysilicon (122) is deposited over the gate oxide (121) and over the field oxide (123) portion to form the gate polysilicon of the LDMOS device; Long strip-shaped trenches are etched on one side of the first conductivity type body region (111) and the second conductivity type drift region (112), and multiple rectangular trenches are etched in the field oxide (123) and the second conductivity type drift region (112). Ion implantation is performed on the elongated trench on one side of the second conductivity type drift region (112) to form a drain doped region (113) of the second conductivity type, and ion implantation is performed on the first conductivity type body region (111) near the polysilicon (122) to form a source doped region (114) of the second conductivity type. Ion implantation is performed on the elongated trench in the first conductivity type body region (111) to form a body region ohmic contact region (115), and ion implantation is performed on the rectangular trench in the drift region to form a body region ohmic contact region (115), and ohmic contact annealing is performed to repair the lattice. An oxide layer is deposited on the device surface to form an interlayer dielectric (120). The oxides in the trenches of the ohmic contact region (115), the second conductivity type drift region (112), and the source doped region (114) are etched to form vias; Metal is deposited on the surface of the device, and the metal fills the trench through the via to form a source metal trench (118), a drift region metal trench (119), and a drain metal trench (117). The metal also covers the surface of the interlayer dielectric (120). Then the metal on the interlayer dielectric (120) is etched to form a source metal electrode (132), a drain metal electrode (131), and a drift region metal electrode (133). Polysilicon is deposited and etched on the interlayer dielectric (120) of the source metal electrode (132), the drift region metal electrode (133) and the drain metal electrode (131) to form a polysilicon resistor (134).

[0015] A third aspect of this application also provides an electronic device, including: a radiation-resistant LDMOS device structure as described in any of the above embodiments.

[0016] The beneficial effects of this application embodiment are as follows: By introducing multiple uniformly distributed metal trenches in the second conductivity type drift region, the metal trenches are surrounded by the first conductivity type heavily doped region in the second conductivity type drift region. The metal trenches are connected to the source metal electrode and the drain metal electrode through polysilicon resistors. By voltage division of the polysilicon resistors, the potential of the metal electrodes in the drift region is controlled. When a single particle is incident, a large number of free charge carriers are generated in the drift region. Under the action of the electric field, the charge carriers are attracted by the nearest metal trench, providing a new path for hole discharge. This prevents the hole current from accumulating towards the source and raising the body region potential, thereby triggering the parasitic bipolar transistor to conduct, thus improving the SEB resistance of the LDMOS device. Furthermore, the radiation-hardened LDMOS device structure in this application introduces a heavily doped region of the first conductivity type, which can provide additional recombination centers for irradiated carriers, reduce the lifetime of irradiated induced carriers, and thus reduce SET current pulses. At the same time, the heavy doped region of the first conductivity type and the drift region of the second conductivity type form a lateral PN junction, which optimizes the electric field distribution in the gate region, thereby preventing the accumulation of carriers at the gate oxide interface and helping to reduce the risk of SEGR.

[0017] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0018] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiments below. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 This is a schematic diagram of the radiation-resistant LDMOS device structure provided in the embodiments of this application; Figure 2 for Figure 1 A schematic diagram of the radiation-resistant LDMOS device structure after removing the interlayer dielectric (120); Figure 3 for Figure 1 A schematic diagram of the radiation-resistant LDMOS device structure after removing the interlayer dielectric (120) and field oxide (123); Figure 4 for Figure 1 A top view of the radiation-resistant LDMOS device structure in the image; Figure 5 For along Figure 1 A schematic diagram of the A1 section of a medium-radiation LDMOS device structure; Figure 6 For along Figure 1 A schematic diagram of the A2 section of a medium-radiation-resistant LDMOS device structure; Figure 7 For along Figure 1 A schematic diagram of the A3 section of a radiation-resistant LDMOS device structure; Figure 8 For along Figure 1 A schematic diagram of the A4 cross-section of a radiation-resistant LDMOS device structure; Figure 9 For conventional LDMOS devices and this application Figure 1 Simulation diagram of the SET effect in the radiation-resistant LDMOS device structure; Figure 10 For conventional LDMOS devices and this application Figure 1 Simulation diagram of SEB effect in radiation-resistant LDMOS device structure; Figure 11 Simulation diagrams of the maximum electric field strength of the gate oxide of conventional LDMOS devices and the radiation-resistant LDMOS devices of this invention; Figure 12 This is a flowchart of a method for fabricating a radiation-resistant LDMOS device structure according to an embodiment of this application; Figure 13a , Figure 13b , Figure 13c , Figure 13d , Figure 13e , Figure 13f , Figure 13g , Figure 13h , Figure 13i , Figure 13j , Figure 13k , Figure 13l According to one embodiment of this application Figure 12 The diagram shows some cross-sectional views of the process of manufacturing radiation-resistant LDMOS devices using the method shown. Detailed Implementation

[0019] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0021] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0022] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The phrase "second connection port" at various locations in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0023] In related technologies, research on combating SEE (Search Engine Effect) in LDMOS devices mainly focuses on methods such as using source segmentation (SS) technology, introducing high-precision field plates and precisely doping to modulate the surface electric field, or using silicon-on-insulator (SOI) substrates. However, to improve SEB resistance, SS-LDMOS sacrifices the source region area and reduces the effective channel width, resulting in a significant increase in the device's characteristic on-resistance. Introducing high-precision field plates and precisely doping to modulate the drift region electric field of LDMOS devices involves high process complexity and is sensitive to process fluctuations, leading to increased device parameter dispersion. Furthermore, SOI technology is incompatible with standard bulk silicon CMOS technology, making it difficult to achieve large-scale application while balancing performance, cost, and reliability.

[0024] Current technologies generally focus on limiting the gain of parasitic LDMOS transistors or suppressing electric field peaks, but lack effective means for actively guiding and rapidly discharging single-event induced transient currents. If transient currents accumulate locally in the drift region, they can still trigger thermal runaway. Therefore, there is an urgent need to propose a novel radiation-resistant LDMOS device structure design that significantly improves its immunity to single-event effects while maintaining low conduction losses and high breakdown voltage, and is compatible with standard bulk silicon processes, providing a power device solution with both performance and robustness for highly reliable electronic systems.

[0025] To address the aforementioned technical problems, this application provides a radiation-resistant LDMOS device structure, see [link to relevant documentation]. Figure 1 As shown, the radiation-resistant LDMOS device structure in this embodiment includes: a first conductivity type substrate 110, a second conductivity type drift region 112, a first conductivity type body region 111, a drain doped region 113, a body region ohmic contact region 115, a source doped region 114, a first conductivity type heavily doped region 116, a gate oxide 121, a field oxide 123, polysilicon 122, an interlayer dielectric 120, a source metal trench 118, a drain metal trench 117, a drift region metal trench 119, a source metal electrode 132, a drain metal electrode 131, a polysilicon resistor 134, and a drift region metal electrode 133.

[0026] In this embodiment, a second conductivity type drift region 112 and a first conductivity type body region 111 are formed on a first conductivity type substrate 110. A drain doped region 113 is formed within the second conductivity type drift region 112 and extends into the first conductivity type substrate 110, with the drain doped region 113 located on the side of the second conductivity type drift region 112 away from the first conductivity type body region 111. A body ohmic contact region 115 is formed within the second conductivity type drift region 112 and extends into the first conductivity type substrate 110, contacting the first conductivity type body region 111, and located on the side of the first conductivity type body region 111 away from the second conductivity type drift region 112. A source doped region 114 is formed between the first conductivity type body region 111 and the body ohmic contact region 115, and the source doped region 114 has a second conductivity type.

[0027] Multiple heavily doped regions 116 of the first conductivity type are formed inside the drift region 112 of the second conductivity type. Gate oxide 121 is formed above the body region 111 of the first conductivity type, and field oxide 123 is formed above the drift region 112 of the second conductivity type. Polysilicon 122 is formed above the gate oxide 121 and the field oxide 123, completely covering the gate oxide 121 and partially covering the field oxide 123; the polysilicon 122 is connected to the gate electrode G. Interlayer dielectric 120 is formed above the substrate 110 of the first conductivity type, the ohmic contact region 115 of the body region, the source doped region 114, the body region 111 of the first conductivity type, the field oxide 123, the drain doped region 113, and the drift region 112 of the second conductivity type.

[0028] Figure 2 This is a schematic diagram of the structure after removing the interlayer medium 120. Figure 3 This is a schematic diagram of the structure after removing the interlayer medium 120 and field oxide 123, combined with... Figure 1 , Figure 2 as well as Figure 3As shown, a source metal trench 118 is formed within a source doped region 114 and an interlayer dielectric 120, with the portion of the source metal trench 118 within the source doped region 114 surrounded by the source doped region 114. A drain metal trench 117 is formed within a drain doped region 113 and an interlayer dielectric 120, with the portion of the drain metal trench 117 within the drain doped region 113 surrounded by the drain doped region 113. A plurality of drift region metal trenches 119 are formed within a first conductivity type heavily doped region 116 and an interlayer dielectric 120, with each drift region metal trench 119 corresponding to a plurality of first conductivity type heavily doped regions 116, and the lower half of each drift region metal trench 119 extending into the first conductivity type heavily doped region 116. A source metal electrode 132 is formed above a source metal trench 118 and is electrically connected to the source metal trench 118 and the source electrode S. A drain metal electrode 131 is formed above a drain metal trench 117 and is electrically connected to the drain metal trench 117 and the drain electrode D. A drift region metal electrode 133 is formed above a drift region metal trench 119 and is electrically connected to the drift region metal trench 119. Figure 4 for Figure 1 A top view of the structure of a radiation-resistant LDMOS device. A polysilicon resistor 134 is formed between adjacent drift region metal electrodes 133, and the two ends of the polysilicon resistor 134 are electrically connected to the adjacent drift region metal electrodes 133 respectively.

[0029] In this embodiment, multiple uniformly distributed drift region metal trenches 119 are introduced within the second conductivity type drift region 112. The metal trenches are surrounded by a first conductivity type heavily doped region 116 within the second conductivity type drift region 112. The metal trenches are connected to the source metal electrode 132 and the drain metal electrode 131 via a polysilicon resistor 134. By dividing the voltage through the polysilicon resistor 134, the potential of the metal electrodes within the second conductivity type drift region 112 is controlled. When a single particle is incident, a large number of free charge carriers are generated within the second conductivity type drift region 112. Under the action of the electric field, the charge carriers are attracted by the nearest metal trench, providing a new path for the discharge of holes. This prevents the hole current from accumulating towards the source and raising the body region potential, thereby triggering the conduction of the parasitic bipolar transistor. This greatly improves the SEB resistance capability of the radiation-resistant LDMOS device structure in this embodiment.

[0030] In some embodiments, Figure 5 For along Figure 1 Schematic diagram of section A1, Figure 6 For along Figure 1 Schematic diagram of section A2 in the middle. Figure 7 For along Figure 1 Schematic diagram of section A3 in the middle. Figure 8 For along Figure 1The schematic diagram at section A4 shows that in this embodiment, by introducing multiple uniformly distributed heavily doped regions 116 of the first conductivity type within the second conductivity type drift region 112, the heavily doped regions 116 provide additional recombination centers for irradiated carriers, reducing the lifetime of irradiated induced carriers and thus reducing the SET current pulse. Furthermore, the heavily doped regions 116 and the second conductivity type drift region 112 form a lateral PN junction, which helps optimize the electric field distribution within the device drift region, enhances the lateral electric field in the gate region, and reduces the longitudinal electric field in the gate region, thereby preventing carrier accumulation at the gate oxide interface and reducing the risk of SEGR.

[0031] In some specific application embodiments, when high-energy particles are incident on the sensitive region of a semiconductor device, a large number of electron-hole pairs are generated on their tracks. These free carriers have long lifetimes and do not recombine rapidly. Instead, they are rapidly collected under the drive of a local electric field, thereby inducing a brief voltage or current pulse at the circuit node, which may cause logic errors, signal distortion, or even system failures. The radiation-hardened LDMOS device structure described above introduces multiple uniformly distributed heavily doped regions within the drift region, providing additional recombination centers for electron-hole pair recombination. When high-energy particles are incident, the generated electron-hole pairs recombine rapidly with the assistance of nearby recombination centers, reducing the current pulse generated after carrier collection, thereby effectively mitigating the SET effect of the LDMOS device. Figure 9 The simulation diagrams show the SET effect of conventional LDMOS devices and the radiation-hardened LDMOS device structure of this invention. Figure 9 It can be seen that the peak value and integral value of the SET pulse current of the radiation-resistant LDMOS device of the present invention are significantly smaller than those of conventional LDMOS devices.

[0032] In some application embodiments, when the LDMOS device operates under high-voltage bias conditions, high-energy particles pass through the drift region of the LDMOS, inducing a large current that triggers the conduction of parasitic bipolar transistors, leading to avalanche positive feedback and thermal runaway. This ultimately results in irreversible damage such as local melting and short circuits, i.e., the SEB effect of LDMOS. Because multiple uniformly distributed drift region metal trenches 119 are introduced within the second conductivity type drift region 112, and corresponding first conductivity type heavily doped regions 116 surround the drift region metal trenches 119 within the second conductivity type drift region 112, adjacent drift region metal trenches 119 are connected through polysilicon resistors 134 to regulate the potential. The first conductivity type heavily doped regions 116 within the second conductivity type drift region 112 can assist in drift region depletion, optimize the electric field within the drift region, and thus improve the breakdown voltage of the LDMOS device. When high-energy particles are incident on the drift region, the resulting free carriers are absorbed by the adjacent drift region metal trench 119 under the influence of the electric field, providing a new path for hole discharge and suppressing the rise in the body region potential, thereby triggering the parasitic bipolar transistor to turn on. Simultaneously, the source metal trench 118 extends deep into the ohmic contact region 115 of the body region, optimizing the hole current path and allowing more hole current to flow directly from the body region to the body doped region, reducing the current density through the drift region-body region-source doped region. This further prevents carriers from accumulating in the source doped region and suppresses the parasitic bipolar transistor to turn on. The drain metal trench 117 extends deep into the second conductivity type drift region 112, dispersing the drain current density and preventing excessive drain current concentration and melting caused by excessive current heating, thereby improving the SEB resistance of the LDMOS device. Figure 10 The figure shows the SEB effect simulation diagram of conventional LDMOS device and radiation-resistant LDMOS device of the present invention. As can be seen from the figure, the SEB threshold voltage of radiation-resistant LDMOS device of the present invention is 19V, which is 46% higher than the 13V SEB threshold voltage of conventional LDMOS device.

[0033] In some application embodiments, holes generated by the incident charged particles drift towards the gate oxide 121 interface. The electric field formed by the holes accumulated at the gate oxide 121 interface superimposed on the original steady-state electric field of the device, generating a transient spike electric field in the oxide layer, which breaks down the gate oxide 121 dielectric, known as the SEGR effect. In the radiation-hardened LDMOS device structure of this embodiment, multiple uniformly distributed first conductivity type heavily doped regions 116 are introduced in the second conductivity type drift region 112. The two drift regions of different conductivity types form a lateral PN junction, which optimizes the electric field distribution in the drift region, enhances the lateral electric field in the gate region, reduces the longitudinal electric field in the gate region, thereby weakening the accumulation of radiation-induced holes in the gate region and reducing the risk of single-event gate breakdown in the LDMOS device. Figure 11 The simulation diagrams show the maximum electric field strength of the gate oxide of a conventional LDMOS device and the radiation-resistant LDMOS device of this invention. Figure 11 It can be seen that after charged particles are incident, the maximum electric field strength in the gate oxide of the radiation-resistant LDMOS device of the present invention is significantly smaller than that of conventional LDMOS devices, thus achieving stronger SEGR resistance.

[0034] In some embodiments, the well depth of the drain doped region 113 is greater than the well depth of the drift region 112 of the second conductivity type, and the difference between the well depth of the drain doped region 113 and the well depth of the drift region 112 of the second conductivity type is less than one-fifth of the well depth of the drain doped region 113.

[0035] In this embodiment, the well depth of the drain doped region 113 is comparable to the well depth of the drift region 112 of the second conductivity type.

[0036] In some embodiments, the well depth of the body ohmic contact region 115 is greater than the well depth of the first conductivity type body region 111, and the difference between the well depth of the body ohmic contact region 115 and the well depth of the first conductivity type body region 111 is less than one-fifth of the well depth of the body ohmic contact region 115.

[0037] In this embodiment, the well depth of the body ohmic contact region 115 is equivalent to the well depth of the first conductivity type body region 111.

[0038] In some embodiments, the well depth of the first conductivity type heavily doped region 116 is greater than the well depth of the second conductivity type drift region 112, and the difference between the well depth of the first conductivity type heavily doped region 116 and the well depth of the second conductivity type drift region 112 is less than one-fifth of the well depth of the first conductivity type heavily doped region 116.

[0039] In this embodiment, the well depth of the first conductivity type heavily doped region 116 is comparable to the well depth of the second conductivity type drift region 112.

[0040] In some embodiments, each first conductivity type heavily doped region 116 is provided with a plurality of drift region metal trenches 119, and the portion of each drift region metal trench 119 within the first conductivity type heavily doped region 116 is surrounded by the first conductivity type heavily doped region 116.

[0041] In this embodiment, a plurality of uniformly distributed first conductivity type heavily doped regions 116 are introduced in the second conductivity type drift region 112, which can provide additional recombination centers for irradiated carriers, which helps to reduce the lifetime of irradiated induced carriers and thus reduce the SET current pulse.

[0042] In some embodiments, a plurality of first conductivity type heavily doped regions 116 are spaced apart inside the second conductivity type drift region 112, and the first conductivity type heavily doped regions 116 extend into the first conductivity type substrate 110.

[0043] In this embodiment, the first conductivity type heavily doped region 116 and the second conductivity type drift region 112 form a lateral PN junction, which optimizes the electric field distribution in the gate region and transforms the longitudinal electric field into a lateral electric field, thereby preventing the accumulation of charge carriers at the gate oxide interface and reducing the risk of SEGR.

[0044] In some embodiments, the polysilicon resistors 134 are arranged in a continuous, zigzag pattern.

[0045] In some embodiments, the distance between two adjacent drift region metal electrodes 133 in the lateral position is the same, and the length of the polysilicon resistor 134 between two adjacent drift region metal electrodes 133 in the lateral position is the same.

[0046] In this embodiment, multiple uniformly distributed drift region metal trenches 119 are introduced within the second conductivity type drift region 112. A heavily doped first conductivity type region 116 surrounds the drift region metal trenches 119. The drift region metal trenches 119 are connected to the source metal electrode 132 and the drain metal electrode 131 via a polysilicon resistor 134. The potential of the drift region metal electrode 133 within the drift region is controlled by voltage division at the drain metal electrode 131. When the device operates under a high drain voltage bias condition, the heavily doped region assists in the depletion of the drift region, optimizing the drift region electric field and improving the breakdown voltage of the LDMOS device. When a single particle is incident, a large number of free charge carriers are generated in the drift region. Under the action of the electric field, the charge carriers are attracted by the nearest metal trench, providing a new path for the discharge of holes and preventing the hole current from accumulating at the source and raising the body potential, thereby triggering the parasitic bipolar transistor to conduct. The source metal trench attracts holes, causing the hole current path in the body region to redistribute, further preventing the parasitic bipolar transistor from conducting. The drain metal trench disperses the drain current density, preventing excessive concentration of drain current and resulting in thermal melting, thereby improving the SEB resistance of the radiation-resistant LDMOS device structure in this embodiment.

[0047] In some embodiments, the polysilicon resistor 134 can be replaced by a trap resistor, extending the metal electrode in the drift region to the outside of the active region, and electrically connecting it to the trap resistor outside the active region through a via.

[0048] In some embodiments, the resistance of the polysilicon resistor 134 is in the range of 10MΩ to 100MΩ.

[0049] In some embodiments, the first conductivity type is P-type and the second conductivity type is N-type.

[0050] This application also provides a method for fabricating a radiation-resistant LDMOS device structure according to any of the above claims, the method comprising steps S201 to S212.

[0051] In step S201, as Figure 13aAs shown, a first conductivity type substrate 110 is obtained.

[0052] In this embodiment, the first conductivity type substrate 110 can be a P-type silicon carbide material or a P-type silicon substrate.

[0053] In step S202, as Figure 13b As shown, ion implantation is performed on one surface of a first conductivity type substrate 110, and after high-temperature annealing, a second conductivity type drift region 112 and a first conductivity type body region 111 are formed.

[0054] In this embodiment, combined with Figure 13b As shown, by implanting second conductive ions into a first predetermined region on the first surface of a first conductivity type substrate 110, a second conductivity type drift region 112 is formed after annealing. Then, by implanting first conductive ions into the second predetermined region, a first conductivity type body region 111 is formed after annealing. The third predetermined region on the first surface of the first conductivity type substrate 110 may not undergo ion implantation, and the second predetermined region is located between the third predetermined region and the first predetermined region.

[0055] In some embodiments, the area of ​​the first preset region is larger than the area of ​​the third preset region.

[0056] In step S203, as Figure 13c As shown, in Figure 13b The device structure shown has a surface dry-grown high-quality oxide, and the oxide portion above the first conductivity type body region 111 is the gate oxide 121 of the LDMOS device.

[0057] In this embodiment, a dry oxidation process can be used to... Figure 13b The first surface of the device structure shown is generated with oxide, and then the oxide on the second conductivity type drift region 112 is removed by etching, leaving the oxide above the first conductivity type body region 111 as the gate oxide 121 of the LDMOS device.

[0058] In some embodiments, all may be retained. Figure 13b The oxide generated on the first surface of the device structure shown is, for example Figure 13c As shown.

[0059] In step S204, as Figure 13d As shown, a wet oxidation growth field oxide 123 is grown above the second conductivity type drift region 112.

[0060] In this embodiment, a field oxide 123 can be formed on the second conductivity type drift region 112 by a wet oxidation process, such as... Figure 13d As shown.

[0061] In some embodiments, it can be directly in Figure 13c A field oxide 123 is formed on a portion of the first surface of the device structure shown (the portion above the drift region 112 of the second conductivity type) using a wet oxidation process.

[0062] In step S205, as Figure 13e As shown, polysilicon 122 is deposited over the gate oxide 121 and the field oxide 123 to form the gate G of the LDMOS device.

[0063] In this embodiment, polysilicon 122 covers a portion of the area above the gate oxide 121 and a portion of the area on the field oxide 123.

[0064] In step S206, as Figure 13f As shown, an elongated trench 301 is etched on the side of the first conductivity type body region 111 near the second conductivity type drift region 112, and multiple rectangular trenches 302 are etched in the field oxide 123 and the second conductivity type drift region 112.

[0065] In this embodiment, an elongated trench 301 is formed on one side of the second conductivity type drift region 112 near the third preset region on the first conductivity type body region 111 by an etching process. The first side of the elongated trench 301 is close to the third preset region, and the second side of the elongated trench 301 is close to the polysilicon 122. The trench depth of the elongated trench 301 is comparable to the junction depth of the first conductivity type body region 111 and the second conductivity type drift region 112, respectively. The trench depth of the plurality of rectangular trenches 302 is comparable to the junction depth of the second conductivity type drift region 112.

[0066] In some embodiments, the depth of the elongated trench 301 is greater than the thickness of the first conductive type body region 111, the elongated trench 301 divides the first conductive type body region 111 into two parts, and the width of the first conductive type body region 111 on the first side of the elongated trench 301 is less than the width of the first conductive type body region 111 on the second side of the elongated trench 301.

[0067] In some embodiments, the trench depth of the rectangular trench 302 is greater than the thickness of the second conductivity type drift region 112.

[0068] In step S207, as Figure 13g As shown, ion implantation is performed on the first conductivity type body region 111 on the second side of the elongated trench 301 to form a drain doped region 113 of the second conductivity type, and ion implantation is performed on the first conductivity type body region 111 next to the polysilicon 122 to form a source doped region 114 of the second conductivity type.

[0069] In this embodiment, the second side of the elongated trench 301 is the side closest to the polysilicon 122, and a portion of the first conductive type body region 111 on the second side of the elongated trench 301 is located below the polysilicon 122.

[0070] In step S208, as Figure 13h As shown, an ion implantation is performed on the elongated trench 301 in the first conductivity type body region 111 to form an ohmic contact region 115, and an ion implantation is performed on the rectangular trench 302 in the drift region to form an ohmic contact region 115, and then ohmic contact annealing is performed to repair the lattice.

[0071] In step S209, as Figure 13i As shown, in Figure 13h An oxide layer is deposited on the surface of the device shown to form an interlayer dielectric 120.

[0072] In this embodiment, by means of Figure 13h The first surface of the device is deposited with an oxide layer to form an interlayer dielectric 120, which covers the ohmic contact region 115 and the drain doped region 113.

[0073] In step S210, as Figure 13j As shown, the oxides in the trenches of the body region ohmic contact region 115, the second conductivity type drift region 112, and the source doped region 114 are etched to form vias 303.

[0074] In this embodiment, each through hole 303 can connect multiple rectangular trenches 302 in the same row and the bulk ohmic contact area 115 formed by ion implantation of the rectangular trenches 302 in the drift region.

[0075] In step S211, as Figure 13k As shown, in Figure 13j The device surface shown is deposited with metal, which fills the trench through the via 303 to form the source metal trench 118, the drift region metal trench 119 and the drain metal trench 117; the metal also covers the surface of the interlayer dielectric 120, and finally the metal on the interlayer dielectric 120 is etched to form the source metal electrode 132, the drain metal electrode 131 and the drift region metal electrode 133.

[0076] In step S212, as Figure 13l As shown, polysilicon is deposited and etched on the interlayer dielectric 120 of the source metal electrode 132, the drift region metal electrode 133 and the drain metal electrode 131 to form a polysilicon resistor 134.

[0077] In this embodiment, the first conductivity type heavily doped regions 116, corresponding one-to-one within the second conductivity type drift region 112, surround the drift region metal trenches 119. Adjacent drift region metal trenches 119 are connected by polysilicon resistors 134 to regulate the potential. The source metal trench 118 extends deep into the body region ohmic contact region 115, optimizing the hole current path and allowing more hole current to flow directly from the body region to the body region doped region, reducing the current density through the drift region-body region-source doped region, further preventing carrier accumulation in the source doped region, and suppressing the conduction of parasitic bipolar transistors. The drain metal trench 117 extends deep into the second conductivity type drift region 112, dispersing the drain current density, preventing excessive concentration of drain current, and preventing melting caused by excessive current heating effect, thereby improving the SEB resistance of the LDMOS device.

[0078] The fabrication method described in this embodiment only requires an additional trench etching step, without the need to introduce an additional photolithography mask layer. It is compatible with standard bulk silicon CMOS processes. While effectively improving the resistance to single-particle irradiation, it also takes into account the device's electrical performance, manufacturing cost, and reliability, and has the potential for large-scale application in space and high-radiation environments.

[0079] This application also provides an electronic device, including: a radiation-resistant LDMOS device structure as described in any of the above embodiments.

[0080] In this embodiment, by employing the radiation-resistant LDMOS device structure described in any of the above embodiments in an electronic device, the radiation resistance of the electronic device is improved. Specifically, within each radiation-resistant LDMOS device structure, multiple uniformly distributed metal trenches are introduced within a second conductivity type drift region. These metal trenches are surrounded by a first conductivity type heavily doped region within the second conductivity type drift region. The metal trenches are connected to the source and drain metal electrodes via polysilicon resistors. By voltage division using the polysilicon resistors, the potential of the metal electrodes within the drift region is controlled. When a single particle is incident, a large number of free charge carriers are generated within the drift region. Under the influence of the electric field, these charge carriers are attracted to the nearest metal trench, providing a new path for hole discharge. This prevents hole current from accumulating towards the source, raising the body region potential, and triggering the parasitic bipolar transistor to conduct, thereby improving the SEB resistance of the LDMOS device. Furthermore, the radiation-hardened LDMOS device structure in this application introduces a heavily doped region of the first conductivity type, which can provide additional recombination centers for irradiated carriers, reduce the lifetime of irradiated induced carriers, and thus reduce SET current pulses. At the same time, the heavy doped region of the first conductivity type and the drift region of the second conductivity type form a lateral PN junction, which optimizes the electric field distribution in the gate region, thereby preventing the accumulation of carriers at the gate oxide interface and helping to reduce the risk of SEGR.

[0081] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0082] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0083] In the embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the electronic device embodiments described above are merely illustrative. For example, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0084] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0085] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0086] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A radiation-resistant LDMOS device structure, characterized in that, The radiation-resistant LDMOS device structure includes: First conductivity type substrate (110); A second conductivity type drift region (112) and a first conductivity type body region (111) are formed on the first conductivity type substrate (110). A drain doped region (113) is formed in the second conductivity type drift region (112) and extends into the first conductivity type substrate (110); wherein the drain doped region (113) is located on the side of the second conductivity type drift region (112) away from the first conductivity type body region (111); A bulk ohmic contact region (115) is formed within the second conductivity type drift region (112) and extends into the first conductivity type substrate (110); the bulk ohmic contact region (115) contacts the first conductivity type bulk region (111), and the bulk ohmic contact region (115) is located on the side of the first conductivity type bulk region (111) away from the second conductivity type drift region (112); A source doped region (114) is formed between the first conductivity type body region (111) and the body region ohmic contact region (115); the source doped region (114) has a second conductivity type; Multiple first conductivity type heavily doped regions (116) are formed inside the second conductivity type drift region (112). Gate oxide (121) formed above the first conductivity type body region (111). Field oxide (123) formed above the drift region (112) of the second conductivity type; Polysilicon (122) is formed over the gate oxide (121) and the field oxide (123), the polysilicon (122) completely covering the gate oxide (121) and partially covering the field oxide (123); the polysilicon (122) is connected to the gate electrode (G). Interlayer dielectric (120) formed on the first conductivity type substrate (110), the bulk ohmic contact region (115), the source doped region (114), the first conductivity type bulk region (111), the field oxide (123), the drain doped region (113), and the second conductivity type drift region (112). A source metal trench (118) is formed in the source doped region (114) and the interlayer dielectric (120); wherein the portion of the source metal trench (118) within the source doped region (114) is surrounded by the source doped region (114); A drain metal trench (117) is formed in the drain doped region (113) and the interlayer dielectric (120); wherein the portion of the drain metal trench (117) within the drain doped region (113) is surrounded by the drain doped region (113); Multiple drift region metal trenches (119) are formed in the first conductivity type heavily doped region (116) and the interlayer medium (120); wherein, the multiple drift region metal trenches (119) correspond to multiple first conductivity type heavily doped regions (116), and the lower half of each drift region metal trench (119) extends into the first conductivity type heavily doped region (116); A source metal electrode (132) is formed above the source metal trench (118); the source metal electrode (132) is electrically connected to the source metal trench (118) and the source electrode (S); A drain metal electrode (131) is formed above the drain metal trench (117); the drain metal electrode (131) is electrically connected to the drain metal trench (117) and the drain electrode (D); A drift region metal electrode (133) is formed above the drift region metal trench (119); the drift region metal electrode (133) is electrically connected to the drift region metal trench (119); A polysilicon resistor (134) is formed between adjacent drift region metal electrodes (133), and the two ends of the polysilicon resistor (134) are electrically connected to the adjacent drift region metal electrodes (133).

2. The radiation-resistant LDMOS device structure according to claim 1, characterized in that, The well depth of the drain doped region (113) is greater than the well depth of the drift region (112) of the second conductivity type, and the difference between the well depth of the drain doped region (113) and the well depth of the drift region (112) of the second conductivity type is less than one-fifth of the well depth of the drain doped region (113).

3. The radiation-resistant LDMOS device structure according to claim 1, characterized in that, The depth of the body ohmic contact region (115) is greater than the depth of the first conductivity type body region (111), and the difference between the depth of the body ohmic contact region (115) and the depth of the first conductivity type body region (111) is less than one-fifth of the depth of the body ohmic contact region (115).

4. The radiation-resistant LDMOS device structure according to claim 1, characterized in that, The well depth of the first conductivity type heavily doped region (116) is greater than the well depth of the second conductivity type drift region (112), and the difference between the well depth of the first conductivity type heavily doped region (116) and the well depth of the second conductivity type drift region (112) is less than one-fifth of the well depth of the first conductivity type heavily doped region (116).

5. The radiation-resistant LDMOS device structure according to claim 1, characterized in that, Each of the first conductivity type heavily doped regions (116) is provided with a plurality of drift region metal trenches (119), and the portion of each drift region metal trench (119) within the first conductivity type heavily doped region (116) is surrounded by the first conductivity type heavily doped region (116).

6. The radiation-resistant LDMOS device structure according to claim 1, characterized in that, Multiple first conductivity type heavily doped regions (116) are spaced apart inside the second conductivity type drift region (112), and the first conductivity type heavily doped regions (116) extend into the first conductivity type substrate (110).

7. The radiation-resistant LDMOS device structure according to claim 1, characterized in that, The polycrystalline silicon resistors (134) are arranged in a continuous, zigzag pattern.

8. The radiation-resistant LDMOS device structure according to claim 1, characterized in that, The distance between two adjacent drift region metal electrodes (133) in the lateral position is the same, and the length of the polycrystalline silicon resistor (134) between two adjacent drift region metal electrodes (133) in the lateral position is the same.

9. A method for fabricating a radiation-resistant LDMOS device structure as described in any one of claims 1-8, characterized in that, The preparation method includes: Obtain a substrate (110) having a first conductivity type; Ion implantation is performed on one surface of the substrate (110), followed by annealing to form a drift region (112) of the second conductivity type and a body region (111) of the first conductivity type. High-quality oxide is dry-grown on the surface of the device structure, and the oxide above the body region (111) is used as the gate oxide (121) of the LDMOS device. Wet oxidation growth field oxide (123) is performed above the drift region (112) of the second conductivity type. Polysilicon (122) is deposited over the gate oxide (121) and over the field oxide (123) portion to form the gate polysilicon of the LDMOS device; Long strip-shaped trenches are etched on one side of the first conductivity type body region (111) and the second conductivity type drift region (112), and multiple rectangular trenches are etched in the field oxide (123) and the second conductivity type drift region (112). Ion implantation is performed on the elongated trench on one side of the second conductivity type drift region (112) to form a drain doped region (113) of the second conductivity type, and ion implantation is performed on the first conductivity type body region (111) near the polysilicon (122) to form a source doped region (114) of the second conductivity type. Ion implantation is performed on the elongated trench in the first conductivity type body region (111) to form a body region ohmic contact region (115), and ion implantation is performed on the rectangular trench in the drift region to form a body region ohmic contact region (115), and ohmic contact annealing is performed to repair the lattice. An oxide layer is deposited on the device surface to form an interlayer dielectric (120). The oxides in the trenches of the ohmic contact region (115), the second conductivity type drift region (112), and the source doped region (114) are etched to form vias; Metal is deposited on the surface of the device, and the metal fills the trench through the via to form a source metal trench (118), a drift region metal trench (119), and a drain metal trench (117). The metal also covers the surface of the interlayer dielectric (120). Then the metal on the interlayer dielectric (120) is etched to form a source metal electrode (132), a drain metal electrode (131), and a drift region metal electrode (133). Polysilicon is deposited and etched on the interlayer dielectric (120) of the source metal electrode (132), the drift region metal electrode (133) and the drain metal electrode (131) to form a polysilicon resistor (134).

10. An electronic device, characterized in that, include: The radiation-resistant LDMOS device structure as described in any one of claims 1 to 8.

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