A high PSR low power consumption N-type low dropout linear regulator without off-chip capacitor

Abstract

This invention discloses a high PSR, low power consumption, capacitor-free N-type low-dropout linear regulator, belonging to the field of analog integrated circuits. The regulator includes an error amplifier, a voltage buffer, a PSR enhancement circuit, and an NMOS power transistor. The voltage buffer uses a unity-gain negative feedback configuration, employing a smaller quiescent current at the same output impedance. At the output voltage... V OUT When the voltage rises, the error amplifier and voltage buffer suppress the rise through a negative feedback loop. V OUT To achieve circuit stability, the PSR enhancement circuit uses a high-pass filter for sampling. V OUT Ripple at mid-to-high frequencies creates negative feedback, generating gain that acts on... V OUT This ultimately improves power supply rejection at mid-to-high frequencies. Compared to PMOS transistors, using NMOS transistors as power transistors allows for a smaller footprint while maintaining the same current. This invention offers advantages such as low power consumption, high PSR, and small footprint, making it suitable for mobile smart terminals, embedded systems, low-power IoT devices, and various high-precision analog circuit systems sensitive to power supply noise.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuits, and specifically relates to an N-type low dropout linear regulator with high PSR, low power consumption and no external capacitors. Background Technology

[0002] System-on-a-Chip (SoC) typically requires a switching power converter to provide multiple voltage domains for different types of circuit blocks. Its output exhibits significant ripple at the switching frequency, thus a low-dropout linear regulator (LDO) is often cascaded after it to power noise-sensitive analog circuits. Furthermore, the switching frequency of digital circuits can also couple to the power supply of analog circuits through parasitic capacitances within the circuitry. Since LDOs are also used in Internet of Things (IoT) sensor systems, they need to have low no-load quiescent power consumption (PSR) to extend battery life. While LDOs with external μF-level capacitors offer good power supply rejection characteristics, they are not conducive to integration. Therefore, an LDO with high PSR, low power consumption, and ease of integration is worth researching and developing.

[0003] Because LDOs have high low-frequency (DC) loop gain, typical LDOs exhibit optimal power supply rejection (PSR) at lower frequencies. However, at higher frequencies, the PSR begins to degrade due to the limited loop bandwidth of the LDO. Therefore, it is worthwhile to investigate how to improve the PSR at mid-to-high frequencies.

[0004] Improving the power supply rejection ratio (PSR) at mid-to-high frequencies is mainly achieved through feedforward technology and adding series components at the input to shield power supply noise. While using a series low-pass filter circuit or pre-regulating with an LDO can indeed improve the PSR, this reduces the maximum achievable efficiency of the low-dropout regulator. For LDOs with PMOS as the power transistor, the PSR can be improved by sampling the power supply voltage ripple and applying the voltage signal 1:1 to the power transistor's gate, thus keeping VGS constant. However, for NMOS as the power transistor, sampling the power supply ripple does not involve applying the voltage signal 1:1 to the gate; instead, the PSR needs to be adjusted according to the specific circuit. Therefore, this method is very sensitive to PVT and is not suitable for practical use. Summary of the Invention

[0005] In view of the above, the present invention proposes an N-type low dropout linear regulator with high PSR, low power consumption and no external capacitor, which mainly consists of an error amplifier, a voltage buffer, a PSR enhancement circuit and a power transistor MN14.

[0006] The first input terminal of the error amplifier is connected to a reference voltage. V ref The second input terminal is connected to the feedback voltage. V fb Output terminal V1 Connect the input terminal of the voltage buffer; The voltage buffer adopts a unity-gain negative feedback structure at the output terminal. V G Connect the NMOS power transistor M N14 The gate; The NMOS power transistor M N14 The drain is connected to the power supply voltage. V DD Source output regulated voltage V OUT The feedback voltage is generated through a feedback resistor network. V fb ; The PSR enhancement circuit includes a high-pass filter, the input of which is connected to the NMOS power transistor. M N14 The source terminal is connected to the output terminal of the voltage buffer. V G Used for sampling V OUT The high-frequency power supply ripple in the medium and high frequency components forms negative feedback. when V OUT When the ripple frequency is low, the PSR enhancement circuit is inactive, and circuit voltage stabilization is achieved solely through the error amplifier and voltage buffer; when... V OUT When the ripple frequency increases, the error amplifier is bandwidth-limited and does not operate, and the PSR enhancement circuit generates gain to the output of the voltage buffer. V G This results in gain suppression in the negative feedback loop of the PSR enhancement circuit. V OUT change.

[0007] Preferably, the PSR enhancement circuit is implemented by a common-source amplifier with active negative feedback, including an NMOS transistor. M N12 NMOS transistor M N13 and capacitor C H The M N13 The source is grounded, and the gate is connected to the bias voltage generated by the current source. V N1 Drain connection M N12 The source pole; M N12The drain connection voltage buffer output terminal V G Gate connection M N14 The source of the capacitor; C H One end connection M N12 One end is the source, and the other end is grounded.

[0008] Preferably, the equivalent transconductance expression of the PSR enhancement circuit is: ; In the formula, for M N13 Small signal impedance, for M N12 The transconductance of S is the Laplace operator; By adjusting and The parameters enable the PSR enhancement circuit to generate peak gain at the target frequency.

[0009] Preferably, the error amplifier adopts a two-stage folded cascode structure, including an input transconductance stage and a cascode output stage; The input transconductance stage includes four PMOS transistors. M p1 , M p2 , M p3 and M p4 , used to generate small signal current; M p1 and M p2 The gate is connected. M p1 The drain is connected to the current source. M p1 and M p2 The source is connected to a pre-regulated voltage to form the input side. M p2 As a tail current source, the input differential pair M p3 and M p4 The source is connected and M p2 Drain connection; M p3 The gate of the amplifier is the first input terminal of the error amplifier. M p4 The gate is the second input terminal of the error amplifier; The common-source, common-gate output stage includes four PMOS transistors. M p5 , M p6 , M p7 , M p8 and four NMOS transistors M N1 , M N2 , M N3 , M N4 Used to provide output impedance M p5 and M p6 The source is connected to a pre-regulated voltage. M p5 drain connection M p7 The source pole, M p6 drain connection M p8 The source pole, M p7 and M p8 The gate is connected. M p5 and M p6 The gate is connected. M N1 and M N2 The source is grounded. M N1 and M N2 The gate is connected. M N1 drain connection M N3 The source pole, M N2 Drain, M N4 The source pole and M p4 The three drain electrodes are connected together. M N3 and M N4 The gate is connected. M N1 and M N3 The drain is connected to M p3 The drain electrode, MN2 and M N4 The drain is connected to M p4 The drain electrode, M p7 and M N3 The drains are connected. M p8 and M N4 The drain of the amplifier is connected to the output terminal of the error amplifier.

[0010] Preferably, the voltage buffer includes a first-stage gain and a second-stage gain; The first-stage gain consists of an input differential pair, a common-mode negative feedback module, and a PMOS transistor. M p9 and M p10 and NMOS transistors M N5 Composition; the input difference pair includes M N6 and M N7 ; M p9 and M p10 The source is connected to a pre-regulated voltage. M p9 and M p10 The gate is connected; M N5 The source is grounded. M N5 gate connection M N1 The gate; M N6 The gate is the input terminal of the voltage buffer. M N6 and M N7 The source poles are connected together M N5 The drain electrode; M p9 drain connection M N6 The drain electrode, M p10 drain connection M N7 The drain of the common-mode negative feedback module is connected to... M p9 and M p10 Between the drain electrodes; The second-stage gain includes a PMOS transistor. M p11 , M p12 and NMOS transistor M N8 , M N9 ; M p11 and M p12 Used to generate small signal current, its sources are all connected to a pre-regulated voltage. M p11 and M p12 The gates are all with M p9 Drain connection; M N8 and M N9 Used to provide output impedance, its sources are all grounded. M N8 and M N9 The gate is connected. M N8 The gate and drain are shorted to form a diode connection. M p11 and M N8 The drains are connected. M p12 , M N9 Drain and M N7 The gate is connected as the output of the voltage buffer and connected to M N14 The gate.

[0011] Preferably, the common-mode negative feedback module includes R 1 and R 2 , R 1 The first end and M p9 The drain connection, R 2 The first end and M p10 The drain connection, R 1 and R 2 The second end is connected to M p9 and M p10The gate of the voltage divider forms a voltage divider node.

[0012] Preferably, M p1 The gate and drain are shorted to form a diode connection, thereby generating a bias voltage. V P1 External bias circuit generates bias voltage V P2 , V N2 and V N1 Apply to M p7 , M N3 and M N1 Gate; bias voltage V N1 and V P1 Used to provide bias current and bias voltage V P2 and V N2 This is used to ensure that all transistors in the common-source, common-gate output stage of the error amplifier operate in the saturation region.

[0013] Preferably, the feedback resistor network consists of resistors connected in series. R 3 and resistance R 4 The component consists of a connection point that outputs the feedback voltage. V fb To the second input terminal of the error amplifier.

[0014] Preferably, the NMOS power transistor M N1 4 The source is connected to a load capacitor. C L and load voltage R L , used to simulate load.

[0015] Preferably, the output terminal V 1 Through capacitor C 1 Grounding.

[0016] Compared with the prior art, the present invention has the following beneficial effects: (1) The core loop of the LDO uses NMOS power transistors. M N14As a pass transistor, NMOS has two advantages. First, compared to traditional PMOS power transistors, the higher electron mobility of NMOS allows for a smaller device area to be required for the same current drive capability, thereby reducing gate parasitic capacitance and improving loop bandwidth. Second, its low output impedance allows for the placement of the main pole internally.

[0017] (2) The present invention improves the PSR in the mid-to-high frequency range by using a high-pass filter and forming negative feedback. On the one hand, since the high-pass filter does not generate gain at low frequencies, loop stability problems are avoided. On the other hand, since it is a closed-loop system, it does not change much with PVT, thus overcoming the problem that the improvement of PSR is very sensitive to PVT in existing technologies (such as feedforward ripple elimination technology).

[0018] (3) By using a unity-gain negative feedback buffer, the present invention effectively reduces static power consumption while achieving the same output impedance, compared with the existing method of using a source follower, thereby reducing the static power consumption of the entire regulator. Attached Figure Description

[0019] Figure 1 Schematic diagram of a high PSR N-type low dropout linear regulator with no external capacitors; Figure 2 Small-signal block diagram of a high PSR N-type low dropout linear regulator with no external capacitor; Figure 3 The waveform diagram for PSR simulation. Detailed Implementation

[0020] The present invention will now be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the present invention.

[0021] like Figure 1 The diagram shows a high PSR, low power consumption, capacitor-free N-type low-dropout linear regulator provided by the present invention, comprising an error amplifier, a voltage buffer, a PSR enhancement circuit, and a power transistor. M N14 .

[0022] The error amplifier employs a folded cascode structure, which provides sufficiently high DC gain at lower supply voltages while maintaining a wide output swing. The error amplifier includes an input transconductance stage and a cascode output stage, wherein the input transconductance stage includes... M p1 , M p2 ,M p3 and M p4 Four PMOS transistors are used to generate small-signal current; the cascode output stage includes... M p5 , M p6 , M p7 , M p8 Four PMOS transistors and M N1 , M N2 , M N3 , M N4 Four NMOS transistors are used to provide the output impedance.

[0023] In the input transconductance stage, M p1 and M p2 The gate is connected. M p1 The drain is connected to the current source. M p1 The gate and drain are shorted to form a diode connection, as shown in the figure. V p1 for M p1 The bias voltage generated by the diode connection is used to generate the bias current; M p1 and M p2 The source is connected to a pre-regulated voltage. V pre_5V It constitutes the input side. M p2 As a tail current source, the input differential pair M p3 and M p4 The source is connected and M p2 The drain connection. M p3 The gate is connected to the reference voltage. V ref , M p3 The drain of the common source cascode output stage M N1 and M N3 The drain electrode. M p4 Gate feedback voltage Vfb , M p4 The drain of the common source cascode output stage M N2 and M N4 The drain. Input differential pair M p3 and M p4 Comparison feedback voltage V fb With reference voltage V ref And the error signal is amplified.

[0024] In a common source cascode output stage, M p5 and M p6 The source is connected to a pre-regulated voltage. V pre_5V , M p5 drain connection M p7 The source pole, M p6 drain connection M p8 The source pole. M p7 and M p8 The gate is connected. M p5 and M p6 The gate is connected and with M p7 The drains are shorted to form a diode connection. M N1 and M N2 The source is grounded. M N1 and M N2 The gate is connected. M N1 drain connection M N3 The source pole, M N2 drain connection M N4 The source pole, M N3 and M N4 The gate is connected. M p7 drain connection M N3The drain electrode, M p8 and M N4 The drain of the circuit is connected to the output of the error amplifier, and the output node voltage is... V 1 This output node is connected to C 1 One end, C 1 The other end is grounded. (See diagram) V P2 , V N1 and V N2 All of these are bias voltages generated by an external bias circuit, among which, V N1 Used to generate bias current V P2 and V N2 This is used to ensure that all transistors in the common-source, common-gate output stage of the error amplifier operate in the saturation region.

[0025] The voltage buffer employs a unity-gain negative feedback structure, comprising a first-stage gain and a second-stage gain. The first-stage gain consists of the input differential pair, the common-mode negative feedback module, and... M p9 , M p10 Two PMOS transistors and one NMOS transistor M N5 The structure includes input difference pairs. M N6 and M N7 Common-mode negative feedback includes R 1 and R 2 The second-stage gain is determined by... M p11 , M p12 Two PMOS transistors and M N8 , M N9 It consists of two NMOS transistors.

[0026] In the first level of gain, M p9 and M p10 The source is connected to a pre-regulated voltage. V pre_5V , M p9 and Mp10 The gate is connected. M N5 The source is grounded. M N5 gate connection M N1 The gate; M N6 The gate access error amplifier output V 1 As input to the voltage buffer, M N6 and M N7 The source poles are connected together M N5 The drain electrode; M p9 drain connection M N6 The drain electrode, M p10 drain connection M N7 The drain electrode, R 1 The first end and M p9 The drain connection, R 2 The first end and M p10 The drain connection, R 1 and R 2 The second end is connected to M p9 and M p10 The gate of the voltage divider forms a voltage divider node. M N6 and M N7 Used to generate small signal current, and through R 1 and R 2 for M p9 and M p10 Provide common-mode negative feedback, M p9 , M p10 , R 1 and R 2 Used to provide output impedance.

[0027] In the second level of gainM p11 and M p12 Used to generate small signal current, its sources are all connected to a pre-regulated voltage. V pre_5V , M p11 and M p12 The gates are all with M p9 The drain connection. M N8 and M N9 Used to provide output impedance, its sources are all grounded. M N8 and M N9 The gate is connected. M N8 The gate and drain are shorted to form a diode connection. M p11 and M N8 The drains are connected. M p12 , M N9 Drain and M N7 The gate is connected as the output of the voltage buffer and connected to M N14 The gate of the output node voltage is V G , V G and V 1 Equal. The structure of the voltage buffer can effectively reduce the output impedance, which is beneficial for forming a high-frequency loop on the one hand, and ensures the stability of the entire main loop on the other.

[0028] The PSR enhancement circuit consists of a common-source amplifier with active negative feedback, including... M N12 , M N13 and C H This common-source amplifier is essentially a high-pass filter. M N13 The source is grounded, and the gate is connected to the bias voltage. V N1 , M N13 Drain and M N12 The source is connected and connected C HOne end, C H The other end is grounded. M N12 The drain is connected to the output node of the voltage buffer, and the gate is connected to... M N14 The source pole.

[0029] M N14 The source output stable voltage V OUT , M N14 The source poles are connected in parallel. R L , C L and series R 3 and R 4 , R L and C L Used to simulate load, R 3 and R 4 The connection forms a feedback resistor network and generates a feedback voltage. V fb to M P4 The gate, M N14 The drain is connected to the power supply voltage. V DD .

[0030] When the output voltage V OUT When it is too high, V fb Increase, that is M p4 The gate voltage increases at this time. M p4 The drain voltage decreases, that is... M N4 The source voltage decreases, therefore M N4 The drain voltage decreases, thus leading to V 1 The voltage at the point decreases. V 1 The voltage at the point decreases, i.e. M N6 If the gate voltage decreases, then M N6 The voltage at the drain increases, that is... M P12As the gate voltage increases, the reverse gain effect of the common-source amplifier stage... V G The voltage drops, thus pulling down V OUT Until feedback voltage V fb With reference voltage V ref The voltage values ​​are equal.

[0031] In addition, when V G The voltage is slightly higher V 1 hour, M N7 The drain voltage decreases, that is... M P11 The gate voltage decreases, thereby M P11 The gate voltage is greater than M P12 The gate voltage causes M N8 As the gate voltage increases, the reverse gain effect of the common-source amplifier stage... V G The voltage decreases until it is equal to... V 1 The voltage remains constant.

[0032] Accordingly, when the output voltage V OUT When it is low, V fb Reduce, that is M p4 When the gate voltage decreases, at this time M p4 The drain voltage increases, that is M N4 The source voltage increases, therefore M N4 The drain voltage increases, thus leading to V 1 The voltage at the point increases. V 1 The voltage at the point increases, i.e. M N6 If the gate voltage increases, then M N6 The voltage at the drain electrode decreases, that is... M P12 As the gate voltage decreases, the reverse gain effect of the common-source amplifier stage... V G The voltage increases, thereby pulling up V OUT Until feedback voltage Vfb With reference voltage V ref The voltage values ​​are equal.

[0033] In addition, when V G The voltage is slightly lower V 1 hour, M N7 The drain voltage increases, that is M P11 The gate voltage increases, thus M P11 The gate voltage is less than M P12 The gate voltage causes M N8 As the gate voltage decreases, the reverse gain effect of the common-source amplifier stage... V G The voltage rises until it is equal to... V 1 Keep the voltage consistent. Figure 1 The circuit is divided into Figure 2 The small signal block diagram shown provides a more intuitive demonstration of the circuit's working principle.

[0034] in, gm 1 yes M p3 and M p4 transconductance, r o1 yes V 1 Node output impedance, gm 2 It refers to the input differential pairs, common-mode negative feedback, and input mode negative feedback in the circuit buffer. M p9 , M p10 , M p11 , M p12 The equivalent transconductance, r o2 , C 2 They are V G The node's output impedance and equivalent capacitance to ground, G(S), are given by... M N12 , M N13 and C H constitute. G MN ,r on They are M N14 The transconductance and small-signal impedance of the power transistor V GS yes M N14 Gate-source voltage, V S For the source node voltage. V S The value is equal to V OUT . R fb1 and R fb2 Corresponding to Figure 1 In R 3 and R 4 , R L and C L That is Figure 1 In R L and C L .

[0035] In the diagram, Loop 1 samples the feedback voltage through an error amplifier. V fb And amplify to generate V 1 Loop2 is sampled via the PSR enhancement circuit. V OUT The mid-to-high frequency power supply ripples in the loop form negative feedback, which is amplified by the Loop3 through a two-stage amplifier. V G voltage and V 1 The voltage difference creates negative feedback, making V G Capable of precise tracking V 1 The changes in Loop1 will... V 1 The point is taken as the dominant pole. To ensure loop stability, this requires... V G and V S If the pole frequencies are all outside the gain-bandwidth product GBW1 of Loop1, then it is necessary to ensure that GBW3 of Loop3 is greater than GBW1 of Loop1. V SAs long as the pole frequency is greater than GBW1 under light load, stability under full load can be guaranteed. The dominant pole of the Loop3 loop is... V G Because there are no other high-resistance nodes inside, this loop is relatively stable.

[0036] For G(S), let gm H yes M N12 transconductance, r oH yes M N13 The small-signal impedance. Then, from M N12 , M N13 and C H The equivalent transconductance expression can be approximated as: In the formula, S is the Laplace operator. When V OUT The small signal current generated at very low frequencies is only V OUT · / r oH ; and when V OUT When the frequency is high enough, the generated small signal current is V OUT ·gm H By adjusting r oH and CH The parameters ensure that the peak gain (i.e., G(S) is maximum) at the target frequency (1MHz in this embodiment) and there is no gain at low frequencies. Therefore, when V OUT When the ripple frequency is low, Loop3 does not work, while Loop1 and Loop2 are active, and the power supply ripple is suppressed by the negative feedback loop Loop1.

[0037] when V OUT When the ripple reaches a certain frequency (e.g., around 1MHz), for example... M N12 When the gate voltage increases, a sufficient small signal current will be generated. V G This point, thus generating gain, makes V G The point voltage decreases, thereby suppressing... V OUT The high-frequency variation. This enhancement circuit can improve the PSR. times.

[0038] Figure 3The corresponding PSR simulation waveforms are shown below. The blue line represents the PSR simulation waveform with a load current of 100µA and the PSR enhancement circuit proposed in this invention included. The green curve represents the PSR simulation waveform with a load current of 100µA but without the PSR enhancement circuit. It can be seen that at 1MHz, this PSR enhancement circuit effectively improves the PSR by 6dB. The red line represents the PSR simulation waveform with a load current of 25mA and the PSR enhancement circuit proposed in this invention included. The yellow curve represents the PSR simulation waveform with a load current of 25mA but without the PSR enhancement circuit. Similarly, it can be seen that at 1MHz, this PSR enhancement circuit effectively improves the PSR by 6dB. In summary, this PSR enhancement circuit can effectively improve the PSR at a selected frequency across the entire load current range under the same quiescent current.

[0039] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A high PSR, low power consumption, and capacitor-free N-type low dropout linear regulator, characterized in that, Includes error amplifier, voltage buffer, PSR enhancement circuit and NMOS power transistor. M N14 ; The first input terminal of the error amplifier is connected to a reference voltage. V ref The second input terminal is connected to the feedback voltage. V fb Output terminal V 1 Connect the input terminal of the voltage buffer; The voltage buffer adopts a unity-gain negative feedback structure at the output terminal. V G Connect the NMOS power transistor M N14 The gate; The NMOS power transistor M N14 The drain is connected to the power supply voltage. V DD Source output regulated voltage V OUT The feedback voltage is generated through a feedback resistor network. V fb ; The PSR enhancement circuit includes a high-pass filter, the input of which is connected to the NMOS power transistor. M N14 The source terminal is connected to the output terminal of the voltage buffer. V G Used for sampling V OUT The high-frequency power supply ripple in the medium and high frequency components forms negative feedback. when V OUT When the ripple frequency is low, the PSR enhancement circuit is inactive, and circuit voltage stabilization is achieved solely through the error amplifier and voltage buffer; when... V OUT When the ripple frequency increases, the error amplifier is bandwidth-limited and does not operate, and the PSR enhancement circuit generates gain to the output of the voltage buffer. V G This results in gain suppression in the negative feedback loop of the PSR enhancement circuit. V OUT change.

2. The voltage regulator according to claim 1, characterized in that, The PSR enhancement circuit is implemented by a common-source amplifier with active negative feedback, including an NMOS transistor. M N12 NMOS transistor M N13 and capacitor C H The M N13 The source is grounded, and the gate is connected to the bias voltage generated by the current source. V N1 Drain connection M N12 The source pole; M N12 The drain connection voltage buffer output terminal V G Gate connection M N14 The source pole; capacitance C H One end connection M N12 One end is the source, and the other end is grounded.

3. The voltage regulator according to claim 2, characterized in that, The equivalent transconductance expression of the PSR enhancement circuit is: ； In the formula, for M N13 Small signal impedance, for M N12 The transconductance of S is the Laplace operator; By adjusting and The parameters enable the PSR enhancement circuit to generate peak gain at the target frequency.

4. The voltage regulator according to claim 1, characterized in that, The error amplifier adopts a two-stage folded cascode structure, including an input transconductance stage and a cascode output stage; The input transconductance stage includes four PMOS transistors. M p1 , M p2 , M p3 and M p4 , used to generate small signal current; M p1 and M p2 The gate is connected. M p1 The drain is connected to the current source. M p1 and M p2 The source is connected to a pre-regulated voltage to form the input side. M p2 As a tail current source, the input differential pair M p3 and M p4 The source is connected and M p2 Drain connection; M p3 The gate of the amplifier is the first input terminal of the error amplifier. M p4 The gate is the second input terminal of the error amplifier; The common-source, common-gate output stage includes four PMOS transistors. M p5 , M p6 , M p7 , M p8 and four NMOS transistors M N1 , M N2 , M N3 , M N4 Used to provide output impedance M p5 and M p6 The source is connected to a pre-regulated voltage. M p5 drain connection M p7 The source pole, M p6 drain connection M p8 The source pole, M p7 and M p8 The gate is connected. M p5 and M p6 The gate is connected. M N1 and M N2 The source is grounded. M N1 and M N2 The gate is connected. M N1 drain connection M N3 The source pole, M N2 Drain, M N4 The source pole and M p4 The three drain electrodes are connected together. M N3 and M N4 The gate is connected. M N1 and M N3 The drain is connected to M p3 The drain electrode, M N2 and M N4 The drain is connected to M p4 The drain electrode, M p7 and M N3 The drains are connected. M p8 and M N4 The drain of the amplifier is connected to the output terminal of the error amplifier.

5. The voltage regulator according to claim 4, characterized in that, The voltage buffer includes a first-stage gain and a second-stage gain; The first-stage gain consists of an input differential pair, a common-mode negative feedback module, and a PMOS transistor. M p9 and M p10 and NMOS transistors M N5 Composition; the input difference pair includes M N6 and M N7 ; M p9 and M p10 The source is connected to a pre-regulated voltage. M p9 and M p10 The gate is connected; M N5 The source is grounded. M N5 gate connection M N1 The gate; M N6 The gate is the input terminal of the voltage buffer. M N6 and M N7 The source poles are connected together M N5 The drain electrode; M p9 drain connection M N6 The drain electrode, M p10 drain connection M N7 The drain of the common-mode negative feedback module is connected to... M p9 and M p10 Between the drain electrodes; The second-stage gain includes a PMOS transistor. M p11 , M p12 and NMOS transistor M N8 , M N9 ; M p11 and M p12 Used to generate small signal current, its sources are all connected to a pre-regulated voltage. M p11 and M p12 The gates are all with M p9 Drain connection; M N8 and M N9 Used to provide output impedance, its sources are all grounded. M N8 and M N9 The gate is connected. M N8 The gate and drain are shorted to form a diode connection. M p11 and M N8 The drains are connected. M p12 , M N9 Drain and M N7 The gate is connected as the output of the voltage buffer and connected to M N14 The gate.

6. The voltage regulator according to claim 5, characterized in that, The common-mode negative feedback module includes R 1 and R 2 , R 1 The first end and M p9 The drain connection, R 2 The first end and M p10 The drain connection, R 1 and R 2 The second end is connected to M p9 and M p10 The gate of the voltage divider forms a voltage divider node.

7. The voltage regulator according to claim 4, characterized in that, M p1 The gate and drain are shorted to form a diode connection, thereby generating a bias voltage. V P1 External bias circuit generates bias voltage V P2 , V N2 and V N1 Apply to M p7 , M N3 and M N1 Gate; bias voltage V N1 and V P1 Used to provide bias current and bias voltage V P2 and V N2 This is used to ensure that all transistors in the common-source, common-gate output stage of the error amplifier operate in the saturation region.

8. The voltage regulator according to claim 1, characterized in that, The feedback resistor network consists of resistors connected in series. R 3 and resistance R 4 The component consists of a connection point that outputs the feedback voltage. V fb To the second input terminal of the error amplifier.

9. The voltage regulator according to claim 1, characterized in that, The NMOS power transistor M N1 4 The source is connected to a load capacitor. C L and load voltage R L , used to simulate load.

10. The voltage regulator according to claim 1, characterized in that, Output V 1 Through capacitor C 1 Grounding.

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