Power management circuit and display device

Abstract

A power management circuit and a display device are provided. The display device includes a display panel, a data driving circuit, a gate driving circuit, a controller configured to supply image data corresponding to a data voltage to the data driving circuit and to control the data driving circuit and the gate driving circuit, and a power management circuit including a plurality of voltage conversion circuits and a plurality of driving voltage supply circuits, each driving voltage supply circuit configured to supply a driving voltage to at least one of a plurality of sub-pixels, the data driving circuit, the gate driving circuit, and the controller based on an input voltage supplied from a corresponding one of the plurality of voltage conversion circuits. The power management circuit is configured to cause a first driving voltage supply circuit of the plurality of driving voltage supply circuits, which is configured to supply a first driving voltage to the data driving circuit, to be deactivated during at least one first sub-frame in at least one frame corresponding to the image data.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0181803, filed on December 09, 2024, with the Korean Intellectual Property Office, which is incorporated herein by reference for all purposes as if fully set forth herein. Technical Field

[0003] This disclosure relates to electronic devices, and more particularly to power management circuitry and display devices including such power management circuitry. Background Technology

[0004] In today's information society, display devices used to present images or visual information to users are becoming increasingly important. The need for such display devices has led to the rapid development of display technology, and various types of display devices have been developed and are used, such as liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays.

[0005] Among these display devices, organic light-emitting display devices using self-emissive organic light-emitting diodes (OLEDs) exhibit high response speed and have advantages such as contrast ratio, luminous efficiency, brightness, and viewing angle compared to other types of display devices (such as liquid crystal display (LCD) devices).

[0006] Power management is becoming increasingly important, and to reduce power consumption, display devices can employ variable refresh rate (VRR) mode, where the refresh rate can be varied. When a display device displays a still image in VRR mode that does not require rapid updates to the data voltage, the frame period of the driving transistors can be reduced to allow the driving transistors to be driven at a lower rate. Therefore, the display device can reduce power consumption. However, a display device may not minimize power consumption solely by employing VRR mode. Summary of the Invention

[0007] One or more aspects of this disclosure may provide power management circuitry and display devices configured to disable the operation of at least one drive voltage supply circuitry during a specific subframe, thereby enabling power consumption reduction.

[0008] One or more aspects of this disclosure may provide power management circuitry and display devices configured to change the voltage output from at least one voltage conversion circuit during a specific subframe, thereby enabling power consumption reduction.

[0009] One or more aspects of this disclosure may provide a power management circuit and a display device configured to operate in a forced continuous current mode (FCCM) during periods when the voltage output of a voltage conversion circuit changes, thereby reducing time delays during voltage changes.

[0010] The aspects, examples, and embodiments provided in this disclosure are not limited to the foregoing description, and additional aspects, examples, and embodiments provided in this disclosure will become apparent to those skilled in the art from the following description.

[0011] According to one or more embodiments of the present invention, a display device may be provided, comprising: a display panel including a plurality of gate lines, a plurality of data lines, and a plurality of sub-pixels; a data driving circuit configured to supply a data voltage to the plurality of data lines; a gate driving circuit configured to drive the plurality of gate lines; a controller configured to supply image data corresponding to the data voltage to the data driving circuit and to control the data driving circuit and the gate driving circuit; and a power management circuit including a plurality of voltage conversion circuits and a plurality of driving voltage supply circuits, each driving voltage supply circuit being configured to supply a driving voltage to at least one of the plurality of sub-pixels, the data driving circuit, the gate driving circuit, and the controller based on an input voltage supplied from a corresponding one of the plurality of voltage conversion circuits.

[0012] In one or more aspects, the power management circuitry may be configured to cause a first drive voltage supply circuit, which is configured to supply a first drive voltage to the data drive circuitry, to be deactivated during at least one first subframe in at least one frame corresponding to the image data.

[0013] According to one or more embodiments of the present invention, a power management circuit may be provided, comprising: a first voltage conversion circuit configured to convert an initial voltage supplied from a system power supply into a first input voltage; a second voltage conversion circuit configured to convert the initial voltage into a second input voltage; a first drive voltage supply circuit configured to generate a first drive voltage based on the first input voltage and supply the first drive voltage to a data drive circuit, the first drive voltage supply circuit being configured to be deactivated during at least one first subframe in at least one frame corresponding to image data supplied from a controller to the data drive circuit; and a second drive voltage supply circuit configured to generate a second drive voltage based on the second input voltage and supply the second drive voltage to the data drive circuit, the second drive voltage supply circuit being configured to be deactivated during at least one second subframe in the at least one frame.

[0014] According to one or more aspects of this disclosure, a power management circuit and display device may be provided that can reduce power consumption by disabling the operation of at least one drive voltage supply circuit during a specific subframe.

[0015] According to one or more aspects of this disclosure, a power management circuit and display device can be provided that can reduce power consumption by changing the voltage output from at least one voltage conversion circuit during a specific subframe.

[0016] According to one or more aspects of this disclosure, a power management circuit and display device may be provided that allows forced continuous current mode (FCCM) to operate during a period when the voltage output from a voltage conversion circuit is changed, and reduces time delay when the voltage is changed.

[0017] The effects or features of the aspects, examples, and embodiments described herein are not limited thereto, and additional effects or features will become apparent to those skilled in the art from the following description. Attached Figure Description

[0018] The aspects, examples, and embodiments discussed herein will be more fully understood in light of the detailed description and accompanying drawings provided below. It should be understood here that the aspects, examples, and embodiments described herein are not intended to be limiting, as alternative aspects, examples, and embodiments may be added to, omitted from, or modified in terms of elements, structures, configurations, etc. In the accompanying drawings:

[0019] Figure 1 This is a system configuration of an example display device based on various aspects of this disclosure;

[0020] Figure 2 An example configuration of a display device according to various aspects of this disclosure is shown;

[0021] Figure 3 This is an example circuit configuration of a sub-pixel in a display device according to aspects of this disclosure;

[0022] Figure 4 Example operation timing diagrams of subpixels in refresh frames and anode reset frames in a display device according to various aspects of this disclosure are shown.

[0023] Figure 5 Example power management circuits according to various aspects of this disclosure are shown;

[0024] Figures 6 to 10 An example voltage conversion circuit included in a power management circuit is shown according to various aspects of this disclosure;

[0025] Figures 11 to 13 An example mode control circuit included in a power management circuit is shown according to various aspects of this disclosure;

[0026] Figure 14 and Figure 15 Examples of a first drive voltage supply circuit and a second drive voltage supply circuit, including a power management circuit, are shown according to various aspects of this disclosure; and

[0027] Figure 16 and Figure 17 Example gate drive circuits according to various aspects of this disclosure are shown. Detailed Implementation

[0028] Reference will now be made in detail to exemplary embodiments of this disclosure, examples or aspects of which may be illustrated in the accompanying drawings. In the following description, unless otherwise stated, the structures, implementations, methods, and operations described herein are not limited to the specific examples, aspects, and embodiments set forth herein, and may be varied as is known in the art. Unless otherwise stated, the same reference numerals always denote the same elements. The names of the corresponding elements used in the following explanation are chosen solely for ease of writing the specification and may therefore differ from the names used in actual products. The advantages and features of this disclosure and its implementation methods will be illustrated by the exemplary embodiments described below with reference to the accompanying drawings. However, this disclosure may be embodied in different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure is thorough and complete enough to assist those skilled in the art in fully understanding the scope of this disclosure. Furthermore, the scope of protection of this disclosure is defined by the claims and their equivalents. In the following description, detailed descriptions of relevant known functions or configurations may be omitted where such detailed descriptions may unnecessarily obscure aspects of this disclosure. The shapes, dimensions, ratios, angles, quantities, etc., shown in the drawings for describing various exemplary embodiments of this disclosure are given by way of example only. Therefore, this disclosure is not limited to the illustrations in the drawings. Terms such as “comprising,” “having,” “including,” “constituting,” “composed of,” and “formed by” as used herein are generally intended to allow for the addition of additional components, unless these terms are used only with the term “only.” As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0029] Although the terms “first,” “second,” A, B, (a), (b), etc., may be used herein to describe various elements, these elements should not be construed as being limited by these terms, as they are not used to define a particular order or priority. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0030] When referring to the first element and the second element as "connected or coupled," "in contact," or "overlapping," it should be explained that not only are the first element and the second element "directly connected or coupled," "in contact," or "overlapping," but a third element may also be "inserted" between the first element and the second element, or the first element and the second element may be "connected or coupled," "in contact," or "overlapping" via a third element. Here, the second element may be included in at least one of two or more elements that are "connected or coupled," "in contact," or "overlapping" with each other.

[0031] When describing positional relationships, such as when using terms like "above," "over," "below," "on top," "beside," or "adjacent" to describe the positional relationship between two parts, one or more other parts may be located between the two parts, unless more restrictive terms such as "immediately," "directly," or "nearly" are used. For example, when an element or layer is placed "on" another element or layer, a third element or layer may be inserted between them. Furthermore, the terms "left," "right," "top," "bottom," "down," "up," "upper," "lower," etc., refer to any frame of reference.

[0032] Furthermore, when referring to any size, relative size, etc., even if no specific description is specified, the numerical or corresponding information of the component or feature (e.g., level, range, etc.) should be considered to include tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external shocks, noise, etc.). In addition, the term "may" fully encompasses all the meanings of the term "able to".

[0033] In the following description, various exemplary aspects of this disclosure are described in detail with reference to the accompanying drawings. Reference numerals for each element in the drawings are used; the same elements may be shown in other drawings, and unless otherwise stated, the same reference numerals may refer to the same elements. Identical or similar elements may be represented by the same reference numerals, even if they are depicted in different drawings. Furthermore, for ease of description, the scale, dimensions, size, and thickness of each element shown in the drawings may differ from the actual scale, dimensions, size, and thickness; therefore, aspects of this disclosure are not limited to the scale, dimensions, size, and thickness shown in the drawings.

[0034] Figure 1 This is an example display device 100 system configuration based on various aspects of this disclosure.

[0035] refer to Figure 1 In one or more example embodiments, the display device 100 may include a display panel 110 and at least one driving circuit for driving the display panel 110.

[0036] At least one driving circuit may include a data driving circuit 120 and a gate driving circuit 130, and further includes a controller 140 configured to control the data driving circuit 120 and the gate driving circuit 130, and a power management circuit 150 configured to supply driving voltage.

[0037] The display panel 110 may include multiple sub-pixels SP connected to multiple data lines DL and multiple gate lines GL.

[0038] Display panel 110 may include a display area DA for displaying images and a non-display area NDA located outside the display area DA. For example, multiple sub-pixels SP for displaying images may be disposed in the display area DA of display panel 110. Driving circuits 120, 130, 140, and 150 may be electrically connected to the non-display area NDA of display panel 110, or at least one of driving circuits 120, 130, 140, and 150 may be mounted on the non-display area NDA of display panel 110. A pad portion to which at least one integrated circuit or at least one printed circuit is connected may be disposed in the non-display area NDA.

[0039] The data driving circuit 120 can be a circuit used to drive multiple data lines DL and provide data signals to the multiple data lines DL. The gate driving circuit 130 can be a circuit used to drive multiple gate lines GL and provide gate signals to the multiple gate lines GL.

[0040] For example, the gate signal may include at least one scan gate signal and at least one emit control gate signal.

[0041] The controller 140 can provide at least one data control signal DCS and at least one gate control signal GCS to the data drive circuit 120 and the gate drive circuit 130, respectively, to control the operation timing of the data drive circuit 120 and the gate drive circuit 130.

[0042] The controller 140 can control the initiation of pixel scanning operations according to the corresponding timing set in each frame. The controller 140 can convert image data received from external devices or systems (e.g., host system 160) into a data signal form that can be read by the data driving circuit 120, and then supply the converted image data DATA to the data driving circuit 120. The controller 140 can control data driving to occur at the time set for scanning one or more corresponding pixels.

[0043] The controller 140 can receive display drive control signals and image data from the external host system 160. For example, the display drive control signals may include vertical synchronization signals, horizontal synchronization signals, input data enable signals, clock signals, etc. The controller 140 can generate several types of control signals based on the display drive control signals received from the host system 160, such as data drive control signals DCS and gate drive control signals GCS, and output the generated control signals DCS and GCS to the data drive circuit 120 and the gate drive circuit 130.

[0044] The controller 140 can be implemented in a separate component from the data drive circuit 120, or integrated with the data drive circuit 120, so that the timing controller 140 and the data drive circuit 120 can be implemented in a single integrated circuit.

[0045] The data driving circuit 120 can drive multiple data lines DL by receiving image data DATA from the controller 140 and supplying data voltage to multiple data lines DL. The data driving circuit 120 can also be called a source driving circuit.

[0046] The data drive circuit 120 may include one or more source driver integrated circuits (SDICs).

[0047] The gate drive circuit 130 can output a gate signal with an on-state voltage level or a gate signal with an off-state voltage level under the control of the controller 140. The gate drive circuit 130 can sequentially drive multiple gate lines GL by supplying gate signals with turn-on voltage levels to multiple gate lines GL in sequence.

[0048] In one or more aspects, each source driver integrated circuit SDIC and gate driver circuit 130 may be connected to the display panel 110 via tape automatic bonding (TAB) technology, or to conductive pads such as bonding pads of the display panel 110 via chip-on-glass (COG) technology or chip-on-panel (COP) technology, or to the display panel 110 via chip-on-film (COF) technology.

[0049] In one or more aspects, the gate driving circuit 130 included in the display device 100 may be disposed in the non-display area NDA of the display panel 110 using gate in-plane (GIP) technology. The gate driving circuit 130 may be disposed on the substrate SUB or connected to the substrate SUB.

[0050] The gate drive circuit 130 may include multiple stages, and each of the multiple stages may supply at least one gate signal to at least one corresponding sub-pixel among the multiple sub-pixels SP.

[0051] In an example where the gate drive circuit 130 is implemented using gate-in-board (GIP) technology, each of the multiple stages can be configured with multiple GIP circuits.

[0052] In one or more aspects, at least one of the data driving circuit 120 and the gate driving circuit 130 may be disposed in the display area DA. When the gate driving circuit 130 drives one or more specific gate lines, the data driving circuit 120 can convert the image data DATA received from the controller 140 into an analog data voltage and supply the resulting data voltage to the multiple data lines DL.

[0053] The power management circuit 150 may include multiple voltage conversion circuits and multiple drive voltage supply circuits, with each drive voltage supply circuit connected to a corresponding one of the multiple voltage conversion circuits. For example, each of the multiple drive voltage supply circuits may supply a corresponding drive voltage to at least one of the display panel 110, data drive circuit 120, gate drive circuit 130, and controller 140.

[0054] For example, a first drive voltage supply circuit among a plurality of drive voltage supply circuits may be configured to supply a first drive voltage to the data drive circuit 120. In this example, the power management circuit 150 may cause the first drive voltage supply circuit to be deactivated during at least one first subframe in at least one frame corresponding to image data DATA.

[0055] Furthermore, a second drive voltage supply circuit among the plurality of drive voltage supply circuits can be configured to supply a second drive voltage to the data drive circuit 120. In this example, the power management circuit 150 can cause the second drive voltage supply circuit to be deactivated during at least one second subframe in at least one frame corresponding to the image data DATA.

[0056] For example, the first subframe could be an anodized reset frame, and the second subframe could be a refresh frame.

[0057] For example, the first driving voltage may be a reference voltage used to generate a gamma voltage in the data driving circuit 120, and the second driving voltage may be a dwell voltage VPAK supplied to multiple data lines DL during at least one first subframe in the data driving circuit 120.

[0058] In the following text, the first drive voltage supply circuit can be described as a reference voltage supply circuit, and the second drive voltage supply circuit can be described as a dwell voltage supply circuit.

[0059] In one or more aspects, the first drive voltage supply circuit may include a first reference voltage supply circuit configured to generate a reference voltage having a high voltage level VREF_H and supply the generated reference voltage having a high voltage level VREF_H to the data drive circuit 120, and a second reference voltage supply circuit configured to generate a reference voltage having a low voltage level VREF_L and supply the generated reference voltage having a low voltage level VREF_L to the data drive circuit 120.

[0060] However, the aspects of this disclosure are not limited thereto. For example, a single circuit (e.g., a first drive voltage supply circuit) may be employed, and in this example, the first drive voltage supply circuit may generate and supply a reference voltage having a high voltage level VREF_H and a reference voltage having a low voltage level VREF_L.

[0061] In one or more aspects, by changing the voltage in at least one first subframe and at least one second subframe, a first voltage conversion circuit in the power management circuit 150, connected to a first drive voltage supply circuit among a plurality of drive voltage supply circuits, can output voltages with different levels. In this embodiment, the display device 100, the power management circuit 150, or the first voltage conversion circuit can operate in forced continuous current mode (FCCM) during the corresponding voltage changing cycle.

[0062] In one or more aspects, the display device 100 may be a display including a backlight unit (such as a liquid crystal display), or it may be a self-emitting display (such as an organic light-emitting diode (OLED) display, a quantum dot display, a micro light-emitting diode display, etc.).

[0063] In one or more aspects, the display panel 110 may have a top-emitting structure, a bottom-emitting structure, or a dual-sided-emitting structure.

[0064] Figure 2 An example configuration of a display device 100 according to various aspects of this disclosure is shown.

[0065] refer to Figure 2 In one or more example embodiments, the data driving circuit 120 and the gate driving circuit 130 included in the display device 100 may be implemented using chip-on-film (COF) technology and gate-in-plate (GIP) technology, respectively. However, aspects of this disclosure are not limited thereto.

[0066] In an example where the gate drive circuit 130 is implemented using GIP technology, multiple gate drive integrated circuits (GDICs) included in the gate drive circuit 130 can be directly disposed in the non-display area NDA of the display panel 110. In one or more aspects, one or more source drive integrated circuits (SDICs) included in the data drive circuit 120 can be mounted on one or more corresponding source films (SFs), and one side of each source film (SF) can be electrically connected to the display panel 110.

[0067] Figure 2 The display device 100 shown includes a plurality of source films SF and a plurality of source driver integrated circuits SDIC respectively disposed on the plurality of source films SF, but the aspects of this disclosure are not limited thereto. For example, the display device 100 may include a source film SF and a source driver integrated circuit SDIC disposed on a source film SF.

[0068] In one or more aspects, the other side of each source film SF on which the corresponding source driver integrated circuit SDIC is mounted can be connected to at least one source printed circuit board SPCB. For example, the side of each source film SF on which the corresponding source driver integrated circuit SDIC is mounted can be electrically connected to the display panel 110, and the other side can be electrically connected to at least one source printed circuit board SPCB.

[0069] The controller 140 and the sub-power control circuit 210 can be mounted on a control printed circuit board (CPCB). The controller 140 can control the operation of the data drive circuit 120 and the gate drive circuit 130. The sub-power control circuit 210 can provide various levels of voltage or current to the display panel 110, the gate drive circuit 130, the data drive circuit 120, etc., or control the level of the voltage or current to be supplied.

[0070] At least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) may be electrically connected to each other via at least one connector (such as a flexible printed circuit board (FPC), a flexible flat cable (FFC), etc.). In one or more aspects, at least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) may be integrated into a single printed circuit board.

[0071] The display device 100 may further include a setup board 230 electrically connected to a control printed circuit board (CPCB). The setup board 230 may be referred to as a power board. A main power management circuit 220 configured to manage the overall power of the display device 100 may be mounted on the setup board 230. The main power management circuit 220 may interoperate with the sub-power control circuit 210.

[0072] In one or more aspects, the power management circuit 150 may include at least one of a sub-power control circuit 210 and a main power management circuit 220.

[0073] Figure 3 This is an example circuit configuration of the sub-pixel SP in the display device 100 according to aspects of this disclosure.

[0074] Reference Figure 3 In one or more exemplary embodiments, a sub-pixel SP may include a light-emitting element ED and a driving transistor DRT configured to drive the light-emitting element ED. For example, the light-emitting element ED may be a self-emitting element, such as an organic light-emitting diode (OLED). However, aspects of this disclosure are not limited thereto. For example, the light-emitting element ED may be an inorganic light-emitting diode, a quantum dot light-emitting diode, a micro light-emitting diode, a mini light-emitting diode, etc.

[0075] An ED (Emitting Light Element) may include a pixel electrode, a common electrode, and an emitting layer located between the pixel electrode and the common electrode.

[0076] The pixel electrode of the light-emitting element (ED) can be an electrode set for each sub-pixel (SP), and the common electrode can be an electrode set for all or some of the multiple sub-pixels (SP). For example, the pixel electrode can be an anode electrode, and the common electrode can be a cathode electrode. In another example, the pixel electrode can be a cathode electrode, and the common electrode can be an anode electrode.

[0077] Reference Figure 3 The pixel electrode of the light-emitting element ED can be connected to the fourth node N4, and its common electrode can be connected to the low drive voltage line VSSL for delivering the low drive voltage VSSEL.

[0078] In addition to the driving transistor DRT, the sub-pixel SP may further include one or more transistors. (See reference...) Figure 3 The sub-pixel SP may further include first to sixth transistors T1 to T6.

[0079] The sub-pixel SP may further include a storage capacitor Cstg, which is configured to apply a high drive voltage VDDEL delivered via the high drive voltage line VDDL to the gate node of the drive transistor DRT within a frame period.

[0080] The storage capacitor Cstg may include one end (or electrode) electrically connected to the first node N1 and the other end (or electrode) electrically connected to the high drive voltage line VDDL.

[0081] Figure 3 The diagram shows a sub-pixel SP with a 7T1C structure, but the present disclosure is not limited thereto. For example, the sub-pixel can be configured with various circuit structures, such as a 2T1C structure, a 3T1C structure, an 8TO2 structure in which two of the eight transistors are oxide transistors, etc.

[0082] The driving transistor DRT may include a first node N1, a second node N2, and a third node N3. For example, the first node N1 may be the gate node of the driving transistor DRT, the second node N2 may be the source or drain node of the driving transistor DRT, and the third node N3 may be the drain or source node of the driving transistor DRT.

[0083] The first transistor T1 can receive the second scan gate signal SCAN2 with a conduction voltage level supplied by the gate drive circuit 130, and control the connection between the second node N2 and the data line DL.

[0084] For example, the data line DL can be supplied with a dwell voltage VPAK during the first subframe (e.g., an anode reset frame) and a data voltage VDATA during the second subframe (e.g., a refresh frame).

[0085] The second transistor T2 can receive the emit control gate signal EM with a conduction voltage level supplied by the gate drive circuit 130, and control the connection between the second node N2 and the high drive voltage line VDDL.

[0086] The third transistor T3 can receive the first scan gate signal SCAN1 with a conduction voltage level supplied by the gate drive circuit 130, and control the connection between the first node N1 and the third node N3.

[0087] The fourth transistor T4 can receive the third scan gate signal SCAN3 with a conduction voltage level supplied by the gate drive circuit 130, and control the connection between the third node N3 and the initialization voltage line INIL.

[0088] For example, at least one voltage, namely the initialization voltage VINI and the bias voltage VOBS, can be supplied to the initialization voltage line INIL, having a voltage level higher than the initialization voltage VINI.

[0089] The fifth transistor T5 can receive an emit control gate signal EM having a turn-on voltage level supplied by the gate drive circuit 130, and control the connection between the third node N3 and the fourth node N4 connected to the pixel electrode of the light-emitting element ED.

[0090] The sixth transistor T6 can receive the third scan gate signal SCAN3 with a turn-on voltage level supplied by the gate drive circuit 130, and control the connection between the fourth node N4 and the reset voltage line VARL for delivering the anode reset voltage VAR.

[0091] Reference Figure 3 The fourth transistor T4 and the sixth transistor T6 can be provided with the third scan gate signal SCAN3 through a gate line GL.

[0092] In one or more aspects, the fourth transistor T4 and the sixth transistor T6 can be provided with the third scan gate signal SCAN3 via different gate lines GL.

[0093] For example, when Figure 3 When the sub-pixel SP is the nth sub-pixel (where n is an integer equal to or greater than 1), the fourth transistor T4 can receive the third scan gate signal SCAN3 through the gate line GL of the nth stage among the multiple stages in the gate drive circuit 130, and the sixth transistor T6 can receive the third scan gate signal SCAN3 through the gate line GL of the (n+1)th stage among the multiple stages.

[0094] In one or more aspects, a second initialization voltage VAR2 may be applied to the initialization voltage line INIL during a first subframe (e.g., an anode reset frame), and a first initialization voltage VAR1 having a higher voltage level than the second initialization voltage VAR2 may be applied during a second subframe (e.g., a refresh frame). However, aspects of this disclosure are not limited thereto.

[0095] When the transistors applying these gate signals are n-type transistors, the corresponding on-state voltage levels of the first scan gate signal SCAN1, the second scan gate signal SCAN2, the third scan gate signal SCAN3, and the emitter control gate signal EM can be high voltage levels, while when the transistors are p-type transistors, they can be low voltage levels.

[0096] Reference Figure 3 For example, the driving transistor DRT, the first transistor T1, the second transistor T2, and the fourth to sixth transistors T4 to T6 can be p-type transistors, and the third transistor T3 can be an n-type transistor. However, aspects of this disclosure are not limited thereto. For example, the third transistor T3 can be a p-type transistor, or at least one of the driving transistor DRT, the first transistor T1, the second transistor T2, and the fourth to sixth transistors T4 to T6 can be an n-type transistor.

[0097] In one or more aspects, the third transistor T3 may be an oxide transistor, and the driving transistor DRT, the first transistor T1, the second transistor T2, and the fourth to sixth transistors T4 to T6 may be low-temperature polycrystalline silicon (LTPS) transistors. However, the aspects of this disclosure are not limited thereto. For example, the third transistor T3 may be an LTPS transistor, or at least one of the driving transistor DRT, the first transistor T1, the second transistor T2, and the fourth to sixth transistors T4 to T6 may be an oxide transistor.

[0098] Figure 4 An example operation timing diagram of a subpixel in a refresh frame RF and an anode reset frame AR in a display device 100 according to various aspects of the present disclosure is shown.

[0099] refer to Figure 3 and Figure 4 In one or more example embodiments, the period of the refresh frame RF may include a first conduction bias sub-period OBS1 and a second conduction bias sub-period OBS2 configured to apply a high voltage level bias voltage VOBS to the third node N3 of the driving transistor DRT, and a sampling sub-period Sampling configured to apply a data voltage VDATA to the second node N2 of the driving transistor DRT.

[0100] In addition, the period of the anode reset frame AR may include a third conduction bias sub-cycle OBS3 and a fourth conduction bias sub-cycle OBS4, which are set to apply a high-voltage level bias voltage VOBS to the third node N3 of the driving transistor DRT.

[0101] For example, the conduction bias sub-cycles OBS1, OBS2, OBS3, and OBS4 can be periods set to mitigate hysteresis effects that may occur in the driving transistor DRT and improve response characteristics.

[0102] Reference Figure 3 and Figure 4 For example, the bias voltage VOBS can be applied to the initialization voltage line INIL during the on-bias sub-cycles OBS1, OBS2, OBS3 and OBS4 in each of the refresh frame RF and the anode reset frame AR, and the initialization voltage VINI can be applied to the initialization voltage line INIL during the remaining sub-cycles other than the on-bias sub-cycles OBS1, OBS2, OBS3 and OBS4.

[0103] During the sampling sub-cycle, the emit control gate signal EM with a cutoff voltage level can be applied to the second transistor T2 and the fifth transistor T5, and the third gate scan signal SCAN3 with a cutoff voltage level can be applied to the fourth transistor T4 and the sixth transistor T6.

[0104] During the sampling sub-cycle, a first scan gate signal SCAN1 with a conduction voltage level can be applied to the third transistor T3, and a second scan gate signal SCAN2 with a conduction voltage level can be applied to the first transistor T1.

[0105] For example, when the driving transistor DRT, the first transistor T1, and the third transistor T3 are turned on during the sampling sub-cycle, the data voltage VDATA can be supplied to the second node N2 of the driving transistor DRT, thereby supplying a voltage corresponding to the data voltage VDATA to one end (or electrode) of the storage capacitor Cstg.

[0106] When the second transistor T2 and the fifth transistor T5 are turned off during the anode reset frame AR period, the first scan gate signal SCAN1 with a cutoff voltage level can be applied to the third transistor T3, and the second scan gate signal SCAN2 with a cutoff voltage level can be applied to the first transistor T1.

[0107] During the time period of each of the refresh frame RF and the anode reset frame AR, the third scan gate signal SCAN3 applied to the fourth transistor T4 and the sixth transistor T6 may have at least one on-state voltage level and at least one off-state voltage level.

[0108] The fourth transistor T4 can be turned on in response to the third scan gate signal SCAN3, and a bias voltage VOBS with a high voltage level can be applied to the third node N3 of the driving transistor DRT.

[0109] The sixth transistor T6 can be turned on in response to the third scan gate signal SCAN3, and the anode reset voltage VAR can be applied to the pixel electrode (e.g., the anode electrode) of the light-emitting element ED.

[0110] Reference Figure 3 and Figure 4 A first initialization voltage VAR1 may be applied to the initialization voltage line INIL during the refresh frame RF period, and a second initialization voltage VAR2 having a lower voltage level than the first initialization voltage VAR1 may be applied to the initialization voltage line INIL during the anode reset frame AR period. However, aspects of this disclosure are not limited thereto.

[0111] In one or more aspects, a data voltage VDATA can be applied to the data line DL during the refresh frame RF period, and a dwell voltage VPK can be applied to the data line DL during the anode reset frame AR period.

[0112] refer to Figure 4 The dwell voltage VPK can be designed to have a higher voltage level than the data voltage VDATA.

[0113] Figure 5 An example configuration of the power management circuit 150 according to various aspects of this disclosure is explained.

[0114] refer to Figure 5 In one or more example embodiments, the power management circuit 150 may include a first voltage conversion circuit 501 configured to convert an initial voltage supplied by the system power supply 500 into a first input voltage VI1, a second voltage conversion circuit 502 configured to convert the initial voltage into a second input voltage VI2, a third voltage conversion circuit 503 configured to convert the initial voltage into a third input voltage VI3, and a fourth voltage conversion circuit 504 configured to convert the initial voltage into a fourth input voltage VI4.

[0115] Figure 5 The system power supply 500, configured to supply an initial voltage, is shown located external to the power management circuitry 150, but aspects of this disclosure are not limited thereto. For example, the system power supply 500 and the power management circuitry 150 may be integrated into a single circuit.

[0116] The first voltage conversion circuit 501 can supply a first voltage level with a first input voltage VI1 during the refresh frame RF, and can supply a first input voltage VI1 with a second voltage level lower than the first voltage level during the anode reset frame AR by changing the first voltage level of the first input voltage VI1 to a second voltage level. Therefore, the power management circuit 150 can provide the advantage of reduced power consumption.

[0117] The second voltage conversion circuit 502 can supply a second input voltage VI2 having a third voltage level higher than the first voltage level during the refresh frame RF and the anode reset frame AR. The third voltage conversion circuit 503 can supply a third input voltage VI3 having a fourth voltage level lower than the second voltage level. The fourth voltage conversion circuit 504 can supply a fourth input voltage VI4 having a fifth voltage level higher than the third voltage level.

[0118] For example, the first input voltage VI1 can be the source drive voltage SVDD, and the first voltage conversion circuit 501 can directly supply the source drive voltage SVDD to the data drive circuit 120.

[0119] For example, the fourth input voltage VI4 can be the power supply voltage VCC, and the fourth voltage conversion circuit 504 can directly supply the power supply voltage VCC to the data drive circuit 120 and the controller 140.

[0120] The first voltage conversion circuit 501 can operate in forced continuous current mode (FCCM) based on a mode control signal received from the controller 140 during a first voltage change cycle and a second voltage change cycle. During the first voltage change cycle, the first input voltage VI1 changes from a first voltage level to a second voltage level, and during the second voltage change cycle, the first input voltage VI1 changes from a second voltage level back to a first voltage level. Therefore, the power management circuit 150 can provide the advantage of reducing time delays when changing the first input voltage VI1.

[0121] Each of the first voltage conversion circuit 501, the second voltage conversion circuit 502, the third voltage conversion circuit 503, and the fourth voltage conversion circuit 504 may include at least one of a buck converter, a boost converter, and a buck-boost converter.

[0122] refer to Figure 5 The power management circuit 150 may further include a first drive voltage supply circuit 511 and 512 configured to receive a first input voltage VI1 and generate a reference voltage (VREF_H or VREF_L) as a first drive voltage, and a second drive voltage supply circuit 521 configured to receive a second input voltage VI2 and generate a dwell voltage VPK as a second drive voltage.

[0123] Furthermore, the power management circuit 150 may further include at least one third drive voltage supply circuit 531, 532, 533, 534 and / or 535, which is configured to receive a corresponding one of the second input voltage VI2 and the third input voltage VI3 and generate the third drive voltage.

[0124] Furthermore, the power management circuit 150 may further include at least one fourth drive voltage supply circuit 541 and / or 542, which is configured to receive a corresponding one of the second input voltage VI2 and the third input voltage VI3 and generate the fourth drive voltage.

[0125] For example, the third driving voltage can be a DC voltage directly supplied to the sub-pixel, and the fourth driving voltage can be a DC voltage supplied to the gate driving circuit 130.

[0126] The first drive voltage supply circuits 511 and 512 may include a first reference voltage supply circuit 511 configured to generate a reference voltage with a high voltage level VREF_H and supply the generated reference voltage with a high voltage level VREF_H to the data drive circuit 120, and a second reference voltage supply circuit 512 configured to generate a reference voltage with a low voltage level VREF_L and supply the generated reference voltage with a low voltage level VREF_L to the data drive circuit 120.

[0127] The power management circuit 150 can disable the first reference voltage supply circuit 511 and the second reference voltage supply circuit 512 during the anode reset frame AR period. Therefore, the power management circuit 150 can provide the advantage of reduced power consumption.

[0128] The second drive voltage supply circuit 521 can generate a dwell voltage VPAK based on the second input voltage VI2 and supply the generated dwell voltage VPAK to the data drive circuit 120.

[0129] The power management circuit 150 can disable the second drive voltage supply circuit 521 during the refresh frame RF period. Therefore, the power management circuit 150 can provide the advantage of reduced power consumption.

[0130] The third driving voltage may be a voltage supplied to the source or drain node of at least one transistor included in each of the plurality of sub-pixels SP, and may include at least one of bias voltage VOBS, initialization voltage VINI, and anode reset voltage VAR.

[0131] At least one third drive voltage supply circuit may include a bias voltage supply circuit 531, an initialization voltage supply circuit 532, and at least one reset voltage supply circuit 533, 534, and / or 535.

[0132] The bias voltage supply circuit 531 can receive the second input voltage VI2 and generate a bias voltage VOBS, and supply the generated bias voltage VOBS to the fourth transistor T4 of the sub-pixel SP via the initialization voltage line INIL (see [link to circuit 531]). Figure 4 (Configuration).

[0133] The initialization voltage supply circuit 532 can receive the third input voltage VI3 and generate an initialization voltage VINI, and supply the generated initialization voltage VINI to the fourth transistor T4 of the sub-pixel SP through the initialization voltage line INIL at a time different from the time of supplying the bias voltage VOBS.

[0134] At least one reset voltage supply circuit 533, 534 and / or 535 can receive a third input voltage VI3 and generate an anode reset voltage VAR, and supply the generated anode reset voltage VAR to the sixth transistor T6 of the sub-pixel SP via the reset voltage line VARL (see Figure 4 (Configuration).

[0135] In one or more aspects, the power management circuit 150 may reduce power consumption by disabling the initialization voltage supply circuit 532 during the period of the anode reset frame AR, but the aspects of this disclosure are not limited thereto.

[0136] Reference Figure 5 At least one reset voltage supply circuit 533, 534 and / or 535 may include a first reset voltage supply circuit 533, a second reset voltage supply circuit 534 and a third reset voltage supply circuit 535, which may correspond to sub-pixels SP of different colors, but aspects of this disclosure are not limited thereto.

[0137] The first reset voltage supply circuit 533 can supply the anode reset voltage VAR_R corresponding to the first color (e.g., red) to the sub-pixel SP of the first color.

[0138] The second reset voltage supply circuit 534 can supply the anode reset voltage VAR_B corresponding to the second color (e.g., blue) to the sub-pixel SP of the second color.

[0139] The third reset voltage supply circuit 535 can supply the anode reset voltage VAR_G corresponding to the third color (e.g., green) to the sub-pixel SP of the third color.

[0140] In one or more aspects, at least one reset voltage supply circuit 533, 534 and / or 535 may supply an anode reset voltage VAR with different voltage levels in each of the refresh frame RF and the anode reset frame AR.

[0141] The fourth driving voltage may be the voltage supplied to the gate driving circuit 130, and includes at least one of the gate high voltage VGH and the gate low voltage VGL.

[0142] refer to Figure 5 At least one fourth drive voltage supply circuit may include a first gate supply circuit 541 and a second gate supply circuit 542.

[0143] The first gate supply circuit 541 can receive the second input voltage VI2 and generate a gate high voltage VGH, and supply the generated gate high voltage VGH to the gate drive circuit 130.

[0144] The second gate supply circuit 542 can receive the third input voltage VI3 and generate a gate low voltage VGL, and supply the generated gate low voltage VGL to the gate drive circuit 130.

[0145] The gate drive circuit 130 can generate a gate signal to be supplied through the gate line GL to the corresponding gate node of at least one transistor among a plurality of sub-pixels SP based on the gate high voltage VGH and the gate low voltage VGL.

[0146] refer to Figure 3The gate signals may include a first scan gate signal SCAN1, a second scan gate signal SCAN2, a third scan gate signal SCAN3, and an emit control gate signal EM.

[0147] In one or more aspects, at least one fourth drive voltage supply circuit 541 and / or 542 may supply the gate drive circuit 130 with a gate high voltage VGH and a gate low voltage VGL having different voltage levels.

[0148] For example, the gate drive circuit 130 can use a first gate high voltage and a first gate low voltage supplied by at least one fourth drive voltage supply circuit 541 and / or 542 to generate first to third scan gate signals SCAN1 to SCAN3, and use a second gate high voltage and a second gate low voltage supplied by at least one fourth drive voltage supply circuit 541 and / or 542 to generate an emit control gate signal EM.

[0149] Furthermore, the gate drive circuit 130 can use a first gate high voltage and a first gate low voltage to generate gate signals (e.g., SCAN1) for controlling one or more oxide transistors in the sub-pixel SP, and can use a second gate high voltage and a second gate low voltage to generate gate signals (e.g., SCAN2, SCAN3, and EM) for controlling one or more LTPS transistors in the sub-pixel SP.

[0150] However, the present disclosure is not limited thereto. For example, a gate high voltage VGH and a gate low voltage VGL can be used to generate the first to third scan gate signals SCAN1 to SCAN3 and the emit control gate signal EM.

[0151] Figures 6 to 10 An example voltage conversion circuit included in a power management circuit 150 according to various aspects of this disclosure is shown.

[0152] Figure 6 An example configuration of the first voltage conversion circuit 501 and the second voltage conversion circuit 502 is shown. Figure 7 An example configuration of the third voltage conversion circuit 503 is shown. Figure 8 An example configuration of the fourth voltage conversion circuit 504 is shown.

[0153] Figure 9 Show Figures 6 to 8 Example control circuits included in each of the second voltage conversion circuit 502, the third voltage conversion circuit 503, and the fourth voltage conversion circuit 504 shown. Figure 10 Showing includes Figure 6 Example control circuit in the first voltage conversion circuit 501.

[0154] refer to Figure 6 In one or more example embodiments, each of the first voltage conversion circuit 501 and the second voltage conversion circuit 502 may include a first capacitor C11 connected to a first node N11 to which an initial voltage is applied from the system power supply 500, an inductor L11 connected to the first node N11 and the second node N21, a first transistor T11 connected to a second node, a second transistor T21 connected to the second node N21 and the third node N31, and a second capacitor C21 connected to the third node N31.

[0155] refer to Figure 6 Each of the first voltage conversion circuit 501 and the second voltage conversion circuit 502 can be a boost converter, which is configured to alternately turn on the first transistor T11 and the second transistor T21 to output a DC voltage (e.g., the first input voltage VI1 or the second input voltage VI2) in which the input voltage is boosted.

[0156] refer to Figure 7 In one or more example embodiments, the third voltage conversion circuit 503 may include a first capacitor C12 connected to a first node N12 to which an initial voltage is applied, a first transistor T12 connected to the first node N12 and the second node N22, an inductor L12 connected to the second node N22, a second transistor T22 connected to the second node N22 and the third node N32, and a second capacitor C22 connected to the third node N32.

[0157] refer to Figure 7 The third voltage conversion circuit 503 can be a buck-boost converter, which is configured to alternately turn on the first transistor T12 and the second transistor T22 to output a DC voltage (e.g., the third input voltage VI3) in which the input voltage is boosted or bucked.

[0158] In one or more aspects, the third voltage conversion circuit 503 can output a DC voltage with the opposite polarity to the input voltage. For example, the third voltage conversion circuit 503 can output a DC voltage as a negative voltage (i.e., a negative voltage) by pulling down an input voltage that is a positive voltage (i.e., + voltage).

[0159] refer to Figure 8 In one or more example embodiments, the fourth voltage conversion circuit 504 may include a first capacitor C13 connected to a first node N13 to which an initial voltage is applied, a first transistor T13 connected to the first node N13 and the second node N23, a second transistor T23 connected to the second node N23, an inductor L13 connected to the second node N23 and the third node N33, and a second capacitor C23 connected to the third node N33.

[0160] refer to Figure 8 The fourth voltage conversion circuit 504 can be a buck converter, which is configured to alternately turn on the first transistor T13 and the second transistor T23 to output a DC voltage (e.g., the fourth input voltage VI4) in which the input voltage is stepped down.

[0161] refer to Figure 9 and Figure 10 In one or more example embodiments, each of the first voltage conversion circuit 501, the second voltage conversion circuit 502, the third voltage conversion circuit 503, and the fourth voltage conversion circuit 504 may include a current sensing circuit 910, an oscillator 920, an adder 930, a first resistor R1, a second resistor R2, an error amplifier 940, a comparator 950, and a switch control circuit 960.

[0162] The current sensing circuit 910 can detect the current at the second node N2 where the first transistor and the second transistor are connected.

[0163] For example, the corresponding current sensing circuits 910 included in the first voltage conversion circuit 501, the second voltage conversion circuit 502, the third voltage conversion circuit 503, and the fourth voltage conversion circuit 504 can respectively detect the current at the second node N21 of the first voltage conversion circuit 501, the second node N21 of the second voltage conversion circuit 502, the second node N22 of the third voltage conversion circuit 503, and the second node N23 of the fourth voltage conversion circuit 504.

[0164] For example, the current sensing circuit 910 can be an inductor-based current sensing circuit.

[0165] Adder 930 can output a signal generated by reflecting or adding the slope value of the signal output from current sensing circuit 910 to a triangular wave output from oscillator 920.

[0166] The first resistor R1 and the second resistor R2 can supply the divided output voltage based on the voltage supplied from the fourth node N4.

[0167] For example, the corresponding first resistor R1 and second resistor R2 included in the first voltage conversion circuit 501, the second voltage conversion circuit 502, the third voltage conversion circuit 503, and the fourth voltage conversion circuit 504 can supply a divided output voltage based on the voltage supplied from the fourth node N41 of the first voltage conversion circuit 501, the fourth node N41 of the second voltage conversion circuit 502, the fourth node N42 of the third voltage conversion circuit 503, and the fourth node N43 of the fourth voltage conversion circuit 504, respectively.

[0168] The error amplifier 940 can supply an error amplification signal based on a preset amplifier reference voltage VREFA and a divided output voltage provided from the first resistor R1 and the second resistor R2. For example, the error amplification signal can correspond to a signal generated by amplifying the difference between the amplifier reference voltage VREFA and the divided output voltage.

[0169] For example, the amplifier reference voltage VREFA may include a first amplifier reference voltage applied to the refresh frame RF and a second amplifier reference voltage applied to the anode reset frame AR having a voltage level lower than the first amplifier reference voltage, and a corresponding one of the first amplifier reference voltage and the second amplifier reference voltage may be supplied to the error amplifier 940 based on the control operation of the controller 140.

[0170] For example, at least two amplifier reference voltages VREFA input to the amplifier reference voltages VREFA included in the corresponding error amplifiers 940 in the first voltage conversion circuit 501, the second voltage conversion circuit 502, the third voltage conversion circuit 503, and the fourth voltage conversion circuit 504 can be set to be the same or different from each other.

[0171] Comparator 950 can generate control pulses based on the comparison between the triangular wave output from adder 930 and the error amplification signal output from error amplifier 940.

[0172] The switch control circuit 960 can output a first switch control signal S1 for the first transistor and a switch control signal S2 for the second transistor based on the control pulse output from the comparator 950. For example, each of the first switch control signal S1 and the second switch control signal S2 can be supplied to the gate nodes of the first transistor and the second transistor, respectively.

[0173] For example, the switch control circuit 960 can output a first switch control signal S1 and a second switch control signal S2, wherein at least one of the gate voltage levels of the first transistor and the second transistor, the on-time control timing, and the off-time control timing is controlled based on a control pulse.

[0174] For example, the corresponding switch control circuits 960 included in the first voltage conversion circuit 501, the second voltage conversion circuit 502, the third voltage conversion circuit 503, and the fourth voltage conversion circuit 504 can respectively supply a first switch control signal S11 and a second switch control signal S21 to the first transistor T11 and the second transistor T21 of the first voltage conversion circuit 501, supply a first switch control signal S11 and a second switch control signal S21 to the first transistor T11 and the second transistor T21 of the second voltage conversion circuit 502, supply a first switch control signal S12 and a second switch control signal S22 to the first transistor T12 and the second transistor T22 of the third voltage conversion circuit 503, and supply a first switch control signal S13 and a second switch control signal S23 to the first transistor T13 and the second transistor T23 of the fourth voltage conversion circuit 504.

[0175] Reference Figure 10 The first voltage conversion circuit 501 may further include a mode control circuit 1000. For example, the mode control circuit 1000 may output a forced continuous current mode (FCCM) drive signal to the switch control circuit 960 based on the current detection result of the current sensing circuit 910 and the mode control signal output from the controller 140, for driving the first voltage conversion circuit 501 in forced continuous current mode (FCCM) during the voltage change cycle.

[0176] The switch control circuit 960 can output a first switch control signal S11 and a second switch control signal S21 corresponding to the first transistor T11 and the second transistor T21 based on the forced continuous current mode (FCCM) drive signal output from the mode control circuit 1000.

[0177] Figures 11 to 13 An example mode control circuit 1000, including in a power management circuit 150, is shown according to various aspects of this disclosure.

[0178] Figure 11 An example configuration of the mode control circuit 1000 is shown. Figure 12 An example of current change measured at the second node N21 of the first voltage conversion circuit 501 by driving in forced continuous current mode (FCCM) is shown. Figure 13 An example is shown of the variation of the first input voltage VI1 (which may be the source drive voltage SVDD) output from the first voltage conversion circuit 501 based on the mode control signal.

[0179] refer to Figure 11 In one or more example embodiments, the mode control circuit 1000 may include a mode reference voltage selector 1210 and a negative current controller 1220.

[0180] The mode reference voltage selector 1210 can supply the negative current controller 1220 with one of a first mode reference voltage VREFM1 applied during normal mode drive and a second mode reference voltage VREFM2 applied during forced continuous current mode (FCCM) drive.

[0181] For example, mode reference voltage selector 1210 can supply one of a first mode reference voltage VREFM1 and a second mode reference voltage VREFM2 to negative current controller 1220 based on a mode control signal supplied from controller 140.

[0182] For example, when a mode control signal with a low voltage level is received from the controller 140 to operate in normal mode, the mode reference voltage selector 1210 can output a first mode reference voltage VREFM1.

[0183] Furthermore, when a mode control signal with a high voltage level is received from the controller 140 to operate in forced continuous current mode (FCCM), the mode reference voltage selector 1210 can output a second mode reference voltage VREFM2.

[0184] The negative current controller 1220 can generate a forced continuous current mode (FCCM) drive signal based on the mode reference voltage output from the mode reference voltage selector 1210 and the output signal generated by detecting the current at the second node N21 of the first voltage conversion circuit 501 output from the current sensing circuit 910.

[0185] The switch control circuit 960 can supply the first switch signal S11 and the second switch signal S21, corresponding to the normal mode or the forced continuous current mode (FCCM), to the first transistor T11 and the second transistor T21 of the first voltage conversion circuit 501, respectively, based on the forced continuous current mode (FCCM) drive signal output from the negative current controller 1220.

[0186] refer to Figure 6 , Figure 11 and Figure 12 When a mode control signal with a low voltage level is applied from the controller 140, the negative current controller 1220 can receive the first mode reference voltage VREFM1 and output a forced continuous current mode (FCCM) drive signal corresponding to the normal mode, and the switch control circuit 960 can output a first switch signal S11 and a second switch signal S21 corresponding to the normal mode.

[0187] In this configuration, the first voltage conversion circuit 501 can operate in normal mode and can form a current path from the first node N11 to the fourth node N41 and a current path from the first node N11 to the ground line GND connected to the first transistor T11. Therefore, currents such as those detected at the second node N21 can be observed. Figure 12 The positive current mode of 'A1'.

[0188] When a mode control signal with a high voltage level is applied from the controller 140, the negative current controller 1220 can receive the second mode reference voltage VREFM2 and output a forced continuous current mode (FCCM) drive signal corresponding to the forced continuous current mode (FCCM), and the switch control circuit 960 can output a first switch signal S11 and a second switch signal S21 corresponding to the forced continuous current mode (FCCM).

[0189] In this configuration, the first voltage conversion circuit 501 can operate in forced continuous current mode (FCCM) and can form a current path from the fourth node N41 to the first node N11 and a current path from the ground line GND connected to the first transistor T11 to the first node N11. Therefore, currents such as those detected at the second node N21 can be observed. Figure 12 The negative current mode of 'A2'.

[0190] Reference Figure 13 The mode control signal supplied from the controller 140 to the first voltage conversion circuit 501 may include a first control pulse CP1 and a second control pulse CP2. For example, the first control pulse CP1 and the second control pulse CP2 may correspond to the period of applying a mode control signal with a high voltage level.

[0191] The pulse width of the first control pulse CP1 can correspond to the length of the first voltage change cycle. During the first voltage change cycle, the source drive voltage SVDD output from the first voltage conversion circuit 501 changes from the first voltage level VL1 to the second voltage level VL2.

[0192] Furthermore, the pulse width of the second control pulse CP2 can correspond to the length of the second voltage change cycle. During the second voltage change cycle, the source drive voltage SVDD output from the first voltage conversion circuit 501 changes from the second voltage level VL2 to the first voltage level VL1.

[0193] For example, the first control pulse CP1 may correspond to (or overlap with) the start time of the period of the anode reset frame AR, and the second control pulse CP2 may correspond to (or overlap with) the end time of the period of the anode reset frame AR.

[0194] For example, to reduce power consumption, the first voltage conversion circuit 501 can supply a source drive voltage SVDD with a first voltage level VL1 during the refresh frame RF period, and supply a source drive voltage SVDD with a second voltage level VL2 lower than the first voltage level VL1 during the anode reset frame AR period. In this case, since power loss may occur when driving the continuous current mode (FCCM) during all periods of the anode reset frame AR, the forced continuous current mode (FCCM) can be driven only during the voltage change cycle, thereby reducing power loss and reducing the time delay when performing voltage changes.

[0195] Figure 14 and Figure 15 An example configuration of a first drive voltage supply circuit 511 and 512 and a second drive voltage supply circuit 521 included in a power management circuit 150, according to various aspects of this disclosure, is shown.

[0196] Figure 14 An example configuration of the first drive voltage supply circuits 511 and 512 is shown, and Figure 15 An example configuration of the second drive voltage supply circuit 521 is shown.

[0197] refer to Figure 14 In one or more example embodiments, the first drive voltage supply circuits 511 and 512 may include a first reference voltage supply circuit 511 configured to generate a reference voltage with a high voltage level VREF_H and a second reference voltage supply circuit 512 configured to generate a reference voltage with a low voltage level VREF_L.

[0198] The first reference voltage supply circuit 511 and the second reference voltage supply circuit 512 may include a first driver amplifier 1400, which is configured to generate a reference voltage with a high voltage level VREF_H and a reference voltage with a low voltage level VREF_L based on a first input voltage output from the first voltage conversion circuit 501 and a preset first drive reference voltage VREFD1, respectively.

[0199] For example, the corresponding first drive reference voltages VREFD1 supplied to the first reference voltage supply circuit 511 and the second reference voltage supply circuit 512 can be set to be the same as or different from each other.

[0200] Each of the first reference voltage supply circuit 511 and the second reference voltage supply circuit 512 may further include a first drive control transistor TC1, which is connected between the first control node NC1 to which the first input voltage is applied and the first drive amplifier 1400, and is configured to control the supply of the first input voltage to the first drive amplifier 1400 according to a switching operation.

[0201] For example, the first drive control transistor TC1 can be turned on or off based on a first drive control signal DS1 with an on-state voltage level or a first drive control signal DS1 with an off-state voltage level supplied from the controller 140.

[0202] In the example where the first drive control transistor TC1 is an n-type transistor, the on-state voltage level of the first drive control signal DS1 can be a high voltage level, and the off-state voltage level of the first drive control signal DS1 can be a low voltage level.

[0203] Furthermore, in the example where the first drive control transistor TC1 is a p-type transistor, the on-state voltage level of the first drive control signal DS1 can be a low voltage level, and the off-state voltage level of the first drive control signal DS1 can be a high voltage level.

[0204] For example, the first drive control transistor TC1 can be supplied with a first drive control signal DS1 having an on-state voltage level during the refresh frame RF, and with a first drive control signal DS1 having an off-state voltage level during the anode reset frame AR.

[0205] For example, during the refresh frame RF, the first drive voltage supply circuits 511 and 512 can be supplied with a first drive control signal DS1 having a turn-on voltage level from the controller 140. This allows the first drive control transistor TC1 to turn on, and the first control node NC1 and the first drive amplifier 1400 to connect. Therefore, either the first drive voltage supply circuit 511 or 512 can be enabled.

[0206] Furthermore, during the anode reset frame AR, the first drive voltage supply circuits 511 and 512 can be supplied with a first drive control signal DS1 from the controller 140, having a cutoff voltage level. Consequently, the first drive control transistor TC1 can be turned off, and the connection between the first control node NC1 and the first drive amplifier 1400 can be disconnected. Therefore, either the first drive voltage supply circuit 511 or 512 can be deactivated.

[0207] refer to Figure 15 In one or more example embodiments, the second drive voltage supply circuit 521 may include a second drive amplifier 1500 configured to generate a dwell voltage VPK based on a second input voltage output from the second voltage conversion circuit 502 and a preset second drive reference voltage VREFD2.

[0208] Furthermore, the second drive voltage supply circuit 521 may further include a second drive control transistor TC2, which is connected between the second control node NC2 to which the second input voltage is applied and the second drive amplifier 1500, and is configured to control the supply of the second input voltage to the second drive amplifier 1500 according to a switching operation.

[0209] For example, the second drive control transistor TC2 can be turned on or off based on a second drive control signal DS2 with an on-state voltage level or a second drive control signal DS2 with an off-state voltage level supplied from the controller 140.

[0210] In the example where the second drive control transistor TC2 is an n-type transistor, the on-state voltage level of the second drive control signal DS2 can be a high voltage level, and the off-state voltage level of the second drive control signal DS2 can be a low voltage level.

[0211] Furthermore, in the example where the second drive control transistor TC2 is a p-type transistor, the on-state voltage level of the second drive control signal DS2 can be a low voltage level, and the off-state voltage level of the second drive control signal DS2 can be a high voltage level.

[0212] For example, the second drive control transistor TC2 can be supplied with a second drive control signal DS2 with an on-state voltage level during the anode reset frame AR, and with a second drive control signal DS2 with an off-state voltage level during the refresh frame RF.

[0213] For example, during the anode reset frame AR, the second drive voltage supply circuit 521 can be supplied with a second drive control signal DS2 having a turn-on voltage level from the controller 140. This turns on the second drive control transistor TC2, and connects the second control node NC2 and the second drive amplifier 1500. Therefore, the second drive voltage supply circuit 521 can be enabled.

[0214] Furthermore, the second drive voltage supply circuit 521 can be supplied with a second drive control signal DS2 with a cutoff voltage level from the controller 140 during the refresh frame RF. Consequently, the second drive control transistor TC2 can be turned off, and the connection between the second control node NC2 and the second drive amplifier 1500 can be disconnected. Therefore, the second drive voltage supply circuit 521 can be disabled.

[0215] Figure 16 and Figure 17 An example configuration of the gate drive circuit 130 according to various aspects of this disclosure is shown.

[0216] Figure 16An example configuration of gate drive circuitry 130, comprising multiple stages STG1 to STGn+1, is shown, and Figure 17 Example scan driver SCD and example transmit control driver EMD are shown in each of the multiple levels STG1 to STGn+1.

[0217] refer to Figure 16 In one or more example embodiments, the gate drive circuit 130 may include a plurality of GIP circuits corresponding to each of the plurality of stages STG1 to STGn+1. For example, the plurality of GIP circuits may be disposed in the non-display area NDA.

[0218] For example, the multiple GIP circuits corresponding to each level in the multiple STG levels may include GIP circuits disposed in the left non-display area NDA and GIP circuits disposed in the right non-display area NDA relative to the display area DA, but aspects of this disclosure are not limited thereto. For example, the multiple GIP circuits corresponding to each level in the multiple STG levels may be disposed only in a portion of the left or right non-display area NDA corresponding to the display area DA.

[0219] Each of the multiple GIP circuits may include at least one of a first scan driver SCD1, a second scan driver SCD2, a third scan driver SCD3, and a transmit control driver EMD.

[0220] Reference Figure 16 The GIP circuit located in the left non-display area NDA may include a first scan driver SCD1, a second scan driver SCD2, and a transmit control driver EMD, and the GIP circuit located in the right non-display area NDA may include a second scan driver SCD2, a third scan driver SCD3, and a transmit control driver EMD.

[0221] For example, the second scan driver SCD2 can be located in both the GIP circuit in the left non-display area NDA and the GIP circuit in the right non-display area NDA.

[0222] However, the arrangement of drivers in GIP circuits is not limited to this, and the drivers in each of multiple GIP circuits can be designed or changed differently according to design requirements.

[0223] refer to Figure 16The first scan driver SCD1 in the nth stage STGn can supply the first scan gate signal SCAN1 to the nth sub-pixel, the second scan driver SCD2 can supply the second scan gate signal SCAN2 to the nth sub-pixel, the third scan driver SCD3 can supply the third scan gate signal SCAN3 to the nth sub-pixel, and the transmit control driver EMD can supply the transmit control gate signal EM to the nth sub-pixel.

[0224] In one or more aspects, reference Figure 3 and Figure 16 The fourth transistor T4 in the nth sub-pixel SP can be supplied with the third scan gate signal SCAN3 from the third scan driver SCD3 in the nth stage STGn, and the sixth transistor T6 in the nth sub-pixel SP can be supplied with the third scan gate signal SCAN3 from the third scan driver SCD3 in the (n+1)th stage STGn+1).

[0225] refer to Figure 17 In one or more example embodiments, each of at least one scan driver SCD and transmit control driver EMD may include buffer circuitry 1610 and control circuitry 1620. For example, at least one scan driver SCD may include a first scan driver SCD1, a second scan driver SCD2, and a third scan driver SCD3.

[0226] The buffer circuit 1610 may include a pull-up transistor Tu connected between the first node ND1 and the second node ND2 and a pull-down transistor Td connected between the third node ND3 and the second node ND2.

[0227] The control circuit 1620 can control the voltage of the first control node (i.e., the Q node) which serves as the gate node of the pull-up transistor Tu and the second control node (i.e., the QB node) which serves as the gate node of the pull-down transistor Td.

[0228] Each buffer circuit 1610 included in the scan driver SCD and the transmit control driver EMD can output a gate drive signal to a gate line electrically connected to the second control node.

[0229] For example, the buffer circuit 1610 of the first scan driver SCD1 can output the first scan gate signal SCAN1, the buffer circuit 1610 of the second scan driver SCD2 can output the second scan gate signal SCAN2, the buffer circuit 1610 of the third scan driver SCD3 can output the third scan gate signal SCAN3, and the buffer circuit 1610 of the transmit control driver EMD can output the transmit control gate signal EM.

[0230] One of the first power supply voltage applied to the first node ND1 of the buffer circuit 1610 and the second power supply voltage applied to its third node ND3 can be a gate low voltage VGL, and the other can be a gate high voltage VGH that is higher than the gate low voltage VGL. For example, the gate low voltage VGL and the gate high voltage VGH can be supplied from the power management circuit 150.

[0231] For example, when the pull-up transistor Tu and the pull-down transistor Td are n-type transistors, the first power supply voltage can be the gate high voltage VGH, and the second power supply voltage can be the gate low voltage VGL.

[0232] Furthermore, when the pull-up transistor Tu and the pull-down transistor Td are p-type transistors, the first power supply voltage can be the gate low voltage VGL, and the second power supply voltage can be the gate high voltage VGH.

[0233] according to Figure 17 In this configuration, each of the scan driver SCD and the transmit control driver EMD can receive a start signal VST and a clock signal CLK from the controller 140, and is supplied with a gate high voltage VGH as a first power supply voltage and a gate low voltage VGL as a second power supply voltage. Thus, each of the scan driver SCD and the transmit control driver EMD can supply the corresponding gate signal from the scan gate signals SCAN1, SCAN2, and SCAN3 and the transmit control gate signal EM.

[0234] For example, the start signal VST and clock signal CLK supplied to each of the scan driver SCD and the transmit control driver EMD can be the same or different from each other.

[0235] Examples, aspects, and embodiments of the display device 100 and display panel 110 described herein can be described as follows.

[0236] According to one or more exemplary embodiments described herein, a display device may be provided, comprising: a display panel including a plurality of gate lines, a plurality of data lines, and a plurality of sub-pixels; a data driving circuit configured to supply a data voltage to the plurality of data lines; a gate driving circuit configured to drive the plurality of gate lines; a controller configured to supply image data corresponding to the data voltage to the data driving circuit and control the data driving circuit and the gate driving circuit; and a power management circuit including a plurality of voltage conversion circuits and a plurality of drive voltage supply circuits, each of the plurality of drive voltage supply circuits being configured to supply a drive voltage to at least one of the plurality of sub-pixels, the data driving circuit, the gate driving circuit, and the controller based on an input voltage supplied from a corresponding one of the plurality of voltage conversion circuits. In one or more aspects, the power management circuit may be configured to cause a first drive voltage supply circuit to supply a first drive voltage to the data driving circuit among the plurality of drive voltage supply circuits, to be deactivated during at least one first sub-frame in at least one frame corresponding to the image data.

[0237] In one or more aspects, the power management circuitry may be configured to cause the second drive voltage supply circuitry, which is configured to supply the second drive voltage to the data drive circuitry, to be deactivated during at least one second subframe in at least one frame.

[0238] In one or more aspects, at least one first subframe may be an anode reset frame, and at least one second subframe may be a refresh frame.

[0239] In one or more aspects, the first driving voltage may be a reference voltage for generating a gamma voltage in the data driving circuit, and the second driving voltage may be a dwell voltage supplied by the data driving circuit to multiple data lines during at least one first subframe.

[0240] In one or more aspects, the first drive voltage supply circuit may include: a first reference voltage supply circuit configured to generate a reference voltage having a first voltage level and supply the reference voltage having the first voltage level to the data drive circuit; and a second reference voltage supply circuit configured to generate a reference voltage having a second voltage level and supply the reference voltage having the second voltage level to the data drive circuit. The second voltage level may be lower than the first voltage level.

[0241] In one or more aspects, the plurality of voltage conversion circuits may include a first voltage conversion circuit and a second voltage conversion circuit, the first voltage conversion circuit being configured to convert an initial voltage supplied from a system power supply to a first input voltage and supply the first input voltage to a first drive voltage supply circuit, and the second voltage conversion circuit being configured to convert the initial voltage to a second input voltage and supply the second input voltage to a second drive voltage supply circuit.

[0242] In one or more aspects, the first voltage conversion circuit may be configured to supply a first input voltage having a first voltage level to a first input voltage during at least one second subframe, and to change the first voltage level of the first input voltage to a second voltage level less than the first voltage level during at least one first subframe, and to supply a first input voltage having a second voltage level.

[0243] In one or more aspects, the first voltage conversion circuit may be configured to receive a mode control signal from a controller and operate in a forced continuous current mode based on the mode control signal in at least one of a first voltage change cycle and a second voltage change cycle, wherein during the first voltage change cycle, the first input voltage changes from a first voltage level to a second voltage level, and during the second voltage change cycle, the first input voltage changes from the second voltage level to the first voltage level.

[0244] In one or more aspects, the mode control signal may include a first control pulse and a second control pulse. In one or more aspects, the pulse width of the first control pulse may correspond to the length of a first voltage changing period, and the pulse width of the second control pulse may correspond to the length of a second voltage changing period.

[0245] In one or more aspects, the plurality of voltage conversion circuits may further include a third voltage conversion circuit configured to convert an initial voltage into a third input voltage.

[0246] In one or more aspects, the plurality of drive voltage supply circuits may further include: a third drive voltage supply circuit configured to receive at least one of a second input voltage and a third input voltage; generate at least one third drive voltage; and supply the at least one third drive voltage to a source node or drain node of at least one transistor included in each of the plurality of sub-pixels; and a fourth drive voltage supply circuit configured to receive at least one of the second input voltage and the third input voltage, generate at least one fourth drive voltage, and supply the at least one fourth drive voltage to a gate drive circuit.

[0247] In one or more aspects, at least one third drive voltage may include at least one of a bias voltage, an initialization voltage, and an anode reset voltage, and at least one fourth drive voltage may include at least one of a gate high voltage and a gate low voltage.

[0248] In one or more aspects, the gate drive circuit can be configured to generate a gate signal to be supplied to the gate node of at least one transistor through at least one of a plurality of gate lines based on at least one fourth drive voltage.

[0249] In one or more aspects, the first voltage conversion circuit may be configured to supply a first input voltage having a first voltage level during the second subframe.

[0250] In one or more aspects, the second voltage conversion circuit may be configured to supply a second input voltage having a third voltage level greater than the first voltage level during at least one first subframe and at least one second subframe.

[0251] In one or more aspects, the third voltage conversion circuit can be configured to supply a third input voltage having a fourth voltage level that is lower than the first voltage level.

[0252] In one or more aspects, the plurality of voltage conversion circuits may include at least one of a buck converter, a boost converter, and a buck-boost converter.

[0253] According to one or more example embodiments of this disclosure, a power management circuit may be provided, comprising: a first voltage conversion circuit configured to convert an initial voltage supplied from a system power supply into a first input voltage; a second voltage conversion circuit configured to convert the initial voltage into a second input voltage; a first drive voltage supply circuit configured to generate a first drive voltage based on the first input voltage, supply the first drive voltage to a data drive circuit, and be deactivated during at least one first subframe of at least one frame corresponding to image data supplied from a controller to the data drive circuit; and a second drive voltage supply circuit configured to generate a second drive voltage based on the second input voltage, supply the second drive voltage to the data drive circuit, and be deactivated during at least one second subframe of at least one frame.

[0254] In one or more aspects, the first drive voltage supply circuit may include: a first drive amplifier configured to generate a first drive voltage based on a first input voltage; and a first drive control transistor disposed between a first drive voltage line supplied with the first drive voltage and the first drive amplifier, and configured to cause the first drive amplifier to be deactivated during at least one first subframe by a switching operation based on a first drive control signal supplied from a controller.

[0255] In one or more aspects, the second drive voltage supply circuit may include a second drive amplifier and a second drive control transistor, the second drive amplifier being configured to generate a second drive voltage based on a second input voltage, the second drive control transistor being disposed between a second drive voltage line supplied with the second drive voltage and the second drive amplifier, and being configured to cause the second drive amplifier to be deactivated during at least one second subframe by a switching operation based on a second drive control signal supplied from a controller.

[0256] In one or more aspects, the first voltage conversion circuit may be configured to supply a first input voltage having a first voltage level during at least one second subframe, and to supply a first input voltage having a second voltage level less than the first voltage level during at least one first subframe.

[0257] In one or more aspects, the first voltage conversion circuit may be configured to receive a mode control signal from a controller and operate in a forced continuous current mode based on the mode control signal during at least one of a first voltage change cycle and a second voltage change cycle, wherein the first input voltage changes from a first voltage level to a second voltage level during the first voltage change cycle and the first input voltage changes from a second voltage level to a first voltage level during the second voltage change cycle.

[0258] In one or more aspects, the first voltage conversion circuit may include: a first transistor and a second transistor; a current sensing circuit configured to detect the current at the node to which the first transistor and the second transistor are connected; a mode control circuit configured to output a forced continuous current mode drive signal for operation in a forced continuous current mode based on the current detection result of the current sensing circuit and the mode control signal; and a switch control circuit configured to control the switching operation of the first transistor and the second transistor based on the forced continuous current mode drive signal.

[0259] The above description has been presented to enable any person skilled in the art to make and use the technical ideas of this disclosure, and has been provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the principles described herein can be applied to other embodiments and applications without departing from the scope of this disclosure. The above description and drawings are provided as examples of the technical ideas of this disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical ideas of this disclosure.

[0260] The various embodiments described above can be combined to provide further embodiments. If desired, aspects of the embodiments can be modified to employ the concepts of various embodiments to provide further embodiments.

[0261] Based on the detailed description above, these and other changes can be made to the embodiments. Generally, the terminology used in the appended claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be understood to include all possible embodiments and the full scope of equivalents enjoyed by these claims. Therefore, the claims are not limited to this disclosure.

Claims

1. A display device, comprising: The display panel includes multiple gate lines, multiple data lines, and multiple sub-pixels; A data driving circuit configured to supply data voltage to the plurality of data lines; A gate driving circuit configured to drive the plurality of gate lines; A controller configured to supply image data corresponding to the data voltage to the data driving circuit and to control the data driving circuit and the gate driving circuit; as well as A power management circuit includes multiple voltage conversion circuits and multiple drive voltage supply circuits. Each drive voltage supply circuit is configured to supply a drive voltage to at least one of the multiple sub-pixels, the data drive circuit, the gate drive circuit, and the controller based on an input voltage supplied from a corresponding voltage conversion circuit among the multiple voltage conversion circuits. The power management circuit is configured to cause the first drive voltage supply circuit, which is configured to supply a first drive voltage to the data drive circuit, to be deactivated during at least one first subframe in at least one frame corresponding to the image data.

2. The display device according to claim 1, wherein, The power management circuit is configured to cause one of the plurality of drive voltage supply circuits, which is configured to supply a second drive voltage to the data drive circuit, to be deactivated during at least one second subframe in the at least one frame.

3. The display device according to claim 2, wherein, The at least one first subframe is an anode reset frame, and the at least one second subframe is a refresh frame.

4. The display device according to claim 2, wherein, The first driving voltage is a reference voltage used to generate a gamma voltage in the data driving circuit, and the second driving voltage is a dwell voltage supplied by the data driving circuit to the plurality of data lines during the at least one first subframe.

5. The display device according to claim 4, wherein, The first driving voltage supply circuit includes: A first reference voltage supply circuit, configured to generate a reference voltage having a first voltage level and supply the reference voltage at the first voltage level to the data driving circuit; and A second reference voltage supply circuit is configured to generate a reference voltage having a second voltage level and supply the reference voltage at the second voltage level to the data driving circuit. Wherein, the second voltage level is lower than the first voltage level.

6. The display device according to claim 2, wherein, The plurality of voltage conversion circuits include: A first voltage conversion circuit, configured to convert an initial voltage supplied from the system power supply into a first input voltage, and supply the first input voltage to the first drive voltage supply circuit; and A second voltage conversion circuit is configured to convert the initial voltage into a second input voltage and supply the second input voltage to the second drive voltage supply circuit.

7. The display device according to claim 6, wherein, The first voltage conversion circuit is configured to supply the first input voltage having a first voltage level during the at least one second subframe, and to change the first voltage level of the first input voltage to a second voltage level lower than the first voltage level during the at least one first subframe, and to supply the first input voltage having the second voltage level.

8. The display device according to claim 7, wherein, The first voltage conversion circuit is configured to receive a mode control signal from the controller and operate in a forced continuous current mode based on the mode control signal in at least one of a first voltage change cycle and a second voltage change cycle, wherein the first input voltage changes from the first voltage level to the second voltage level during the first voltage change cycle and changes from the second voltage level to the first voltage level during the second voltage change cycle.

9. The display device according to claim 8, wherein, The mode control signal includes a first control pulse and a second control pulse, and Wherein, the pulse width of the first control pulse corresponds to the length of the first voltage change period, and the pulse width of the second control pulse corresponds to the length of the second voltage change period.

10. The display device according to claim 6, wherein, The plurality of voltage conversion circuits further include a third voltage conversion circuit configured to convert the initial voltage into a third input voltage, and The plurality of drive voltage supply circuits further include: A third driving voltage supply circuit is configured to receive at least one of the second input voltage and the third input voltage, generate at least one third driving voltage, and supply the at least one third driving voltage to the source or drain node of at least one transistor included in each of the plurality of sub-pixels; and A fourth drive voltage supply circuit is configured to receive at least one of the second input voltage and the third input voltage, generate at least one fourth drive voltage, and supply the at least one fourth drive voltage to the gate drive circuit.

11. The display device according to claim 10, wherein, The at least one third drive voltage includes at least one of a bias voltage, an initialization voltage, and an anode reset voltage, and the at least one fourth drive voltage includes at least one of a gate high voltage and a gate low voltage.

12. The display device according to claim 10, wherein, The gate drive circuit is configured to generate a gate signal to be supplied to the gate node of the at least one transistor through at least one of the plurality of gate lines based on the at least one fourth drive voltage.

13. The display device according to claim 10, wherein: The first voltage conversion circuit is configured to supply the first input voltage having a first voltage level during the second subframe; The second voltage conversion circuit is configured to supply a second input voltage having a third voltage level greater than the first voltage level during the at least one first subframe and the at least one second subframe; and The third voltage conversion circuit is configured to supply the third input voltage having a fourth voltage level that is lower than the first voltage level.

14. The display device according to claim 1, wherein, The plurality of voltage conversion circuits include at least one of a buck converter, a boost converter, and a buck-boost converter.

15. A power management circuit, comprising: A first voltage conversion circuit is configured to convert an initial voltage supplied from the system power supply into a first input voltage; A second voltage conversion circuit is configured to convert the initial voltage into a second input voltage; A first driving voltage supply circuit is configured to generate a first driving voltage based on the first input voltage and supply the first driving voltage to a data driving circuit. The first driving voltage supply circuit is configured to be deactivated during at least one first subframe of at least one frame corresponding to image data supplied from the controller to the data driving circuit. as well as A second driving voltage supply circuit is configured to generate a second driving voltage based on the second input voltage and supply the second driving voltage to the data driving circuit, and the second driving voltage supply circuit is configured to be deactivated during at least one second subframe in the at least one frame.

16. The power management circuit according to claim 15, wherein, The first driving voltage supply circuit includes: A first driver amplifier, configured to generate a first drive voltage based on the first input voltage; and A first drive control transistor is disposed between a first drive voltage line supplied with the first drive voltage and the first drive amplifier, and is configured to cause the first drive amplifier to be deactivated during the at least one first subframe by a switching operation based on a first drive control signal supplied from the controller.

17. The power management circuit according to claim 16, wherein, The second drive voltage supply circuit includes: A second driver amplifier, configured to generate a second drive voltage based on the second input voltage; and A second drive control transistor is disposed between a second drive voltage line supplied with the second drive voltage and the second drive amplifier, and is configured to cause the second drive amplifier to be deactivated during the at least one second subframe by a switching operation based on a second drive control signal supplied from the controller.

18. The power management circuit according to claim 15, wherein, The first voltage conversion circuit is configured to supply a first input voltage having a first voltage level during at least one second subframe, supply a first input voltage having a second voltage level less than the first voltage level during at least one first subframe, and receive a mode control signal from a controller, operating in a forced continuous current mode based on the mode control signal in at least one of a first voltage change cycle and a second voltage change cycle, wherein the first input voltage changes from the first voltage level to the second voltage level during the first voltage change cycle, and the first input voltage changes from the second voltage level to the first voltage level during the second voltage change cycle.

19. The power management circuit according to claim 18, wherein, The first voltage conversion circuit includes: First transistor and second transistor; A current sensing circuit configured to detect the current at the node where the first transistor and the second transistor are connected; A mode control circuit, configured to output a forced continuous current mode drive signal for operation in the forced continuous current mode based on the current detection result of the current sensing circuit and the mode control signal; and A switching control circuit configured to control the switching operations of the first transistor and the second transistor based on the forced continuous current mode drive signal.

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