LDO circuit based on inverting voltage follower and double feed-forward zero stability compensation

Abstract

This invention discloses an LDO circuit based on a flip-flop voltage follower and dual feedforward zero-point stability compensation, comprising a flip-flop voltage follower, a dual feedforward zero-point compensation network, an embedded feedforward ripple cancellation network, a bias network, and a level shifting network. The flip-flop voltage follower dynamically adjusts the output voltage of the power output PMOS transistor. The dual feedforward zero-point compensation network performs zero-point compensation on the two non-dominant poles of the circuit. The bias network provides appropriate bias to ensure that the MOS transistor in the error amplifier operates at the correct operating point, thereby providing sufficient DC gain. The embedded feedforward ripple cancellation network achieves a feedforward path by multiplexing the signal transmission path of the error amplifier, effectively reducing additional noise sources. Simultaneously, the feedforward gain of the embedded feedforward ripple cancellation network can be adjusted by the bias network to meet the ripple cancellation requirements, ultimately achieving a high power supply rejection ratio over a wide frequency range.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design, and more specifically to an LDO circuit based on a flip-flop voltage follower and dual feedforward zero-point stability compensation. Background Technology

[0002] Ring oscillators (ROs) are widely used in sub-rate clocking strategies in multi-channel SerDes systems due to their small size, resistance to electromagnetic interference, and ability to generate multiple phases. However, RO frequencies are inherently much more sensitive to power supply voltage variations than LC oscillators, thus requiring additional investment in power supply regulation. In some phase-locked loop (PLL) designs, the transfer function amplitude from RO power supply noise to output phase noise reaches its maximum when the frequency offset equals the loop bandwidth of the PLL. Since the loop bandwidth of a low-jitter RO-PLL typically varies between 20 and 120 MHz, improving the power supply noise suppression of the RO within this frequency range is crucial.

[0003] Power supply noise cancellation schemes can adaptively adjust the RO current to stabilize the RO frequency in response to power supply voltage variations. Background calibration can be achieved through digital or analog loops to match the compensation current to power supply noise sensitivity. While these solutions offer compact chip sizes, their improvement in power supply noise suppression is limited at power supply noise frequencies of 40-50MHz. 21dB.

[0004] Another solution relies on voltage regulators to stabilize the RO supply voltage. For example, some designs use replication-biased regulators that eliminate the bulge in the power supply rejection curve by placing the poles below the bandwidth of the error amplifier, thus achieving excellent power supply rejection over a wider frequency range. However, to maintain sufficiently low poles, the capacitors in this type of design need to increase proportionally with the RO current. In low-jitter RO-PLLs, the RO current typically exceeds 10mA, requiring unacceptably large capacitors. Other designs utilize NMOS transfer transistors to provide excellent power supply rejection over a wider frequency range, avoiding the use of large capacitors. However, these designs generate a large 0.7V voltage drop across the NMOS transfer transistor, reducing power efficiency and limiting the maximum supply voltage, thereby limiting the RO frequency. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide an LDO circuit based on a flip-flop voltage follower and dual feedforward zero-point stability compensation.

[0006] The first aspect of the present invention provides an LDO circuit based on a flip-flop voltage follower and dual feedforward zero-point stability compensation, including a flip-flop voltage follower, a dual feedforward zero-point compensation network, an embedded feedforward ripple elimination network, a bias network, and a level shifting circuit.

[0007] The aforementioned flip-flop voltage follower includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a third NMOS transistor, and a power output PMOS transistor; wherein the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the third NMOS transistor constitute an error amplifier for dynamically adjusting the output voltage of the power output PMOS transistor; the drain node of the power output PMOS transistor serves as the output voltage node of the LDO circuit; The dual feedforward zero-point compensation network includes a first feedforward compensation capacitor and a second feedforward compensation capacitor; wherein the first feedforward compensation capacitor is connected in parallel with the source and drain of the first PMOS transistor to generate a first left half-plane zero for frequency compensation; the second feedforward compensation capacitor is connected in parallel with the source and drain of the first NMOS transistor to generate a second left half-plane zero for frequency compensation. The embedded feedforward ripple cancellation network includes a multiplexed second PMOS transistor, a third PMOS transistor, and a second NMOS transistor; the embedded feedforward ripple cancellation network is used to eliminate noise from the power supply voltage; The bias network includes a second PMOS transistor, a third PMOS transistor, a second NMOS transistor, a fifth NMOS transistor, and a bandwidth extension capacitor; the bias network is used to provide the error amplifier with the correct DC operating point to ensure sufficient DC gain, while controlling the gain of the power supply ripple feedforward path. The level shifting circuit includes a fourth PMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor; the level shifting circuit is used to make the output DC voltage of the LDO circuit equal to the reference voltage.

[0008] Furthermore, in the flip voltage follower and level shifter circuit, the third NMOS transistor, the fourth NMOS transistor, and the fifth NMOS transistor constitute a current mirror; at the same time, the ratio of the source-drain current flowing through the first PMOS transistor and the fourth PMOS transistor is equal to the ratio of the width to the length of the first PMOS transistor and the fourth PMOS transistor, so the gate-source voltages of the first PMOS transistor and the fourth PMOS transistor are equal. Since the first PMOS transistor and the fourth PMOS transistor share the same gate voltage, the source voltages of the first PMOS transistor and the fourth PMOS transistor are equal, that is, the output DC voltage and the reference voltage of the LDO circuit are equal. The first PMOS transistor, together with the first NMOS transistor and the third NMOS transistor, forms a folded cascode structure. The connection node between the drain of the first PMOS transistor and the drain of the third NMOS transistor serves as the folding node of the folded cascode structure. The source of the first PMOS transistor is connected to the drain of the power output PMOS transistor to receive the output feedback voltage from the power output PMOS transistor. The gate of the first PMOS transistor is connected to the drain of the fourth PMOS transistor, so that the gate voltage bias of the first PMOS transistor is set by level shifting from the reference voltage. The source of the third NMOS transistor is grounded, and its gate is connected to the drain of the fifth NMOS transistor. The source of the first NMOS transistor is connected to the folded node of the folded common-source common-gate transistor, and the drain is connected to the gate node of the power output PMOS transistor. The gate is connected to a fixed bias voltage.

[0009] Furthermore, in the flip voltage follower and level shifting circuit, the fourth PMOS transistor, the fourth NMOS transistor, and the fifth NMOS transistor are used to shift and transfer the level of the reference voltage to the first PMOS transistor; the folded common-source common-gate error amplifier composed of the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the third NMOS transistor is used to amplify the difference between the output feedback voltage and the input reference voltage, and is used to regulate the gate voltage of the power output PMOS transistor so that the output feedback voltage of the power output PMOS transistor tends to be stable.

[0010] Furthermore, in the dual feedforward zero-point compensation network, the two ends of the first feedforward compensation capacitor are respectively connected to the source and drain of the first PMOS transistor, and the non-major pole at the source of the first PMOS transistor is zero-point compensated through the first feedforward compensation capacitor; the two ends of the second feedforward compensation capacitor are respectively connected to the source and drain of the first NMOS transistor, and the non-major pole at the source of the first NMOS transistor is zero-point compensated through the second feedforward compensation capacitor.

[0011] Furthermore, in the bias network, the third PMOS transistor and the second NMOS transistor generate the bias voltage of the second PMOS transistor, which constitutes the load current source in the error amplifier; the second NMOS transistor and the fifth NMOS transistor form a current mirror and share the same gate voltage; the drain of the second NMOS transistor is connected to the drain of the third PMOS transistor; the drain of the third PMOS transistor is shorted to the gate. The second PMOS transistor serves as the active load of the output voltage node of the error amplifier, with its gate connected to the gate of the third PMOS transistor and its drain connected to the gate of the power PMOS transistor. The bias network is used to provide a bias voltage to the active load formed by the second PMOS.

[0012] Furthermore, in the embedded feedforward ripple elimination network, the second PMOS transistor, the third PMOS transistor, and the second NMOS transistor form the feedforward path for the power supply ripple. The source of the second PMOS transistor is connected to the power supply voltage input. The second PMOS transistor serves as the load current source of the error amplifier and is also the transconductance amplification stage of the power supply ripple feedforward path, transmitting the ripple change of the power supply voltage to the output terminal of the error amplifier, i.e., the gate of the power output PMOS transistor. The third PMOS transistor and the second NMOS transistor form a voltage bias circuit to provide the gate voltage of the second PMOS transistor, and at the same time, it is used to control the magnitude of the power supply ripple transmitted to the gate of the second PMOS transistor, thereby controlling the gain of the power supply ripple feedforward path.

[0013] Furthermore, in the embedded feedforward ripple cancellation network, the power supply voltage ripple change transmitted by the second PMOS transistor is out of phase and matches the ripple change received by the source of the power output PMOS transistor from the power supply voltage input, thus achieving ripple cancellation at the drain of the power output PMOS transistor.

[0014] Furthermore, in the embedded feedforward ripple elimination network, the two ends of the bandwidth extension capacitor are respectively connected to the gate of the third PMOS transistor and ground, providing a left half-plane zero in the power ripple feedforward path to extend the bandwidth of the power ripple feedforward.

[0015] Furthermore, in the bias network, the fifth NMOS transistor, the second NMOS transistor, and the fourth NMOS transistor constitute a current mirror; the drain of the fifth NMOS transistor is connected to the reference current input, and its gate is shorted to the drain and connected to the gates of the second and fourth NMOS transistors, providing a bias voltage for the second and fourth NMOS transistors.

[0016] Furthermore, low-pass filters are provided at the connections between the drain of the fifth NMOS transistor and the gate of the second NMOS transistor, the drain of the fifth NMOS transistor and the gate of the fourth NMOS transistor, and the drain of the fourth PMOS transistor and the gate of the first PMOS transistor; filtering is performed through the low-pass filters.

[0017] The embodiments of the present invention have the following beneficial effects: The LDO circuit based on a flip-flop voltage follower and dual feedforward zero-point stability compensation proposed in this invention employs dual feedforward zero-point compensation technology. Compared with single feedforward zero-point compensation, dual feedforward zero-point compensation eliminates the need for large capacitors to generate low-frequency zeros, reducing high-frequency noise fed from the LDO internal feedthrough to the output, reducing the sources of LDO output noise, maintaining the large bandwidth of the LDO, and ensuring sufficient phase margin and stability of the loop over a wide current range from light load to heavy load. The main sources of output noise in the LDO based on the flip-flop voltage follower are only the first PMOS transistor and the third NMOS transistor. Simultaneously, the embedded feedforward ripple cancellation technology of this invention significantly improves the power supply rejection capability in the mid-to-high frequency range without introducing additional noise sources, and its low voltage drop characteristics make multi-stage cascading possible, thereby further optimizing overall performance. This invention achieves stable operation with low output noise, high power rejection ratio and wide load range simultaneously through a low dropout regulator architecture. It effectively solves the inherent problems of limited PSNR improvement, the need for large external capacitors or sacrifice of power efficiency in traditional power noise suppression technologies. It significantly improves the output phase noise performance of the ring oscillator at the critical frequency offset, and achieves tens of dB improvement in power noise suppression in the power noise frequency range of 20MHz to 100MHz.

[0018] Additional aspects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description or may be learned by practice of the invention. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the basic structure of an LDO circuit based on a flip-flop voltage follower and dual feedforward zero-point stability compensation according to the present invention. Figure 2 This is a schematic diagram of the small-signal model structure of the circuit equivalent of the flip voltage follower of the present invention; Figure 3 This is a schematic diagram comparing the dual feedforward zero-point compensation effect of the circuit of this invention with that of existing solutions; Figure 4 This is a schematic diagram comparing the output noise of the circuit of the present invention with that of existing solutions; Figure 5 This is a schematic diagram comparing the phase margin of the circuit of the present invention with that of existing solutions; Figure 6This is an equivalent schematic diagram of the power supply suppression calculation of the embedded feedforward ripple elimination network in the circuit of this invention; Figure 7 This is a schematic diagram illustrating the bandwidth extension concept of the embedded feedforward ripple cancellation network in the circuit of this invention; Figure 8 This is a schematic diagram comparing the power supply rejection ratio of the circuit of the present invention; Figure 9 This is a schematic diagram of the cascaded effect of the circuit of the present invention; Figure 10 This is a schematic diagram comparing the output noise of the circuit of the present invention; Figure 11 This is a schematic diagram of the noise of a RO power supply without an LDO; Figure 12 This is a schematic diagram of the RO power supply noise using the circuit of the present invention.

[0021] Figure label: M P -Power output PMOS transistor, M P1 - First PMOS transistor, M P2 -Second PMOS transistor, M P3 -Third PMOS transistor, M P4 - Fourth PMOS transistor, M N1 - First NMOS transistor, M N2 -Second NMOS transistor, M N3 -Third NMOS transistor, M N4 - Fourth NMOS transistor, M N5 - Fifth NMOS transistor, C Z1 -First feedforward compensation capacitor, C Z2 -Second feedforward compensation capacitor, C Z3 -Bandwidth extension capacitor, LPF -Low-pass filter. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0023] The power supply noise sensitivity of inverter-based ring oscillators (ROs) can reach the GHz / V level, thus imposing stringent noise requirements on linear regulators (LDOs).

[0024] Inverter-based reverse oscillators (ROs) are extremely sensitive to power supply noise, which can reach several gigahertz per volt. This places extremely stringent output noise requirements on the low-dropout low-voltage direct current generators (LDOs) powering them. For example, for an RO operating at 6 GHz with a power supply noise sensitivity of approximately 7 GHz / V, if its intrinsic phase noise at a 10 MHz frequency offset is... 117dBc / Hz. In order to control the phase noise degradation introduced by power supply noise to within 1dB, calculations show that the output noise spectral density of the LDO needs to be lower than about 1.4nV / √Hz.

[0025] However, existing low-noise LDOs typically rely on extremely narrow loop bandwidth to effectively suppress noise generated by their internal reference source and error amplifier. While this approach reduces the LDO's own output noise, in the absence of large-capacity off-chip capacitors, it directly leads to a severe deterioration in the LDO's power supply rejection ratio (PSRR) performance in the 20MHz to 120MHz frequency band.

[0026] Therefore, such as Figure 1 As shown, this embodiment of the invention provides an LDO circuit based on a flip-flop voltage follower and dual feedforward zero-point stability compensation, including a flip-flop voltage follower, a dual feedforward zero-point compensation network, an embedded feedforward ripple elimination network, and a bias network; wherein the flip-flop voltage follower includes M P1 M P2 M N1 M N3 and M P M P1 M P2 M N1 and M N3 The error amplifier (EA) is used to adjust the power output M. P The output voltage is dynamically adjusted; M P The drain node serves as the output voltage node of the LDO circuit. The dual feedforward zero-point compensation network includes C Z1 and C Z2 ; where C Z1 and M P1 The source and drain are connected in parallel to generate the first left half-plane zero for frequency compensation, C Z2 and M N1 The source and drain are connected in parallel to generate a second left-half-plane zero for frequency compensation; the embedded feedforward ripple cancellation network includes multiplexed M... P2 M P3 M N2 The embedded feedforward ripple cancellation network achieves power supply noise suppression over a wider frequency range by eliminating noise from the power supply voltage; the bias network includes M...P2 M P3 M N2 M N5 and bandwidth expansion capacitor C Z3 The bias network provides the correct DC operating point to the error amplifier to ensure sufficient DC gain, while also controlling the gain of the power supply ripple feedforward path; the level shifting circuit includes M... P4 M N4 and M N5 The level shifter circuit is used to make the output DC voltage of the LDO circuit equal to the reference voltage.

[0027] The LDO circuit proposed in this embodiment of the invention is based on a folded cascode flip-flop voltage follower (FVF) to ensure high loop gain and sufficient power supply rejection (PSR) at low frequencies. Simultaneously, by using transistors (M...) in the cascode branch... N1 M P2 The current (I) casc ) is set to be higher than the transconductance current (I gm The noise level is 19 times lower, minimizing their noise. Since the output noise of an LDO primarily originates from the M... P1 and M N3 Increase transconductance g m,P1 It can effectively suppress output noise and improve loop bandwidth.

[0028] The functional principles of each part of this invention are explained in detail below: In this embodiment of the invention, the flip voltage follower includes M P1 M P2 M N1 M N3 and M P ; where M P1 M P2 M N1 and M N3 Construct an error amplifier for power output M P The output voltage is dynamically adjusted. The level shifting circuit includes M... P4 M N4 and M N5 This is used to make the output DC voltage of the LDO circuit equal to the reference voltage. Specifically, M N3 M N4 With M N5 Forming a current mirror; simultaneously flowing through M P1 and M P4 The source-to-drain current ratio and M p1 and M P4 The width-to-length ratios are equal, therefore MP1 and M P4 The gate-source voltages are equal, and because M P1 and M P4 They share the same gate voltage, therefore M P1 and M P4 The source voltages are equal, meaning the output DC voltage of the LDO circuit is equal to the reference voltage; M P1 With M N1 and M N3 Forming a folded cascode structure, M P1 Drain and M N3 The drain connection node serves as the folded node for the folded common-source, folded-gate folding mechanism; M P1 The source of M is connected to the drain of the power output PMOS transistor, receiving the output feedback voltage from the power output PMOS transistor. P1 The gate of M is connected to the drain of the fourth PMOS transistor. P1 The gate voltage bias is set by level shifting the reference voltage; M N3 The source is grounded, and the gate is connected to M. N5 Drain; M N1 The source is connected to the folded node of the folded common-source and cascode transistor, and the drain is connected to the power output transistor M. P The gate node is connected to a fixed bias voltage.

[0029] In this embodiment of the invention, M P4 and M N4 The reference branch is formed by series connection, M P4 The source is connected to the reference voltage V. REF , gate drain shorted; M N4 The source is grounded, and the gate is connected to M. N5 The drain of the reference branch; this reference branch is used to generate a level shift so that the reference voltage V REF and output voltage V SUP Equal. M P1 M N1 and M N3 To form a folded cascode stage, M P1 Source receives output feedback voltage V SUP The gate receives a bias voltage generated from a reference voltage through level shifting; M N3 The source is grounded, and the gate is connected to M. N5 The drain of M, its drain is connected to M P1 The drain is connected to the folded node V of the folded common source and common gate. M ; As can be seen, the error amplifier based on folded cascode in this embodiment of the invention introduces very little noise while generating high loop gain; its main noise source is only M. P1 and M N3 The feedback detection stage will output voltage VSUP The error signal is compared with the level-shifted reference voltage, amplified by a common-source cascode stage, and then drives the power transistor M. P The gate (node ​​V) G M is adjusted through negative feedback. P The conduction state ultimately causes the output feedback voltage V to... SUP and reference voltage V REF equal.

[0030] The equivalent small-signal model structure of the flip-flop voltage follower circuit of this invention is as follows: Figure 2 As shown. This LDO has three poles: V G A principal pole (ω) G ), and V M and V SUP The two non-principal poles at (ω) M and ω SUP Due to the large transconductance g m，P1 This will increase ωG and unity-gain frequency (UGF), ω M It will fall within the UGF range and be closer to ω. G (like Figure 3 As shown in the figure, stability compensation is required.

[0031] Traditional methods such as Miller compensation compress ω G This limits the intermediate frequency PSR; while damping factor control compensation can maintain a wide loop bandwidth, but at the cost of increased output noise due to additional active circuitry. Another design is to use M in the FVF. P1 A capacitor C is placed at both ends. Z1 It can generate a feedforward zero ω for stability compensation. Z1 .

[0032] The formula for calculating ωZ1 is as follows: ; Although ω Z1 The generation of ω does not significantly compress ω G However, due to ω Z1 Will follow g m，P1 Increased by (see) Figure 2 Therefore, it requires a large C-size. Z1 Only then can ω Z1 Set at a sufficiently low frequency to compensate for ω M For example, in g m，P1 The current is 20ms and the RO current is I. LOAD At 11mA, a 30pF C is required. Z1 Only then can a phase margin of 65° be achieved (see...) Figure 3 Such a large C Z1This will feed noise from the common source cascode branch to the output, significantly worsening the high-frequency output noise.

[0033] To ensure that the FVF has sufficient phase margin without affecting output noise and UGF, this embodiment of the invention designs a dual feedforward zero-point compensation network. In the dual feedforward zero-point compensation network, C Z1 The two ends are respectively connected to M P1 The source and drain are connected via C. Z1 For M P1 Zero-point compensation is performed on the non-dominant poles at the source; C Z2 The two ends are respectively connected to M N1 The source and drain are connected via C. Z2 For M N1 Zero-point compensation is performed at the non-dominant pole at the source. It can be seen that this invention achieves this by placing a capacitor C across MN1 in the cascode branch. Z2 To generate an additional feedforward zero ω Z2 .

[0034] ω Z2 The calculation formula is as follows: ; Due to M N1 transconductance g m，N1 M P1 Much smaller, a small capacitor C of 0.6pF. Z2 This can produce a low ω Z2 To compensate for ωM, and ω Z1 This can be achieved by placing it at a much higher frequency to compensate for ω. SUP In this embodiment of the invention, a 1.5pF C Z1 Sufficient to achieve a phase margin of 88° (see Figure 3 This effectively suppresses noise feedthrough. Figure 4 The simulation results show that the feedforward compensation scheme proposed in this invention reduces the output noise at 10 / 100MHz by a factor of 1.2 / 4.

[0035] Furthermore, using two feedforward zeros enables the LDO to support a wide load range, for example, even when I LOAD Even when the current drops to 1 mA, the LDO of this embodiment can maintain a phase margin of >60° (see...). Figure 5 In contrast, while using a series resistor-capacitor (RC) network can also generate a low-frequency zero for ω... M Compensation; however, this RC zero-point generation is accompanied by a parasitic pole, which may lead to ω G Compression (see) Figure 3 The feedforward compensation scheme proposed in this invention has almost no ω. GCompression allows the present invention to maintain high power suppression over a wider bandwidth.

[0036] On the other hand, embodiment M of the present invention P3 and M N2 The load current source M in the error amplifier P2 Voltage biasing circuit; M N2 Gate connection M N5 The drain, M N2 The drain and M P3 Drain connection; M P3 The drain and gate are shorted; M P2 As the active load of the error amplifier, the gate is connected to M. P3 The gate and drain of the circuit are connected to the output node of the error amplifier; in this embodiment of the invention, M... P3 With M N2 For node V N1 Establish a static working point; so that M P2 Using V N1 Voltage as its gate voltage, M P2 The whole as output node V G Active loads improve output node V G DC gain. Embodiment M of the present invention. N5 The drain is connected to the reference current input, and the gate is shorted to the drain and connected to M. N4 The gate, M N5 M N2 M N4 and M N3 Construct a current mirror to proportionally copy the reference current I B .

[0037] Furthermore, in M N5 The drain and M N2 Gate connection, M N4 The gate and M N5 Drain connection and M P4 Drain and M P1 A low-pass filter (LPF) is provided on the gate connection; filtering is performed through the LPF. In this embodiment of the invention, the LPF is used to filter out transistor noise and power supply ripple coupling from the bias circuit. The large resistance in the LPF is implemented by an NMOS transistor operating in the subthreshold region to save area.

[0038] The lack of a large external capacitor causes the power supply rejection (PSR) to decrease as the frequency exceeds the EA bandwidth. While feed-forward ripple cancellation (FFRC) technology can improve the intermediate frequency PSR, adding feedforward and summing amplifiers to implement FFRC functionality degrades output noise, contradicting the low-noise requirements of RO applications. To overcome this noise limitation, this invention proposes an E-FFRC scheme that embeds the functionality of the feedforward and summing amplifiers into the error amplifier.

[0039] Specifically, in the embedded feedforward ripple cancellation network of this embodiment, the error amplifier M is multiplexed. P2 M P3 and M N2 .

[0040] In embedded feedforward ripple cancellation networks, M P2 M P3 and M N2 The feedforward path that constitutes the power supply ripple; where M P2 The source is connected to the power supply voltage input, M P2 The load current source transistor of the error amplifier also serves as the transconductance amplification stage of the power supply ripple feedforward path, transmitting the ripple changes of the power supply voltage to the output terminal of the error amplifier, namely the power output transistor M. P The gate of M; P3 and M N2 The voltage bias circuit is composed of M P2 Provides gate voltage and is also used to control power supply ripple propagation to M. P2 The size of the gate controls the gain of the power supply ripple feedforward path.

[0041] The feedforward path designed in E-FFRC can offset M P The power supply ripple changes from the path feed to the output. Specifically, such as... Figure 6 As shown, this circuit conforms to the following formula: ; Therefore, when the error amplifier At that time, it can be done in V SUP Significant ripple elimination is achieved.

[0042] Low-frequency PSR EA It can be used Figure 7 The small-signal model was used for estimation, showing that M could be adjusted. P2 and M N2 The output impedance ratio (i.e., R) O，P2 / R O，N2 To obtain the required PSR EA RO，P2 and R O，N2 By changing M P2 and M N2 The length of the channel is used to change it.

[0043] Due to the pole ω at the output of EA G It will attenuate power supply ripple at high frequencies, leading to PSR EA Deviation from optimal value. To extend the bandwidth of effective ripple cancellation, this embodiment of the invention introduces a capacitor C in the FFRC path. Z3 C Z3 Connect M at both ends P3 Gate and ground, to be in PSR EA Create a zero point in the transfer function (see Figure 7 ).

[0044] Specifically, in the absence of C Z3 At that time, the PSR of the circuit EA The formula is as follows: ; In the presence of C Z3 At that time, the PSR of the circuit EA The formula is as follows: ; in .

[0045] It can be seen that at high frequencies, the capacitance C Z3 Increased the use of M P2 As g m stage amplifier input (V N1 V DD The ripple amplitude at point ) offset the decrease in voltage gain. Figure 8 Simulation results show that the proposed E-FFRC improves PSR by 26 dB at 10 MHz.

[0046] In addition, E-FFRC will also M P The voltage drop across is relaxed to 0.1V, making this LDO architecture very suitable for cascading (see...). Figure 9 Due to the high PSR of LDO1, the noise requirements of LDO2 are significantly relaxed. By setting the quiescent current of LDO2 to one-quarter of that of LDO1, the output noise of the cascaded LDOs increases by only 1.03 times at 100MHz (see...). Figure 10 ), while the PSR at 10MHz improved to < 100dB (see) Figure 9 ).

[0047] For example, to measure the PSNR of a voltage-regulated RO equipped with an embodiment of the present invention, a frequency of f is injected into the power supply via a bias tee. n,sin 50mV pp Sine wave signal as V DD The ripple changes. In f RO =6GHz and f n,sin At 20MHz, the measured spurious emissions with and without the on-chip LDO were respectively... 73 and 15.4 dBc (see Figure 10 ,11), it can be seen that the voltage-regulated RO of the present invention is equipped with PSNR reached 88.4dB, achieving best-in-class design performance.

[0048] In summary, this invention employs dual feedforward zero-point compensation technology. Compared to single feedforward zero-point compensation, it eliminates the need for large capacitors to generate low-frequency zeros, reducing high-frequency noise fed through the LDO to the output and lowering the sources of LDO output noise. It maintains the LDO's large bandwidth while ensuring sufficient phase margin and stability across a wide current range from light to heavy loads. Furthermore, the LDO architecture based on a flip-flop voltage follower allows for fewer components in its error amplifier, thus reducing output noise sources. Simultaneously, its unique embedded feedforward ripple cancellation technology based on a flip-flop voltage follower significantly improves power supply rejection in the mid-to-high frequency range without introducing additional noise sources. Its low voltage drop characteristic enables multi-stage cascading, further optimizing overall performance. This invention effectively solves the inherent problems of limited PSNR improvement, the need for large external capacitors, or the sacrifice of power efficiency in traditional power supply noise suppression technologies, simultaneously achieving low output noise, high power supply rejection ratio, and stable operation over a wide load range.

[0049] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0050] Furthermore, the terms "first," "second," etc., used in the embodiments of this invention are for descriptive purposes only and should not be construed as indicating or implying relative importance, or implicitly specifying the number of technical features indicated in this embodiment. Therefore, features defined with terms such as "first" and "second" in the embodiments of this invention can explicitly or implicitly indicate that the embodiment includes at least one of those features. In the description of this invention, the word "multiple" means at least two or more, such as two, three, four, etc., unless otherwise explicitly specified in the embodiments.

[0051] In embodiments of the present invention, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of the present invention may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0052] Although embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention. Other embodiments of the present invention will readily conceive of by considering the specification and practicing the invention. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the following claims.

Claims

1. An LDO circuit based on a flip-flop voltage follower and dual feedforward zero-point stability compensation, characterized in that, This includes a flip-flop voltage follower, a dual feedforward zero-point compensation network, an embedded feedforward ripple elimination network, a bias network, and a level shifting circuit. The aforementioned flip-flop voltage follower includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a third NMOS transistor, and a power output PMOS transistor; wherein the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the third NMOS transistor constitute an error amplifier for dynamically adjusting the output voltage of the power output PMOS transistor; the drain node of the power output PMOS transistor serves as the output voltage node of the LDO circuit; The dual feedforward zero-point compensation network includes a first feedforward compensation capacitor and a second feedforward compensation capacitor; wherein the first feedforward compensation capacitor is connected in parallel with the source and drain of the first PMOS transistor to generate a first left half-plane zero for frequency compensation; the second feedforward compensation capacitor is connected in parallel with the source and drain of the first NMOS transistor to generate a second left half-plane zero for frequency compensation. The embedded feedforward ripple cancellation network includes a multiplexed second PMOS transistor, a third PMOS transistor, and a second NMOS transistor; the embedded feedforward ripple cancellation network is used to eliminate noise from the power supply voltage; The bias network includes a second PMOS transistor, a third PMOS transistor, a second NMOS transistor, a fifth NMOS transistor, and a bandwidth extension capacitor; the bias network is used to provide the error amplifier with the correct DC operating point to ensure sufficient DC gain, while controlling the gain of the power supply ripple feedforward path. The level shifting circuit includes a fourth PMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor; the level shifting circuit is used to make the output DC voltage of the LDO circuit equal to the reference voltage.

2. The LDO circuit based on a flip-flop voltage follower and dual feedforward zero-point stability compensation according to claim 1, characterized in that, In the flip voltage follower and level shifter circuit, the third NMOS transistor, the fourth NMOS transistor, and the fifth NMOS transistor form a current mirror; at the same time, the ratio of the source-drain current flowing through the first PMOS transistor and the fourth PMOS transistor is equal to the ratio of the width to the length of the first PMOS transistor and the fourth PMOS transistor, so the gate-source voltages of the first PMOS transistor and the fourth PMOS transistor are equal. Since the first PMOS transistor and the fourth PMOS transistor share the same gate voltage, the source voltages of the first PMOS transistor and the fourth PMOS transistor are equal, that is, the output DC voltage and the reference voltage of the LDO circuit are equal. The first PMOS transistor, together with the first NMOS transistor and the third NMOS transistor, forms a folded cascode structure. The connection node between the drain of the first PMOS transistor and the drain of the third NMOS transistor serves as the folding node of the folded cascode structure. The source of the first PMOS transistor is connected to the drain of the power output PMOS transistor to receive the output feedback voltage from the power output PMOS transistor. The gate of the first PMOS transistor is connected to the drain of the fourth PMOS transistor, so that the gate voltage bias of the first PMOS transistor is set by level shifting from the reference voltage. The source of the third NMOS transistor is grounded, and its gate is connected to the drain of the fifth NMOS transistor. The source of the first NMOS transistor is connected to the folded node of the folded common-source common-gate transistor, and the drain is connected to the gate node of the power output PMOS transistor. The gate is connected to a fixed bias voltage.

3. The LDO circuit based on a flip-flop voltage follower and dual feedforward zero-point stability compensation according to claim 2, characterized in that, In the flip voltage follower and level shifting circuit, the fourth PMOS transistor, the fourth NMOS transistor, and the fifth NMOS transistor are used to shift and transfer the level of the reference voltage to the first PMOS transistor; the folded common-source common-gate error amplifier composed of the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the third NMOS transistor is used to amplify the difference between the output feedback voltage and the input reference voltage, and is used to regulate the gate voltage of the power output PMOS transistor so that the output feedback voltage of the power output PMOS transistor tends to be stable.

4. The LDO circuit based on a flip-flop voltage follower and dual feedforward zero-point stability compensation according to claim 1, characterized in that, In the dual feedforward zero-point compensation network, the two ends of the first feedforward compensation capacitor are respectively connected to the source and drain of the first PMOS transistor, and the non-major pole at the source of the first PMOS transistor is zero-point compensated through the first feedforward compensation capacitor; the two ends of the second feedforward compensation capacitor are respectively connected to the source and drain of the first NMOS transistor, and the non-major pole at the source of the first NMOS transistor is zero-point compensated through the second feedforward compensation capacitor.

5. The LDO circuit based on a flip-flop voltage follower and dual feedforward zero-point stability compensation according to claim 1, characterized in that, In the bias network, the third PMOS transistor and the second NMOS transistor generate the bias voltage of the second PMOS transistor, which constitutes the load current source in the error amplifier; the second NMOS transistor and the fifth NMOS transistor form a current mirror and share the same gate voltage; the drain of the second NMOS transistor is connected to the drain of the third PMOS transistor; the drain of the third PMOS transistor is shorted to the gate. The second PMOS transistor serves as the active load of the output voltage node of the error amplifier, with its gate connected to the gate of the third PMOS transistor and its drain connected to the gate of the power PMOS transistor. The bias network is used to provide a bias voltage to the active load formed by the second PMOS.

6. The LDO circuit based on a flip-flop voltage follower and dual feedforward zero-point stability compensation according to claim 5, characterized in that, In the embedded feedforward ripple elimination network, the second PMOS transistor, the third PMOS transistor, and the second NMOS transistor form the feedforward path for the power supply ripple. The source of the second PMOS transistor is connected to the power supply voltage input. The second PMOS transistor serves as the load current source of the error amplifier and is also the transconductance amplification stage of the power supply ripple feedforward path, transmitting the ripple change of the power supply voltage to the output terminal of the error amplifier, i.e., the gate of the power output PMOS transistor. The third PMOS transistor and the second NMOS transistor form a voltage bias circuit to provide the gate voltage of the second PMOS transistor, and at the same time, it is used to control the magnitude of the power supply ripple transmitted to the gate of the second PMOS transistor, thereby controlling the gain of the power supply ripple feedforward path.

7. The LDO circuit based on a flip-flop voltage follower and dual feedforward zero-point stability compensation according to claim 6, characterized in that, In the embedded feedforward ripple cancellation network, the power supply voltage ripple change transmitted by the second PMOS transistor is out of phase and matches the ripple change received by the source of the power output PMOS transistor from the power supply voltage input, thus achieving ripple cancellation at the drain of the power output PMOS transistor.

8. An LDO circuit based on a flip-flop voltage follower and dual feedforward zero-point stability compensation according to claim 6, characterized in that, In the embedded feedforward ripple elimination network, the two ends of the bandwidth extension capacitor are respectively connected to the gate of the third PMOS transistor and ground, providing a left half-plane zero in the power ripple feedforward path to extend the bandwidth of the power ripple feedforward.

9. An LDO circuit based on a flip-flop voltage follower and dual feedforward zero-point stability compensation according to claim 1, characterized in that, In the bias network, the fifth NMOS transistor, the second NMOS transistor, and the fourth NMOS transistor form a current mirror; the drain of the fifth NMOS transistor is connected to the reference current input, and its gate is shorted to the drain and connected to the gates of the second and fourth NMOS transistors, providing a bias voltage for the second and fourth NMOS transistors.

10. An LDO circuit based on a flip-flop voltage follower and dual feedforward zero-point stability compensation according to claim 1, characterized in that, Low-pass filters are provided at the connections between the drain of the fifth NMOS transistor and the gate of the second NMOS transistor, the drain of the fifth NMOS transistor and the gate of the fourth NMOS transistor, and the drain of the fourth PMOS transistor and the gate of the first PMOS transistor; filtering is performed through the low-pass filters.

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