A low-cost high-reliability startup loading redundancy backup method, system, computer device and storage medium for a spaceborne information system

Abstract

The application provides a low-cost and high-reliability starting loading redundancy backup method and system for a satellite-borne information system, computer equipment and a storage medium. After the satellite-borne information system is powered on, a three-out-of-two anti-fuse FPGA loads a first-level boot program for each non-FPGA processor from an SPI Flash. When the detection of the first-level boot program loading of a certain non-FPGA processor fails, the first-level boot program is scanned and repaired. After the first-level boot program of the main control CPU is successfully started and loaded, the operating system image file of the main control CPU is read from a solid state disk array in a three-out-of-two manner. If the reading fails, the operating system image file is repaired. After the reading is successful, the operating system image file is loaded to the main control CPU to complete the starting of the main control CPU. After the operating system of the main control CPU is started, the main control CPU management software is run to create starting loading threads for the remaining non-FPGA processors and FPGA processors, respectively, and to completely start and load each processor.

Description

Technical Field

[0001] This invention belongs to the field of aerospace electronics and spaceborne information processing technology, and particularly relates to a low-cost, high-reliability startup loading redundancy backup method, system, computer equipment, and storage medium for spaceborne information systems. Background Technology

[0002] Due to the influence of high-energy particles and other factors in the space environment, the non-volatile memory used to store boot programs and operational software in spaceborne information systems is at risk of being damaged by single-event upsets, cumulative damage, and other effects. To ensure that the onboard processors can reliably start throughout their entire on-orbit lifespan, traditional designs typically configure several high-reliability Flash chips for each processor, using triple-modular redundancy storage for the primary boot program and critical operational software. A safety control FPGA is responsible for loading the boot program for each processor using a two-out-of-three method and monitoring the correctness of the Flash data. If necessary, erroneous data is repaired via ground-based injection.

[0003] As the complexity of on-orbit intelligent processing services continues to increase, satellites often need to deploy multiple high-performance CPUs, DSPs, NPUs, GPUs, and multiple FPGAs. In traditional solutions, if each processor uses independent tri-mode Flash redundancy, the boot program and image files are scattered and stored in a large number of high-reliability Flash memory locations. This not only results in a large number of chips, high costs, and severe board-level resource consumption, but also low Flash capacity utilization, making it difficult to meet the storage requirements of large-capacity operating system images and multiple versions of business software.

[0004] Furthermore, in traditional solutions, each processor typically reads large data files directly from Flash memory via the antifuse FPGA's SPI interface. Limited by bus bandwidth, this results in slow overall boot loading speeds. In applications requiring frequent resets or rapid restarts, this severely impacts the fault tolerance and business continuity of the onboard information system. Therefore, there is an urgent need for a redundant backup method for onboard information system boot loading that, while ensuring high reliability, reduces the number of high-reliability Flash chips, improves storage resource utilization, and significantly enhances boot loading speed. Summary of the Invention

[0005] This invention provides a low-cost, high-reliability startup loading and redundant backup method, system, computer equipment, and storage medium for spaceborne information systems. This addresses the technical problems of high cost, slow startup speed, and low storage resource utilization in conventional spaceborne information device startup loading schemes. While ensuring high-reliability storage and loading of each processor's boot program and operating system image, it reduces the number of high-reliability Flash chips, simplifies the system structure, and improves system reset and restart efficiency.

[0006] To solve the above problems and achieve the above objectives, the technical solution of the present invention is as follows: a low-cost, high-reliability startup loading redundancy backup method for a spaceborne information system, applied to a spaceborne information system including a security management module, a high-performance information processor, and a storage module, comprising the following steps: After the onboard information system is powered on, the anti-fuse FPGA in the security control module loads the first-level boot program from three high-reliability SPI Flash chips using a three-out-of-two loading method for each non-FPGA type processor in the high-performance information processor. Each of the three SPI Flash chips has an independent first-level boot program storage area for each non-FPGA type processor, and the storage content of the corresponding storage areas in the three SPI Flash chips is consistent. When the loading of the primary bootloader of a non-FPGA processor fails, the privileged mode of the antifuse FPGA is entered. The primary bootloader of the processor is scanned and repaired according to the remote control command. After the repair is completed, the primary bootloader is reloaded. After the primary boot program of the main control CPU in the high-performance information processor is successfully loaded, the primary boot program of the main control CPU reads the operating system image file of the main control CPU from the solid-state disk array in the storage module through the PCIe interface in a 2 out of 3 manner. If the reading fails, it enters the abnormal repair mode to repair the operating system image file. After the reading is successful, the operating system image file is loaded into the main control CPU to complete the boot of the main control CPU. After the main control CPU operating system starts, the main control CPU management software is run to create startup loading threads for each of the remaining non-FPGA and FPGA processors in the high-performance information processor, and to perform a full startup loading for each processor.

[0007] In one or more embodiments, the privileged mode includes performing the following steps: Receive and parse remote control commands; When a bootloader scan instruction is received for a non-FPGA processor, the correctness of the three primary bootloaders corresponding to that processor in the three SPI Flash chips is checked, and the scan results of each primary bootloader are returned via telemetry. When a bootloader self-repair instruction is received for a non-FPGA processor, it is determined whether a correct version exists among the three primary bootloaders. If a correct version exists, the correct version is used to overwrite and repair the damaged version. If all three primary bootloaders are damaged, the self-repair operation is not performed, and the result is fed back via telemetry. When a bootloader injection repair instruction is received for a non-FPGA type processor, the bootloader injection repair switch for that processor is turned on. After receiving the bootloader injection data packet, the injection data is written to the corresponding first-level bootloader storage partition to repair the damaged first-level bootloader.

[0008] In one or more embodiments, the anomaly repair mode of the main control CPU primary boot program includes performing the following steps: If a data reading error is detected during the process of reading the main control CPU operating system image file through the PCIe interface (selecting two out of three), the error information is reported via telemetry. Based on the on-orbit injection data packets sent from the ground, the operating system image file is repaired, and after the repair is completed, a three-out-of-two read and load operation is performed again.

[0009] In one or more embodiments, the processing flow of the startup loading thread created for each non-FPGA type processor in the main control CPU management software includes the following steps: The operating system image file of the corresponding non-FPGA processor is read from the storage module in a 3-out-of-2 manner. If the reading fails, the error information is fed back through telemetry and the system enters the exception handling mode. The operating system image file is repaired according to the on-orbit injection data packet. After the operating system image file is successfully read, it is sent to the primary bootloader of the corresponding non-FPGA processor via the network port. The primary bootloader then completes the boot loading of the corresponding non-FPGA processor.

[0010] In one or more embodiments, the processing flow of the startup loading thread created for each FPGA class processor in the main control CPU management software includes the following steps: The corresponding FPGA-type processor's bit loading file is read from the storage module in a 3-out-of-2 manner. If the reading fails, an error message is fed back via telemetry and an exception handling mode is entered. The bit loading file is repaired based on the on-orbit injection data packet. After the bit loading file is successfully read, the corresponding FPGA is reset and set as an SPI slave device, and the master CPU is configured as an SPI master device. The master CPU sends the bit loading file to the corresponding FPGA through the SPI interface, and the FPGA completes the startup loading of the bit loading file.

[0011] Based on the same concept, the present invention also provides a low-cost, high-reliability startup loading redundancy backup system for a spaceborne information system, used to execute the low-cost, high-reliability startup loading redundancy backup method for a spaceborne information system as described in any of the above-mentioned methods, comprising: The security control module is used to load the first-level boot program for the non-FPGA processors in the high-performance information processor through a 2 out of 3 method after the on-board information system is powered on, and to scan and repair the first-level boot program of each non-FPGA processor in privileged mode. The high-performance information processor includes a main control CPU and several non-FPGA and FPGA processors. The main control CPU is used to run management software after completing its own operating system startup, and to create startup loading threads for each non-FPGA and FPGA processor and complete the startup loading. The storage module is used to store the operating system image file of the main control CPU, the operating system image files of each non-FPGA processor, and the bit loading file of each FPGA processor in a triple-modal redundancy manner, and is connected to the main control CPU through the PCIe interface.

[0012] In one or more embodiments, the security management module is equipped with an antifuse FPGA and three high-reliability SPI Flash chips. Each of the three SPI Flash chips has an independent first-level boot program storage area for each non-FPGA type processor. The storage content of the corresponding storage areas in the three SPI Flash chips is consistent. The antifuse FPGA is connected to the SPI boot loading interface of each non-FPGA type processor to realize the three-out-of-two boot loading of the first-level boot program.

[0013] In one or more embodiments, the storage module is a solid-state drive (SSD) storage array, which is connected to the main control CPU via a PCIe 3.0 interface. All processors in the high-performance information processor, except for the main control CPU, access the storage module through the main control CPU.

[0014] Based on the same concept, the present invention also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, it implements the low-cost, high-reliability startup loading redundancy backup method for a spaceborne information system as described in any of the above-mentioned methods.

[0015] Based on the same concept, the present invention also provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, it implements the low-cost, high-reliability startup loading redundancy backup method for a spaceborne information system as described in any of the above-mentioned methods.

[0016] Because the present invention adopts the above technical solution, it has the following advantages and positive effects compared with the prior art: This invention provides a low-cost, high-reliability boot loading redundancy backup method, system, computer equipment, and storage medium for a spaceborne information system. By centrally storing the primary boot program of non-FPGA processors in three high-reliability SPI Flash chips, and using an antifuse FPGA to achieve tri-modal redundancy storage and a 2-out-of-3 loading mechanism, the number of high-reliability Flash chips is significantly reduced while maintaining high boot program reliability, thus lowering hardware costs and simplifying PCB layout. A large-capacity solid-state drive array is used to centrally store the operating system images and FPGA bit loading files for each processor, which are then read at high speed by the main control CPU via a PCIe interface. This significantly improves the reading speed of large data loading files and shortens system reset and restart time. Simultaneously, both the antifuse FPGA and the main control CPU support scanning, self-repair, and on-orbit repair of the boot program and image files, improving the system's maintainability and on-orbit survivability in complex space environments. Attached Figure Description

[0017] Figure 1 This invention provides a schematic diagram of the structure of a low-cost, high-reliability startup and loading redundant backup system for a spaceborne information system; Figure 2 A schematic diagram of the process of loading the first-level boot program of each processor in the anti-fuse FPGA in the security management module provided by the present invention; Figure 3 The present invention provides a schematic diagram of the process for handling exceptions during startup of an antifuse FPGA in privileged mode. Figure 4 The present invention provides a schematic diagram of the process by which the main control CPU first-level boot program starts and loads its own operating system image file. Figure 5 The flowchart of the main control CPU management software startup and loading of other processor software provided by the present invention is shown in the figure. Detailed Implementation

[0018] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a low-cost, high-reliability startup loading redundancy backup method, system, computer equipment, and storage medium for a spaceborne information system proposed in this invention. The advantages and features of this invention will become more apparent from the following description and claims.

[0019] First Embodiment This embodiment provides a low-cost, high-reliability startup and redundant backup method for spaceborne information systems.

[0020] like Figure 1As shown, the entire onboard information system's low-cost, high-reliability boot loading redundant backup system consists of a security management module, a high-performance information processor, and a storage module. The security management module, composed of an antifuse FPGA and a high-reliability SPI Flash, is used to complete the first-stage secure boot loading and on-orbit repair of the boot program. The high-performance information processor deploys high-performance computing resources such as CPUs, DSPs, NPUs, GPUs, and FPGAs as needed to perform complex processing tasks of onboard payload data. The storage module consists of a large-capacity solid-state drive storage array, used to store payload data, large-capacity operating system image files of each processor, and FPGA bit loading files.

[0021] Specifically, the security management module uses an antifuse FPGA connected to three high-reliability SPI Flash chips. Each SPI Flash chip has an independent primary bootloader storage area for each non-FPGA processor in the high-performance information processor (excluding the FPGA). The contents of the corresponding storage areas in the three SPI Flash chips are completely identical, thus achieving triple-modal redundancy backup of the primary bootloader for all non-FPGA processors. The antifuse FPGA in the security management module is connected to the SPI boot loading interface of each non-FPGA processor to distribute the primary bootloader to each processor.

[0022] The storage module employs a large-capacity solid-state drive (SSD) array. The SSDs are connected to the main control CPU in the high-performance information processor via a PCIe 3.0 interface. All processors in the high-performance information processor, except for the main control CPU, access the storage module through the main control CPU. To improve software loading efficiency, after completing its own boot process, the main control CPU is responsible for reading the operating system image file and FPGA bit loading file from the storage module.

[0023] High-performance information processors deploy high-performance CPUs, DSPs, NPUs, GPUs, and FPGAs as needed. Each processor is connected to the main control CPU via Ethernet or other high-speed interconnect buses. The FPGA's SPI boot loading interface is connected to the main control CPU's SPI peripheral interface, so that the main control CPU can load bit loading files to each FPGA through the SPI interface under the control of its management software.

[0024] The specific steps of the low-cost, high-reliability startup, loading, and redundancy backup method for spaceborne information systems include: After the onboard information system is powered on, such as Figure 2As shown, the antifuse FPGA first loads the primary boot program of each non-FPGA processor from three high-reliability SPI Flash chips using a two-out-of-three selection method. When the primary boot program of a certain processor fails to load, the antifuse FPGA reports the error information via telemetry. Simultaneously, in privileged mode, it can scan and repair the primary boot program of that processor according to remote control commands.

[0025] Specifically, such as Figure 3 As shown, the antifuse FPGA in the safety control module can enter privileged mode after power-on. The main functions of privileged mode include: receiving and parsing remote control commands from the ground; when receiving a bootloader scan command for a non-FPGA processor, verifying the data correctness of the three primary bootloaders corresponding to that processor in the three SPI Flash chips, and feeding back the scan results of each bootloader through telemetry information; when receiving a bootloader self-repair command, the antifuse FPGA first determines whether there is at least one correct version among the three bootloaders. If so, it overwrites and repairs the incorrect version with the correct version; if all three bootloaders are damaged, it does not perform the self-repair operation and feeds back the repair results through telemetry information; when receiving a bootloader uploading repair command, the antifuse FPGA turns on the bootloader uploading repair switch of the corresponding processor. When it receives the bootloader uploading data packet for that processor and the repair switch is in the open state, it writes the uploading data into the primary bootloader storage partition of the corresponding processor to achieve on-orbit uploading repair of the damaged bootloader.

[0026] After the primary boot program of the main control CPU in the high-performance information processor is successfully loaded (two out of three options), such as Figure 4 As shown, the main control CPU's primary bootloader reads the operating system image file from the solid-state drive array via the PCIe interface using a 2-out-of-3 approach. During the read process, if an error is detected, the error is reported telemetryally, and the system enters an anomaly repair mode. In this mode, the operating system image file is repaired based on data packets transmitted from the ground in orbit. After repair, the 2-out-of-3 read operation is performed again. Upon successful read, the main control CPU's primary bootloader loads the operating system image file into memory and completes the full boot of the main control CPU.

[0027] After the main control CPU completes booting and enters the operating system, such as Figure 5 As shown, the main control CPU management software runs automatically. In the management software, startup loading threads are created for all other processors of the high-performance information processor. The startup loading threads are divided into non-FPGA processor startup loading threads and FPGA processor startup loading threads.

[0028] In the non-FPGA processor boot loading thread, the main control CPU reads the corresponding processor's operating system image file from the solid-state drive storage array in a 2 out of 3 manner. If the image file reading fails, the error information is fed back via telemetry, and the system enters an exception handling mode. The operating system image file is repaired according to the on-orbit injection data packet, and then read again after the repair is completed. After successful reading, the main control CPU sends the image file to the corresponding processor's primary boot program via the network port, and the primary boot program completes the boot loading of the corresponding processor.

[0029] In the FPGA-type processor startup loading thread, the main control CPU reads the corresponding FPGA's bit loading file from the solid-state storage array in a 2 out of 3 manner. If the bit loading file reading fails, it sends an error message via telemetry and enters an exception handling mode. It repairs the bit loading file based on the on-orbit data packet and then rereads it after repair. If the reading is successful, the main control CPU resets the corresponding FPGA, sets the FPGA as an SPI slave device, and the main control CPU acts as the SPI master device. The main control CPU sends the bit loading file to the FPGA through the SPI interface, and the FPGA completes the startup loading of the bit loading file. The thread exits after execution.

[0030] Second Embodiment Based on the same concept, the present invention also provides a low-cost, high-reliability startup and loading redundancy backup system for a spaceborne information system, used to execute the low-cost, high-reliability startup and loading redundancy backup method for a spaceborne information system as described in any of the first embodiments, comprising: The security control module is used to load the first-level boot program for non-FPGA processors in the high-performance information processor through a 2-out-of-3 method after the onboard information system is powered on, and to scan and repair the first-level boot program of each non-FPGA processor in privileged mode.

[0031] The high-performance information processor includes a main control CPU and several non-FPGA and FPGA processors. The main control CPU is used to run management software after completing its own operating system startup, and to create startup loading threads for each non-FPGA and FPGA processor and complete the startup loading.

[0032] The storage module is used to store the operating system image file of the main control CPU, the operating system image files of each non-FPGA processor, and the bit loading file of each FPGA processor in a triple-modal redundancy manner, and is connected to the main control CPU through the PCIe interface.

[0033] Specifically, the security control module is equipped with an antifuse FPGA and three high-reliability SPI Flash chips. Each of the three SPI Flash chips has an independent first-level boot program storage area for each non-FPGA processor. The storage content of the corresponding storage areas in the three SPI Flash chips is consistent. The antifuse FPGA is connected to the SPI boot loading interface of each non-FPGA processor to realize the two-out-of-three boot loading of the first-level boot program.

[0034] The storage module is a solid-state drive (SSD) storage array. The SSD storage array is connected to the main control CPU via a PCIe 3.0 interface. All processors in the high-performance information processor, except for the main control CPU, access the storage module through the main control CPU.

[0035] The functional implementation of each component in the aforementioned low-cost, high-reliability startup loading redundancy backup system for spaceborne information systems corresponds to the steps in the aforementioned embodiments of the low-cost, high-reliability startup loading redundancy backup method for spaceborne information systems. Their functions and implementation processes will not be elaborated here.

[0036] This embodiment also provides a computer device, including a processor and a memory, wherein the memory stores a computer program, and when the processor executes the computer program, it implements the low-cost, high-reliability startup loading redundancy backup method for a spaceborne information system as described in any one of the first embodiments.

[0037] This embodiment also provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it implements the low-cost, high-reliability startup loading and redundancy backup method for a spaceborne information system as described in any one of the first embodiments.

[0038] In summary, this invention provides a low-cost, high-reliability boot loading redundancy backup method, system, computer equipment, and storage medium for spaceborne information systems. Specifically, the antifuse FPGA only requires three externally connected high-reliability SPI Flash chips to achieve tri-modal redundancy backup of the primary boot program for all non-FPGA processors. Compared to the traditional approach of configuring three high-reliability Flash chips for each processor, this significantly reduces the number of high-reliability Flash chips and PCB-level resource consumption, thus significantly lowering hardware costs. A large-capacity solid-state disk array is used to centrally store various operating system images and FPGA bit loading files, which are then read at high speed by the main control CPU via a PCIe interface. Compared to the traditional approach of directly reading large amounts of loading files through the antifuse FPGA's SPI interface, the boot loading speed is greatly improved, enhancing the timeliness and availability of information system reset and restart fault tolerance measures. Furthermore, both the antifuse FPGA and the main control CPU support scanning, self-repair, and uploading repair of boot programs and image files, giving the system good on-orbit maintenance capabilities and high overall reliability.

[0039] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments. Even if various changes are made to the present invention, if these changes fall within the scope of the claims of the present invention and their equivalents, they shall still fall within the protection scope of the present invention.

Claims

1. A low-cost, high-reliability startup and redundant backup method for a spaceborne information system, applied to a spaceborne information system including a security management module, a high-performance information processor, and a storage module, characterized in that... Includes the following steps: After the onboard information system is powered on, the anti-fuse FPGA in the security control module loads the first-level boot program from three high-reliability SPI Flash chips using a three-out-of-two loading method for each non-FPGA type processor in the high-performance information processor. Each of the three SPI Flash chips has an independent first-level boot program storage area for each non-FPGA type processor, and the storage content of the corresponding storage areas in the three SPI Flash chips is consistent. When the loading of the primary bootloader of a non-FPGA processor fails, the privileged mode of the antifuse FPGA is entered. The primary bootloader of the processor is scanned and repaired according to the remote control command. After the repair is completed, the primary bootloader is reloaded. After the primary boot program of the main control CPU in the high-performance information processor is successfully loaded, the primary boot program of the main control CPU reads the operating system image file of the main control CPU from the solid-state disk array in the storage module through the PCIe interface in a 2 out of 3 manner. If the reading fails, it enters the abnormal repair mode to repair the operating system image file. After the reading is successful, the operating system image file is loaded into the main control CPU to complete the boot of the main control CPU. After the main control CPU operating system starts, the main control CPU management software is run to create startup loading threads for each of the remaining non-FPGA and FPGA processors in the high-performance information processor, and to perform a full startup loading for each processor.

2. The low-cost, high-reliability startup, loading, and redundancy backup method for a spaceborne information system as described in claim 1, characterized in that: The privileged mode includes performing the following steps: Receive and parse remote control commands; When a bootloader scan instruction is received for a non-FPGA processor, the correctness of the three primary bootloaders corresponding to that processor in the three SPI Flash chips is checked, and the scan results of each primary bootloader are returned via telemetry. When a bootloader self-repair instruction is received for a non-FPGA processor, it is determined whether a correct version exists among the three primary bootloaders. If a correct version exists, the correct version is used to overwrite and repair the damaged version. If all three primary bootloaders are damaged, the self-repair operation is not performed, and the result is fed back via telemetry. When a bootloader injection repair instruction is received for a non-FPGA type processor, the bootloader injection repair switch for that processor is turned on. After receiving the bootloader injection data packet, the injection data is written to the corresponding first-level bootloader storage partition to repair the damaged first-level bootloader.

3. The low-cost, high-reliability startup, loading, and redundancy backup method for a spaceborne information system as described in claim 1, characterized in that: The anomaly repair mode of the main control CPU's primary boot program includes the following steps: If a data reading error is detected during the process of reading the main control CPU operating system image file through the PCIe interface (selecting two out of three), the error information is reported via telemetry. Based on the on-orbit injection data packets sent from the ground, the operating system image file is repaired, and after the repair is completed, a three-out-of-two read and load operation is performed again.

4. The low-cost, high-reliability startup, loading, and redundancy backup method for a spaceborne information system as described in claim 1, characterized in that: In the main control CPU management software, the processing flow for the startup loading thread created for each non-FPGA processor includes the following steps: The operating system image file of the corresponding non-FPGA processor is read from the storage module in a 3-out-of-2 manner. If the reading fails, the error information is fed back through telemetry and the system enters the exception handling mode. The operating system image file is repaired according to the on-orbit injection data packet. After the operating system image file is successfully read, it is sent to the primary bootloader of the corresponding non-FPGA processor via the network port. The primary bootloader then completes the boot loading of the corresponding non-FPGA processor.

5. The low-cost, high-reliability startup, loading, and redundancy backup method for a spaceborne information system as described in claim 1, characterized in that: In the main control CPU management software, the processing flow for the startup loading thread created for each FPGA type processor includes the following steps: The corresponding FPGA-type processor's bit loading file is read from the storage module in a 3-out-of-2 manner. If the reading fails, an error message is fed back via telemetry and an exception handling mode is entered. The bit loading file is repaired based on the on-orbit injection data packet. After the bit loading file is successfully read, the corresponding FPGA is reset and set as an SPI slave device, and the master CPU is configured as an SPI master device. The master CPU sends the bit loading file to the corresponding FPGA through the SPI interface, and the FPGA completes the startup loading of the bit loading file.

6. A low-cost, high-reliability startup and redundant backup system for a spaceborne information system, characterized in that: A method for implementing a low-cost, high-reliability startup and redundant backup method for a spaceborne information system as described in any one of claims 1-5, comprising: The security control module is used to load the first-level boot program for the non-FPGA processors in the high-performance information processor through a 2 out of 3 method after the on-board information system is powered on, and to scan and repair the first-level boot program of each non-FPGA processor in privileged mode. The high-performance information processor includes a main control CPU and several non-FPGA and FPGA processors. The main control CPU is used to run management software after completing its own operating system startup, and to create startup loading threads for each non-FPGA and FPGA processor and complete the startup loading. The storage module is used to store the operating system image file of the main control CPU, the operating system image files of each non-FPGA processor, and the bit loading file of each FPGA processor in a triple-modal redundancy manner, and is connected to the main control CPU through the PCIe interface.

7. The low-cost, high-reliability startup and loading redundant backup system for a spaceborne information system as described in claim 6, characterized in that, The security management module is equipped with an antifuse FPGA and three high-reliability SPI Flash chips. Each of the three SPI Flash chips has an independent first-level boot program storage area for each non-FPGA processor. The storage content of the corresponding storage areas in the three SPI Flash chips is consistent. The antifuse FPGA is connected to the SPI boot loading interface of each non-FPGA processor to realize the two-out-of-three boot loading of the first-level boot program.

8. The low-cost, high-reliability startup and loading redundant backup system for a spaceborne information system as described in claim 6 or 7, characterized in that, The storage module is a solid-state drive (SSD) storage array, which is connected to the main control CPU via a PCIe 3.0 interface. All processors in the high-performance information processor, except for the main control CPU, access the storage module through the main control CPU.

9. A computer device, comprising a memory and a processor, characterized in that, The memory stores a computer program, and when the processor executes the computer program, it implements the low-cost, high-reliability startup loading redundancy backup method for a spaceborne information system as described in any one of claims 1-5.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the low-cost, high-reliability startup loading and redundancy backup method for spaceborne information systems as described in any one of claims 1-5.

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