Operation device based on non-zero starting non-hole coding and dynamic error correction method

Abstract

The application discloses an operation device and method based on non-0 starting non-cavity coding. By mapping all-0 coding to a non-zero reference value, using a negative number of inverse code, a full-field coding system without negative zero redundancy and coding cavity is constructed, and the bit-by-bit inversion and carry injection operations required by the traditional complement code are completely eliminated. Full-field coding can realize addition and subtraction operations only by switching the reference mirror image, and addition and subtraction have isomorphism, and the efficiency of multiplication and division operations is close, so that the iteration delay of division is significantly reduced. The application has the advantages of small hardware overhead, high operation efficiency, strong compatibility and expansibility, and is suitable for high-performance operation scenes such as CPU, GPU, AI accelerator, DSP and embedded processor.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design technology, specifically relating to a binary arithmetic device and a dynamic error correction method, applicable to the design of high-performance computing chips such as CPUs, GPUs, AI accelerators, DSPs, and embedded processors. Background Technology

[0002] Currently, integrated circuit computing chips generally use the traditional two's complement encoding system to implement arithmetic operations. Although this system is a classic and widely used technical solution in the industry, with the iterative upgrading of computing power requirements, it has exposed many inherent technical defects that are difficult to avoid, becoming a core bottleneck restricting the development of high-performance computing architectures. First, the generation method of generating negative two's complement numbers by adding 1 to the one's complement requires additional bitwise inversion and carry-in operations for subtraction, resulting in redundant operation steps and a significant increase in hardware overhead. Second, during the operation, the sign flag (SF), carry flag (CF), zero flag (ZF), overflow flag (OF), and parity flag (PF) are interdependent, requiring joint judgment of multiple flags to complete result correction and state determination. Furthermore, separate parity check circuits and all-zero detection circuits are needed, making the control logic and hardware circuitry doubly complex and significantly increasing computational latency. Third, two's complement encoding has redundancy in positive and negative zeros and encoding gaps. The traditional two's complement system suffers from several drawbacks. First, it has low space utilization. Modular operations and data verification require differentiated processing for negative and zero values, leading to inconsistent logic and a high risk of verification errors. Second, traditional architectures require multiple iterative subtraction iterations for division, with each iteration repeating the two's complement transformation process. Iteration delays accumulate rapidly with increasing bit depth, resulting in a severe imbalance between multiplication and division efficiency. It can only achieve efficient addition, subtraction, and multiplication, failing to achieve balanced optimization across all four arithmetic operations. Third, during data verification, zero-starting encoding and two's complement transformation cause irregular changes in the verification value, with the sign bit interfering with the verification result, significantly reducing verification reliability. These inherent shortcomings make the traditional two's complement system ill-suited to the high-performance computing demands of the AI ​​era.

[0003] Although the industry has conducted a lot of research and exploration on the two's complement arithmetic architecture, the existing solutions cannot completely abandon traditional encoding. Therefore, they cannot truly get rid of the path dependence on the two's complement system. They can only make local optimizations rather than underlying reconstructions, and have failed to fundamentally break through the technical constraints of complex symbol judgment, coupled flags, inefficient division, and hardware redundancy. Summary of the Invention

[0004] This invention proposes a non-zero-starting, hole-free encoding computing device and method, optimizing the computing logic from the root of encoding, eliminating redundancy in two's complement transformation, improving overall computing efficiency, and completely eliminating the aforementioned defects. Without increasing hardware complexity or introducing multi-cycle delays, it achieves unified, efficient, and reliable addition, subtraction, multiplication, and division operations, providing a flexible hardware implementation path for mixed binary and decimal operations, numerical verification and modulo operations, and lightweight fixed-point arithmetic cores.

[0005] Breaking away from the traditional rule that all-zero encoding corresponds to the numerical value 0, a new mapping rule is adopted: n-bit binary all-zero encoding (000…0) corresponds to the internal operand value 1, and (000…1) corresponds to the internal operand value 2. The encoding value and the operand value have a linear positive recursive relationship. n-bit all-1 encoding corresponds to the operand value 2ⁿ. This ensures that all 2ⁿ encoding states of the n-bit binary are free of idleness, gaps, and negative zero redundancy. All encodings participate in numerical operations, and there are no discarded encoding combinations. Taking a 4-bit binary non-zero starting encoding operation device as an example, the mapping relationship is as follows: 1) 0000 → 1 2) 0001 → 2 3) 0010 → 3 4) ... 5) 1111 → -1 6) 1110 → -2 7) 1101 → -3 8) ...

[0006] This invention uses a pure one's complement form to represent negative numbers. Negative numbers are directly obtained by inverting the bits of the positive number encoding, eliminating the need for a two's complement transformation (adding 1 to the one's complement), thus simplifying the negative number arithmetic logic. The positive and negative number encodings are highly symmetrical; addition and subtraction can be unified through encoding reference mirror switching, making addition and subtraction operations isomorphically symmetrical. The arithmetic logic is no longer associated with the sign bit; the sign bit only serves as a positive / negative identifier and does not participate in arithmetic control or correction judgment. This results in strong operational consistency, short paths, and effectively reduced computational latency. Taking a 4-bit binary non-zero start encoding arithmetic device as an example, the logical relationship is as follows: 1) Positive number 0000 → 1, one's complement 1111 → -1 2) Positive number 0001 → 2, one's complement 1110 → -2 3) Positive number 0010 → 3, one's complement 1101 → -3

[0007] This invention employs a correction rule based on carry output. No correction is performed when a carry is generated during an operation; otherwise, an increment (or decrement) correction is performed. The entire process requires only one level of correction judgment, eliminating the need for multi-level complex logic, resulting in a simple and efficient correction process.

[0008] After the operation is started, the operation mode (such as addition / subtraction) is first determined. The basic operation is performed by the encoding reference module and the carry signal is output. The correction control unit detects the carry status in real time and generates the corresponding correction control signal. The correction execution module completes the result calibration according to the control signal and the rule of "no correction if there is a carry, add 1 if there is no carry (subtract 1 if there is subtraction)". Finally, the operation result is output.

[0009] This encoding system does not have independent zero-value encoding, so hardware zero-bypass logic is used when the operand is 0.

[0010] The determination of a zero result is based on only two rules: the absolute values ​​of the two operands must be equal, and their sign bits must be opposite. A zero flag ZF is generated by comparing the numerical values ​​and performing an XOR operation on the sign bit, without relying on result encoding. Based on this matching state, the zero flag ZF in the flag register is set to valid, and a constant of all zeros is directly output at the result output stage for use by external instructions, jump checks, and the system level, ensuring the correct presentation of the zero value result and zero flag status. Because there is no need to perform a check on all zeros in the data bits, a zero detection circuit is no longer required, resulting in a minimalist hardware structure and accurate and reliable judgment.

[0011] The encoding system of this invention has symmetrical native switching characteristics. By switching the encoding base mirror, the operation base 0000 can be directly flipped from positive 1 to negative 1 to realize the native subtraction mode. There is no need to regenerate the negative number encoding or invert the bits, forming an equivalent mirror negative number mechanism.

[0012] Forward encoding mode: N-bit binary all-zero encoding corresponds to the dynamic error correction of the base value by adding 1. The encoding increment corresponds to the forward increment of the operation value. The core circuit is equivalent to an adder, which performs addition operations.

[0013] Reverse mirror mode: Adjust the direction of the encoding reference offset. The N-bit binary all-zero encoding corresponds to a dynamic error correction of the reference value by 1. The encoding increment corresponds to a negative decrease in the operation value. The core circuit is equivalent to a subtractor, which performs subtraction operations.

[0014] Mirror mode switching can be achieved simply by changing the SF sign bit flag, without the need for additional arithmetic units, inversion circuits, or dedicated carry chains for two's complement. The architecture is highly symmetrical and versatile.

[0015] The core modules of the computing device include an encoding and mapping unit, a basic addition and subtraction operation unit, a correction control module and a zero flag generation module, a correction execution module, and a result output unit. These modules work together.

[0016] Encoding Mapping Unit: Implements the conversion between external real values ​​and internal non-zero starting codes, and supports encoding mirroring switching control. Basic Addition / Subtraction Unit: Performs basic binary addition and subtraction operations, outputting the original result and the carry-out (COUT) from the highest bit.

[0017] The correction control module and the zero flag generation module are decoupled and work in parallel. The correction control module generates the core control signal based solely on COUT and performs result calibration according to the unified rule of "no correction if there is a carry, plus 1 if there is no carry (minus 1 for subtraction)".

[0018] The correction execution module, centered on a lightweight conditional decrementer, is embedded at the end of the output chain. It achieves increment correction (+1) through mirrored logic of "bitwise inversion + decrement by 1 + bitwise inversion again." Decrement correction is performed directly through the conditional decrementer. This design achieves final correction entirely through combinational logic, without entering the next calculation cycle. It eliminates the need for separate incrementers and incrementer overflow detection logic, resulting in simplified hardware and lower latency. The zero flag generation module consists of a simple combinational logic plus a single-level MUX correction, without complex timing. The process is as follows: encoding / operation → obtaining the original result, initiating duplicate code detection → outputting ZF, and finally using ZF to control the MUX. ZF=1 → MUX selection, outputting a 0 value; ZF=0 → MUX selection, outputting the corrected normal result.

[0019] Output unit: Outputs the corrected standard true value or zero value.

[0020] This invention employs non-zero starting encoding and a mirror operation mechanism, ensuring operational symmetry between addition and subtraction, and between multiplication and division iterations. When implementing division, iterative operations can be completed solely through mirror subtraction, shifting, and unified correction. Therefore, a division mode can be added to the general algorithm level of the overall architecture. Both multiplication and division modes undergo final correction based on predictable errors. Trial addition iterations for multiplication and trial subtraction iterations for division are executed with the same hardware efficiency, eliminating the need for a division accelerator.

[0021] Figure 1 The traditional two's complement arithmetic process in A requires performing two's complement transformations such as inverting and adding 1 on the operands during subtraction, as well as performing multi-level sign and flag joint judgments. The steps are cumbersome and the calculation path is long.

[0022] Figure 1 The B in the diagram represents the computational flow of this invention. Subtraction is performed directly through a mirror encoding method, eliminating the need for two's complement transformation and complex sign judgment. This results in fewer computational steps, a shorter critical path, and higher execution efficiency.

[0023] The device mainly includes an encoding and mapping unit, a basic addition and subtraction operation unit, a correction control module and a zero flag generation module, a correction execution module, and a result output unit. The encoding and mapping unit completes non-zero starting encoding and mirror switching. The basic operation unit outputs the result and carry signal. The carry signal is directly connected to the correction control module. After calibration by the correction execution module, the final operation result is output. The overall structure is simplified and the operation is efficient.

[0024] The diagram mainly includes a data input unit, a logic operation unit, a comparison and judgment unit, and a result output unit. These units are connected sequentially via logic links to achieve rapid zero-value identification and judgment output of the input data. This diagram is merely a schematic representation to aid in understanding the combinational logic implementation of zero-value judgment in this patent's technical solution and does not constitute a limitation on specific circuit structures or connection methods. Beneficial effects

[0025] First, it greatly simplifies the hardware circuit, completely omitting the inverse code plus 1 transformation circuit, all-zero detection large-scale gate circuit, increment overflow detection logic, and independent parity check circuit of the traditional two's complement system. All correction operations can be completed with just one set of inversion circuit and lightweight conditional decrementer. The hardware area and wiring complexity are significantly reduced, the chip layout is more compact, and it is compatible with various lightweight computing terminals and high-density computing clusters.

[0026] Secondly, it eliminates complex state judgment logic. The sign flag, carry flag, zero flag, overflow flag, and parity flag are decoupled from each other, eliminating the need for multi-flag joint judgment and multi-level branch control. The control logic is simple and regular, effectively reducing the operation delay and improving the operation response speed.

[0027] Third, it achieves unified and efficient operation across all modes of addition, subtraction, multiplication, and division. In addition to being compatible with traditional addition, subtraction, and multiplication operation modes, it can directly add a division operation mode. Through mirror operation and unified correction rules, the efficiency of multiplication trial addition iteration and division trial subtraction iteration tends to be consistent, so that the four basic computer arithmetic operations can achieve streamlined processes, efficient execution, and comprehensive and balanced operation performance.

[0028] Fourth, the operation process is highly unified. The addition and subtraction operations adopt mirror isomorphic logic, so there is no need to perform different operation processes based on the positive or negative of the operands. The single-cycle operation latency of addition and subtraction is basically the same, which is suitable for high-performance operation scenarios such as large number operation and high-precision floating-point operation.

[0029] Fifth, the coding space utilization is maximized, there is no redundancy of positive and negative zeros or coding gaps, the numerical coding is continuous and complete, the operation results have no invalid states, and the operation stability and reliability are significantly improved.

[0030] Sixth, the extended operation and verification logic has been optimized, and comprehensive optimizations have been made for parity flag generation, modulo operation, and data verification scenarios. The parity flag can be directly derived through the operation process without the need for additional hardware circuits. Modulo operation does not require special processing for negative numbers. During data verification, the encoding distribution is uniform and the change is regular, and the sign bit does not interfere with the verification calculation, effectively improving the accuracy and stability of verification.

[0031] Seventh, it maintains high compatibility with external interfaces. The sign bit identification rules and flag register functions are completely consistent with the traditional system. There is no need to change the instruction set and external control logic. It can be directly adapted to various computing chip architectures such as CPUs, GPUs, AI accelerators, and DSPs worldwide. The threshold for promotion and application is low, and it has strong versatility and adaptability.

[0032] Eighth, by adopting a non-zero starting encoding rule, the strong coupling between the sign bit and carry in the traditional encoding system is completely decoupled. The output signal is independently extracted and directly drives the correction logic, eliminating the need for complex judgments on the sign bit state. The carry logic adapts to the decimal carry chain, providing a simple hardware path for mixed-base arithmetic architectures.

[0033] Ninth, its computational behavior is predictable and controllable, with stronger robustness. The computational error corresponds strictly to the carry state, with no implicit overflow or random sign flipping. Correction and zero value states are clearly identifiable, improving system reliability and debugging convenience, and making it fully compatible with high-reliability control chips used in military, aerospace, and other fields. Attached Figure Description Figure 1 A comparative diagram of the operation flow of traditional two's complement encoding and the non-zero starting encoding of this invention. Figure 2 The computing device architecture of this invention Figure 3 Zero-value determination combinational logic diagram Detailed Implementation

[0034] Example 1: Positive number + positive number 2 + 2 1) 2 → 0001 2) Calculation: 0001 + 0001 = 0010 3) Carry: COUT = 0 4) Correction: +1 → 0011 5) Decoding: 0011→4, result is correct. Example 2: Positive number − positive number 3 − 5 1) 3→0010, -5→1010 2) Calculation: 0010 + 1010 = 1100 3) Carry: COUT = 0 4) Correction: +1→1101 5) Decoding: 1101 → -3, the result 3 − 5 = -2 is correct. Example 3: Encoding Mirror Switching • Forward: 0000 → +1, equivalent to an adder • Mirror image: 0000 → -1, equivalent subtractor • Only the encoding base is changed; the hardware remains the same.

[0035] Example 4: Mirror-switched addition and subtraction mixed operations, 4+1-7 1) 4→0011, 1→0000 2) Calculation: 0011 + 0000 = 0011 3) Carry: COUT = 0 4) Correction: +1→0100 5) Switch to mirror mode to become a subtraction machine. 6) 0100→-5, 1001→7 2) Calculation: 0100 + 1001 = 10001 3) Carry: COUT = 1 4) Correction: None 5) 0001 → -2 The final result is correct: 4 + 1 − 7 = −2.

Claims

1. A computing device based on non-zero starting, hole-free coding, characterized in that, include: Encoding mapping unit, basic addition and subtraction operation unit, correction control module and zero flag generation module, correction execution module, result output unit; The encoding mapping unit adopts non-zero starting encoding, mapping N bits of binary all-zero encoding to the base value 1. All encoding states are free of holes, redundancy, and negative zeros, and support encoding base mirror switching to achieve equivalent conversion of adder / subtractor functions. Moreover, the switching process does not require inversion circuit and two's complement carry injection. The basic addition and subtraction operation unit is used to perform binary addition and subtraction operations and output the original operation result and the highest bit carry output COUT. The correction control module and the zero flag generation module are used to generate a core control signal based on COUT. The core control signal is used as both a correction enable signal and a zero value flag signal. The correction execution module is configured to perform an increment (or subtraction) correction on the original result based on the core control signal. The result output unit outputs the final calculation result.

2. The computing device according to claim 1, characterized in that, The correction execution module is a conditional decrement / incrementer embedded at the end of the result carry chain, an external increment / decrementer, a dedicated correction circuit, or an equivalent hardware circuit. The entire calculation and correction process does not require two's complement conversion, borrow chain, or absolute value comparison logic.

3. The computing device according to claim 1, characterized in that, The core control signals include a correction control bit, a correction enable signal, and all equivalent control signals with the same function.

4. The computing device according to claim 1, characterized in that, The system's zero value is identified by the core control signal, without relying on all data bits being zero, and no independent zero detection circuit is set up.

5. The computing device according to claim 1, characterized in that, The operation correction rule is unique: no correction is performed when COUT = 1, and an increment (or decrement) correction is performed when COUT = 0, regardless of the specific implementation of the correction hardware.

6. A dynamic error condition correction method based on non-zero starting encoding, characterized in that, include: a. Non-zero starting encoding is adopted. N-bit binary all-zero encoding corresponds to the base value 1. The encoding space is continuous with no idle space and no gaps. b. Perform addition and subtraction operations on the encoded operands, and obtain the carry-out of the highest bit COUT and the original operation result; c. Using COUT as the sole criterion, if there is a carry, the original result is output directly; otherwise, the original result is corrected by incrementing by 1 (or decrementing by 1). d. Correction enable and zero value identification are synchronously achieved by a single core control signal; zero values ​​are not detected by encoding all zeros in the data bits. e. The addition and subtraction functions are converted by switching the encoding reference mirror, without the need for two's complement inversion and carry injection operations.

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