A method for manufacturing a single-mode single-deflection VCSEL chip

Abstract

The application relates to a preparation method of a single-mode single-deflection VCSEL chip. First, a specific beveling angle substrate is used for epitaxial growth to introduce controllable material anisotropy; second, a phase shift mask technology is combined with a self-aligned side wall pattern transfer process, subwavelength period high-precision surface grating manufacturing is realized through one or more times of pattern multiplication by using a conventional I-line stepper photolithography machine. The method perfectly integrates the preparation of high-performance gratings into a standard integrated circuit process, realizes single-mode single-deflection VCSEL production with high yield, low cost, large batch and stable polarization characteristics.

Description

Technical Field

[0001] This invention relates to the field of semiconductor optoelectronic device manufacturing technology, specifically to a method for fabricating a single-mode, single-biased VCSEL chip. Background Technology

[0002] Single-mode, single-polarized VCSELs (Vertical-Cavity Surface-Emitting Lasers) are core light sources for cutting-edge systems such as high-speed coherent optical communication, high-precision lidar, and quantum technology. The key to achieving their superior performance lies in the precise fabrication of a surface grating structure with a subwavelength period (typically 200-400 nanometers) on the output cavity surface of the device. This grating must simultaneously perform two core functions: suppressing higher-order modes to achieve stable single-mode output, and breaking optical symmetry to lock a single linear polarization direction. However, the fabrication of this crucial structure currently faces severe challenges from both patterning processes and physical design dimensions.

[0003] First, existing technologies for high-precision patterning all face significant bottlenecks. Current mainstream methods rely on electron beam lithography or holographic lithography. While electron beam lithography achieves extremely high pattern resolution and design flexibility, it is essentially a serial direct-write process with very low production efficiency, making it difficult to meet the capacity and cost requirements of large-scale commercial production. Holographic lithography, as a parallel processing technology, theoretically possesses high production capacity potential, but its requirements for the stability of the optical system, laser coherence, and the overall flatness of the substrate are extremely stringent. Even minor environmental vibrations, optical path disturbances, or substrate deformation can cause blurring or distortion of interference fringes, resulting in an extremely narrow process window and ultimately making it difficult to reliably guarantee production yield and batch-to-batch repeatability. On the other hand, I-line stepper lithography machines, which are maturely used in the integrated circuit manufacturing industry and have high-volume production capabilities, have direct imaging resolution limited by the exposure wavelength of approximately 365 nanometers and the numerical aperture of the optical system. Constrained by the optical diffraction limit, they are generally unable to directly and reliably process such deep submicron period precision grating patterns.

[0004] Secondly, at the level of polarization control mechanisms, existing solutions suffer from both simplification and fragility. The currently widely relied-upon rectangular grating structure relies primarily on introducing differentiated losses to two orthogonal polarization modes for polarization locking. However, this mechanism is extremely sensitive to the geometric dimensions of the grating structure (such as groove depth, duty cycle, and sidewall perpendicularity). Unavoidable process fluctuations during manufacturing can easily lead to a decrease in polarization control efficiency, or even polarization state jumps, affecting the long-term operational stability of the device.

[0005] Therefore, in order to promote the large-scale, low-cost, and highly consistent manufacturing of single-mode, single-biased VCSELs, the industry urgently needs to develop an integrated technical solution. Summary of the Invention

[0006] To address the aforementioned technical problems, a more robust polarization stabilization mechanism that transcends the single geometric grating effect is provided. This mechanism combines phase-shifting mask technology with self-aligned sidewall patterning, and employs obliquely cut substrates for epitaxial growth to obtain a highly stable single polarization state. The technical solution of this invention is as follows:

[0007] A method for fabricating a single-mode, single-biased VCSEL chip, the key of which includes the following steps:

[0008] Step S1: Prepare a compound semiconductor substrate with a beveled angle;

[0009] Step S2: An epitaxial structure is grown on the substrate surface to form a wafer with an epitaxial structure;

[0010] Step S3: Deposit a hard mask layer on the surface of the wafer;

[0011] Step S4: Photoresist is coated on the hard mask layer, and an I-line stepper lithography machine equipped with a phase-shifting mask is used for exposure and development to form a photoresist pattern.

[0012] Step S5: Etch and transfer the photoresist pattern to the hard mask layer to form a striped initial periodic pattern;

[0013] Step S6: Remove the photoresist and deposit a fill layer on the structural surface of the initial periodic pattern;

[0014] Step S7: Perform anisotropic etching on the filling layer to remove the filling layer in the gaps at the top and bottom of the initial periodic pattern, leaving only the filling layer material on the sidewalls of the initial periodic pattern.

[0015] Step S8: Selectively remove the initial periodic pattern so that the filling layer material is retained independently;

[0016] Step S9: Using the remaining filler material as an etching mask, the epitaxial structure surface of the wafer is etched to form a striped surface grating structure.

[0017] Step S10: Remove all the filler layer material to form a wafer with a surface grating structure;

[0018] Step S11: The wafer with the surface grating structure is processed to prepare light-emitting holes, electrodes, etc.

[0019] Using the above scheme, this scheme combines a resolution-enhancing patterning process with a polarization-stabilized collaborative design. It combines phase-shifting mask technology with self-aligned sidewall patterning process to obtain a fine grating that far exceeds the nominal resolution of the lithography machine. At the same time, it also uses obliquely cut substrates for epitaxial growth and pre-introduces controllable polarization-dependent gain into the material to obtain a highly stable polarization state.

[0020] Furthermore, the oblique angle of the substrate is 2°-10°, and the stripe direction of the surface grating structure is horizontal or perpendicular to the oblique direction of the substrate.

[0021] Using the above scheme, the fringe direction (geometric polarization selection axis) of the grating is deliberately set to be parallel or perpendicular to the oblique tangent direction of the substrate. The parallel design aims to make the material gain anisotropy and the grating screening effect superimposed in the same direction to obtain high power output; the perpendicular design aims to use the strong selectivity of the grating to overcome and lock the polarization tendency of the material itself to obtain a highly stable single polarization state.

[0022] Furthermore, the phase shift mask mentioned in step S4 is an alternating phase shift mask or an attenuation phase shift mask.

[0023] Furthermore, in step S6, the deposition method of the filling layer is atomic layer deposition, plasma-enhanced chemical vapor deposition, or inductively coupled plasma chemical vapor deposition.

[0024] Furthermore, the filling layer is made of silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide, or aluminum nitride.

[0025] The key to a single-mode, single-biased VCSEL chip lies in its fabrication using the method described above.

[0026] Beneficial effects: (1) Resolution breakthrough: This invention effectively halves the period or critical size of optical exposure pattern through innovative self-aligned sidewall process, and successfully breaks through the physical resolution limit of I-line lithography;

[0027] (2) Excellent polarization performance: Combining the dual mechanism of "material anisotropy" and "geometric anisotropy", the extinction ratio and temperature stability of the output polarization are improved by orders of magnitude compared with the single technology path;

[0028] (3) Flexible design: By adjusting the initial pattern of the phase shift mask, the thickness of the filling layer and the etching process, the period, duty cycle and depth of the final grating can be precisely controlled to adapt to different design requirements. Attached Figure Description

[0029] Figure 1 This is a cross-sectional view of the VCSEL chip structure of the present invention;

[0030] Figure 2 This is a cross-sectional schematic diagram of the key steps in the process flow of the present invention;

[0031] Figure 3 A top view schematic diagram showing the relationship between the crystal orientation of the obliquely cut substrate and the orientation of the grating;

[0032] Figure reference numerals: 1-substrate, 2-epitaxy layer, 3-hard mask layer, 4-photoresist, 5-initial periodic pattern, 6-fill layer, 7-grating, 8-N-side electrode, 9-P-side electrode, 21-N-type DBR layer, 22-quantum well active region, 23-oxide layer, 24-P-type DBR layer. Detailed Implementation

[0033] The present application will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that similar or identical parts are referred to by the same reference numerals in the drawings or description. Implementations not shown or described in the drawings are forms known to those skilled in the art. In the description of this application, terms such as "first" and "second" are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0034] Example 1:

[0035] A method for fabricating a single-mode, single-biased VCSEL chip, the key of which includes the following steps:

[0036] Step S1: Select an n-type GaAs substrate 1 with a 6° bevel angle and tilted from (100) towards

[011] .

[0037] Step S2: An 850nm band VCSEL epitaxial layer 2 (including an N-type DBR layer 21, a quantum well active region 22, an oxide layer 23, a P-type DBR layer 24, etc.) is epitaxially grown on the wafer using MOCVD process, and mesa etching and passivation are performed to form a wafer with an epitaxial structure.

[0038] Step S3: Apply an 80 nm thick silicon nitride layer as a hard mask by plasma-enhanced chemical vapor deposition (PECVD) on the wafer surface.

[0039] Step S4: I-line positive photoresist 4 is spin-coated onto the hard mask layer 3 using an alternating phase-shifting mask (APS). This PSM is designed for the target grating 7 period (e.g., a final period of 200nm), with a mask pattern period twice that of the final period (i.e., 400nm), ensuring a 180-degree phase difference between adjacent transparent areas. Exposure is performed using an I-line stepper lithography machine. Due to the phase-shifting effect, the edge contrast of the line pattern imaged on the photoresist 4 is significantly improved. After exposure, development is performed.

[0040] Step S5: The photoresist 4 pattern is transferred to the underlying silicon nitride hard mask layer by reactive ion etching (RIE) to form a striped initial periodic pattern 5 (period 600nm, linewidth approximately 300nm).

[0041] Step S6: Remove the photoresist 4 and deposit a silicon dioxide filling layer 6 on the structural surface of the initial periodic pattern 5 using atomic layer deposition. The thickness of the filling layer 6 is precisely controlled to be half the linewidth of the target grating 7 (for example, if the target linewidth is 150nm, then deposit 75nm). This thickness directly determines the final linewidth of the grating 7.

[0042] Step S7: Use gases such as CHF3 to perform anisotropic etching on the filling layer 6. The etching rate in the vertical direction is much higher than that in the horizontal direction. Remove the silicon dioxide filling layer 6 in the gap between the top and bottom of the initial periodic pattern 5, leaving only the sidewalls of the silicon dioxide filling layer 6 on the sidewalls of the initial periodic pattern 5.

[0043] Step S8: Use hot phosphoric acid solution to selectively remove the initial periodic pattern 5, so that the filling layer 6 material remains independently. At this time, only a row of independent silica sidewall lines with a period of 300nm (half of the initial period of 600nm) remains.

[0044] Step S9: Using the remaining sidewalls of the silicon dioxide filling layer 6 as an etching mask, chlorine-based ICP etching is performed to etch the surface layer of the epitaxial structure of the wafer, forming a striped surface grating 7 structure.

[0045] Step S10: Use buffered hydrofluoric acid solution to remove all silicon dioxide sidewalls to form a wafer with a surface grating 7 structure;

[0046] Step S11 involves fabricating light-emitting holes and electrodes, cleaving, and encapsulating the wafer with the surface grating 7 structure.

[0047] The key point of this embodiment is that, in the initial photolithography pattern design, the line direction of the initial pattern is set to be perpendicular to the oblique cutting direction of the substrate 1

[011] . Therefore, the stripe direction of the finally formed grating 7 is also perpendicular to the oblique cutting direction. This means that the geometric polarization selection axis of the grating 7 is orthogonal to the material gain advantage axis. By optimizing the depth of the grating 7 (approximately 100 nm) and the duty cycle (approximately 0.5), the grating 7 effect can be made dominant, thereby stably locking the output polarization in the direction perpendicular to the oblique cutting direction of the substrate 1, achieving a high extinction ratio.

[0048] Example 2:

[0049] A method for fabricating a single-mode, single-biased VCSEL chip, the key of which includes the following steps:

[0050] Step S1: Select an n-type GaAs substrate 1 with a 10° bevel angle and biased towards the

[011] crystal orientation;

[0051] Step S2: An 850nm band VCSEL epitaxial layer 2 (including n-DBR, multi-quantum well active region, p-DBR, etc.) is epitaxially grown on it using MOCVD process, and mesa etching and passivation are performed to form a wafer with epitaxial structure.

[0052] Step S3: A 100 nm thick silicon nitride (SiN) layer is deposited on the wafer surface by plasma-enhanced chemical vapor deposition (PECVD) as a hard mask;

[0053] Step S4: I-line positive photoresist 4 is spin-coated onto the hard mask layer 3 using an alternating phase-shifting mask (APS). This PSM is designed for the target grating 7 period (e.g., a final period of 200nm), with a mask pattern period twice that of the final period (i.e., 400nm), ensuring a 180-degree phase difference between adjacent transparent areas. Exposure is performed using an I-line stepper lithography machine. Due to the phase-shifting effect, the edge contrast of the line pattern imaged on the photoresist 4 is significantly improved. After exposure, development is performed.

[0054] Step S5: The photoresist 4 pattern is transferred to the underlying silicon nitride hard mask layer by reactive ion etching (RIE) to form a striped initial periodic pattern 5 (period 600nm, linewidth approximately 300nm).

[0055] Step S6: Remove the photoresist 4 and deposit a silicon dioxide (SiO2) filling layer 6 on the surface of the initial periodic pattern 5 using atomic layer deposition. The thickness of the filling layer 6 is precisely controlled to 75 nm.

[0056] Step S7: Use CHF3 or other gases to anisotropically etch the filling layer 6, vertically etching downwards to remove the silicon dioxide filling layer 6 in the gap between the top and bottom of the initial periodic pattern 5, leaving only the sidewalls of the silicon dioxide filling layer 6 on the sidewalls of the initial periodic pattern 5.

[0057] Step S8: Use hot phosphoric acid solution to selectively remove the initial periodic pattern 5, so that the filling layer 6 material remains independently. At this time, only a row of independent silica sidewall lines with a period of 300nm (half of the initial period of 600nm) remains.

[0058] Step S9: Using the remaining sidewalls of the silicon dioxide filling layer 6 as an etching mask, chlorine-based / boron-based inductively coupled plasma (ICP) etching is performed on the surface of the epitaxial structure of the wafer to form a striped surface grating 7 structure with a depth of about 100 nm.

[0059] Step S10: Use buffered hydrofluoric acid solution to remove all silicon dioxide sidewalls to form a wafer with a surface grating 7 structure;

[0060] Step S11 involves fabricating light-emitting holes and electrodes, cleaving, and encapsulating the wafer with the surface grating 7 structure.

[0061] The collaborative design principle of this embodiment is: during the layout design stage, the line direction of the initial pattern (i.e. the stripe direction of the final grating 7) is made perpendicular to the oblique cutting direction of the substrate 1

[011] . Therefore, the geometric polarization selection axis of the grating 7 is orthogonal to the material gain advantage axis. By optimizing the depth and duty cycle of the grating 7, the grating 7 effect is made dominant, and the output polarization is stably locked in the direction perpendicular to

[011] .

Claims

1. A method for fabricating a single-mode, single-biased VCSEL chip, characterized in that, Includes the following steps: Step S1: Prepare a compound semiconductor substrate with a beveled angle; Step S2: An epitaxial structure is grown on the substrate surface to form a wafer with an epitaxial structure; Step S3: Deposit a hard mask layer on the surface of the wafer; Step S4: Photoresist is coated on the hard mask layer, and an I-line stepper lithography machine equipped with a phase-shifting mask is used for exposure and development to form a photoresist pattern. Step S5: Etch and transfer the photoresist pattern to the hard mask layer to form a striped initial periodic pattern; Step S6: Remove the photoresist and deposit a fill layer on the structural surface of the initial periodic pattern; Step S7: Perform anisotropic etching on the filling layer to remove the filling layer in the gaps at the top and bottom of the initial periodic pattern, leaving only the filling layer material on the sidewalls of the initial periodic pattern. Step S8: Selectively remove the initial periodic pattern so that the filling layer material is retained independently; Step S9: Using the remaining filler material as an etching mask, the epitaxial structure surface of the wafer is etched to form a striped surface grating structure. Step S10: Remove all the filler layer material to form a wafer with a surface grating structure; Step S11: The wafer with the surface grating structure is processed to prepare light-emitting holes, electrodes, etc.

2. The method for fabricating a single-mode, single-biased VCSEL chip according to claim 1, characterized in that, The oblique angle of the substrate is 2°-10°, and the stripe direction of the surface grating structure is horizontal or perpendicular to the oblique direction of the substrate.

3. The method for fabricating a single-mode, single-biased VCSEL chip according to claim 1, characterized in that, The phase shift mask mentioned in step S4 is an alternating phase shift mask or an attenuation phase shift mask.

4. The method for fabricating a single-mode, single-biased VCSEL chip according to claim 1, characterized in that, In step S6, the deposition method of the filling layer is atomic layer deposition, plasma-enhanced chemical vapor deposition, or inductively coupled plasma chemical vapor deposition.

5. The method for fabricating a single-mode, single-biased VCSEL chip according to claim 4, characterized in that, The filling layer is made of silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide, or aluminum nitride.

6. A single-mode, single-biased VCSEL chip, characterized in that, It is prepared by any one of the methods described in claims 1-5.

Images