A radio frequency receiver chip

Abstract

This invention discloses an RF receiver chip, including a low-noise image rejection amplifier (LNA). The signal output terminal of the LNA is connected to an active balun, the signal output terminal of the active balun is connected to a mixer, the signal output terminal of the filter is connected to a variable gain amplifier (VGA), the signal output terminal of the VGA is connected to a bandpass sampling analog-to-digital converter (ADC), and the signal output terminal of the ADC is connected to a frequency synthesizer. By introducing the LNA and the ADC, the chip achieves full real-domain processing of the receiver link. The operating frequency of the frequency synthesizer is the same as the local oscillator frequency, and the chip operates in the real domain. This eliminates the need for an external SAW filter and internal I / Q complex domain signal processing, and also eliminates the need for the frequency synthesizer to provide a quadrature local oscillator signal. This reduces the requirements for the frequency synthesizer's oscillation frequency range and complexity.

Description

Technical Field

[0001] This invention belongs to the field of wireless communication technology, and specifically relates to an radio frequency receiver chip. Background Technology

[0002] Currently, typical RF receiver architectures are mainly divided into three types: superheterodyne, low-IF, and zero-IF. While these three architectures are widely used, they all have limitations in terms of system integration, power consumption, and design complexity. Superheterodyne achieves high selectivity and sensitivity through multi-stage frequency conversion, but it typically requires an external image rejection filter to suppress image frequency interference. This not only increases the system cost and size but also limits the possibility of monolithic integration. Secondly, low-IF architecture downconverts the signal to a lower intermediate frequency to avoid DC offset and flicker noise. However, this architecture requires designing a complex complex domain image rejection filter within the chip, and to handle both I / Q signals, two filter channels must be integrated, occupying a large chip area. Thirdly, zero-IF architecture directly downconverts the RF signal to baseband, avoiding image interference and achieving high integration. However, its signal processing is entirely in the complex domain, requiring all key modules such as mixers, filters, variable gain amplifiers, and analog-to-digital converters to be equipped with both I / Q channels. This significantly increases the chip's power consumption and area. Furthermore, since both the low-IF and zero-IF structures operate in the complex domain, a frequency synthesizer is needed to provide orthogonal local oscillator signals. In practical engineering, a frequency divider is typically used to generate orthogonal components from a twice-harmonic local oscillator signal. This means the frequency synthesizer's oscillation frequency needs to be set to twice the local oscillator signal frequency, greatly increasing the design complexity and power consumption of the frequency synthesizer. Therefore, we propose an RF receiver chip. Summary of the Invention

[0003] This invention provides an radio frequency receiver chip to solve the problems mentioned in the background art.

[0004] The present invention provides the following technical solution: an RF receiver chip, including a mirror rejection low noise amplifier, wherein the signal output terminal of the mirror rejection low noise amplifier is connected to an active balun, and the signal output terminal of the active balun is connected to a mixer; The mixer is used to down-convert the differential signal input from the active balun and send it to the next stage filter. The signal output terminal of the filter is connected to a variable gain amplifier, the signal output terminal of the variable gain amplifier is connected to a bandpass sampling analog-to-digital converter, and the signal output terminal of the bandpass sampling analog-to-digital converter is connected to the frequency synthesizer. The filter is used to filter out the high-frequency signal after down-conversion, and after filtering, the gain of the receiving link is compensated by the variable gain amplifier. Then, the bandpass sampling analog-to-digital converter performs frequency conversion processing so that the intermediate frequency signal output by the mixer is higher than that of the low intermediate frequency or zero intermediate frequency architecture, which is used to improve the suppression capability of the image rejection low noise amplifier.

[0005] A further improvement of the present invention is that the image suppression low noise amplifier includes a first-stage matching circuit and a second-stage suppression circuit. The first-stage circuit is used to match the single-ended impedance of the received signal, and the second-stage circuit is used to filter out the noise superposition of the mixer in the real domain and perform image suppression.

[0006] A further improvement of the present invention is that the first-stage matching circuit is provided with a low-noise amplifier with a single-ended source, which saves the external balun by matching the single-ended impedance of the received signal.

[0007] A further improvement of the present invention is that the secondary suppression circuit is provided with a common-source amplifier and a common-gate amplifier, which are used to implement the in-chip balun function.

[0008] A further improvement of the present invention is that it includes a mirror-suppression low-noise amplifier, an active balun, a mixer A, a passive multinomial network A, a passive multinomial network B, a complex domain mixer BI, a complex domain mixer BQ, a filter, a variable gain amplifier, a bandpass sampling analog-to-digital converter, and a frequency synthesizer. The mixer A converts the differential signal output by the active balun into an orthogonal signal through a passive multiphase network A and performs image noise suppression. Then, the orthogonal signal is mixed by the second-stage complex domain mixer BI and complex domain mixer BQ to output a real domain signal without image interference.

[0009] Compared with the prior art, the beneficial effects of the present invention are: by introducing a mirror rejection low-noise amplifier and a bandpass sampling analog-to-digital converter, the chip receiving link achieves full real-domain processing. The operating frequency of the frequency synthesizer is the same as the local oscillator signal frequency, and the chip operates in the real domain. There is no need for an external SAW filter and internal I / Q complex domain signal processing, nor is there a need for the frequency synthesizer to provide a quadrature local oscillator signal. The requirements for the oscillation frequency range and complexity of the frequency synthesizer are lower, and it has the advantages of small area and low power consumption. Attached Figure Description

[0010] Fig. 1 This is a structural diagram of an RF receiver chip according to the present invention; Fig. 2 This is a circuit diagram of the image suppression low-noise amplifier in this invention; Fig. 3This is a structural diagram of a radio frequency receiver chip capable of two-stage frequency conversion according to the present invention. Detailed Implementation

[0011] The present invention will be further described below with reference to specific embodiments. The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the present invention. In order to better illustrate the specific embodiments of the present invention, some parts in the drawings may be omitted, enlarged or reduced, and do not represent the actual product size. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings. Based on the specific embodiments of the present invention, all other specific embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0012] Example 1 To address the limitations of existing superheterodyne, low-IF, and zero-IF architectures, which, while widely used, suffer from limitations in system integration, power consumption, and design complexity, please refer to [link to relevant documentation]. Figs. 1-3 This invention proposes an RF receiver chip that operates in the real domain, eliminating the need for an external SAW filter and internal I / Q complex domain signal processing. It also eliminates the need for a frequency synthesizer to provide quadrature local oscillator signals, thus reducing the requirements for the frequency synthesizer's oscillation frequency range. The chip features simple design, low complexity, small area, and low power consumption. It includes a low-noise image suppression amplifier (LNA), whose signal output is connected to an active balun, and whose signal output is connected to a mixer. The mixer is used to down-convert the differential signal input from the active balun and send it to the next stage filter.

[0013] In this embodiment, the image rejection low-noise amplifier, in addition to providing pre-amplification gain and a low noise figure, also provides image rejection. Image rejection is mainly used to filter out the noise superposition phenomenon introduced by the subsequent mixer in the real domain, thereby improving the overall noise performance of the receiver. This image rejection filter adopts a single-ended input and single-ended output structure, thus saving the use of external balun devices and reducing chip usage costs.

[0014] The active balun converts the single-ended output of the pre-amplifier image rejection low-noise amplifier (ARPA) to a differential output, which is then sent to the mixer. The mixer down-converts the input differential signal and sends it to the next-stage filter module. Since the down-conversion is performed in the real domain, a quadrature local oscillator signal is not required from the frequency synthesizer, significantly reducing the frequency range requirements of the frequency synthesizer. Because the ARPA already suppresses image noise during the mixing process, mixing in the real domain will not affect the system-level noise performance.

[0015] The signal output of the filter is connected to a variable gain amplifier, the signal output of the variable gain amplifier is connected to a bandpass sampling analog-to-digital converter, and the signal output of the bandpass sampling analog-to-digital converter is connected to a frequency synthesizer.

[0016] In this embodiment, the filter is mainly used to filter out the high-frequency signal after down-conversion. Since the filter operates in the real domain, compared with the filter in the low-intermediate frequency architecture, there is no need to design a complex complex domain bandpass filter scheme to suppress the image signal. Therefore, the design complexity, area and power consumption are greatly reduced.

[0017] The filter is used to filter out the high-frequency signal after down-conversion, and after filtering, the gain of the receiving link is compensated by a variable gain amplifier. Then, the frequency is converted by a bandpass sampling analog-to-digital converter so that the intermediate frequency signal output by the mixer is higher than that of the low intermediate frequency or zero intermediate frequency architecture, which is used to improve the suppression capability of the image rejection low noise amplifier.

[0018] In this embodiment, since the sampling frequency of the bandpass sampling analog-to-digital converter is lower than the input signal frequency and it has a frequency conversion function, it can ensure that the output intermediate frequency signal frequency of the mixer is much higher than that of the low intermediate frequency or zero intermediate frequency architecture. This is beneficial to improving the image rejection capability of the image rejection low noise amplifier and improving the overall noise performance of the receiver.

[0019] In this embodiment, the image suppression low-noise amplifier includes a first-stage matching circuit and a second-stage suppression circuit. The first-stage circuit is used to match the single-ended impedance of the received signal, and the second-stage circuit is used to filter out the noise superposition of the mixer in the real domain and perform image suppression.

[0020] In this embodiment, a low-noise amplifier with a single-ended source is provided in the first-stage matching circuit to save the external balun by matching the single-ended impedance of the received signal; the first-stage matching circuit is used to provide single-ended impedance matching function and a low noise figure.

[0021] In this embodiment, the secondary suppression circuit includes a common-source amplifier and a common-gate amplifier, which are used to implement the on-chip balun function. In the secondary suppression circuit, the inductor Lim and capacitor Cim are connected in series at the load node, providing a zero point and forming a band-stop depression. If the zero-point frequency is equal to the image frequency, image suppression is achieved. The cross transistor pair M7 and M8 provides a negative resistance value to offset the parasitic resistance of inductor Lim, improving the quality factor at the series resonance of inductors Lim and Cim, and enhancing image suppression capability.

[0022] The working principle of this invention is as follows: by introducing a low-noise image suppression amplifier and a bandpass sampling analog-to-digital converter, the chip's receiving link can achieve full real-domain processing. The operating frequency of the frequency synthesizer is the same as the local oscillator signal frequency, and the chip operates in the real domain. There is no need for an external SAW filter and internal I / Q complex domain signal processing, nor is there a need for the frequency synthesizer to provide a quadrature local oscillator signal. This reduces the requirements for the oscillation frequency range and complexity of the frequency synthesizer, and also has the advantages of small area and low power consumption.

[0023] Example 2 In this embodiment, a radio frequency receiver chip capable of two-stage frequency conversion is proposed. The similarities to Embodiment 1 will not be repeated here, but the differences from Embodiment 1 are as follows: The two-stage frequency conversion RF receiver chip includes a mirror rejection low-noise amplifier, an active balun, mixer A, passive multinomial network A, passive multinomial network B, complex domain mixer BI, complex domain mixer BQ, a filter, a variable gain amplifier, a bandpass sampling analog-to-digital converter, and a frequency synthesizer.

[0024] In this embodiment, during operation, mixer A converts the differential signal output from the active balun into a quadrature signal through a passive multiphase network A and performs image noise suppression. Then, the quadrature signal is mixed by the second-stage complex domain mixer BI and complex domain mixer BQ to output a real domain signal without image interference.

[0025] In this embodiment, it should be noted that if the frequency range of the frequency synthesizer in Embodiment 1 still cannot meet the actual design requirements, this embodiment proposes a radio frequency receiver chip capable of two-stage frequency conversion. During operation, mixer A converts the differential signal into an orthogonal signal through a passive polyphase network A and performs image noise suppression. Then, it is mixed with the second-stage complex domain mixer BI and the number domain mixer BQ, respectively, outputting a real-number domain signal without image interference. This signal is processed by a real-number domain filter, a variable frequency synthesizer, and an analog-to-digital converter before being sent to the subsequent baseband module for demodulation. The passive polyphase network B and passive polyphase network A serve the same purpose: converting the output differential signal of the frequency synthesizer into an orthogonal signal.

[0026] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of this invention is defined by the appended claims and their equivalents.

Claims

1. A radio frequency receiver chip, characterized in that: The system includes a mirror-suppressed low-noise amplifier, the signal output of which is connected to the active balun, and the signal output of which is connected to a mixer. The mixer is used to down-convert the differential signal input from the active balun and send it to the next stage filter. The signal output terminal of the filter is connected to a variable gain amplifier, the signal output terminal of the variable gain amplifier is connected to a bandpass sampling analog-to-digital converter, and the signal output terminal of the bandpass sampling analog-to-digital converter is connected to the frequency synthesizer. The filter is used to filter out the high-frequency signal after down-conversion, and after filtering, the gain of the receiving link is compensated by the variable gain amplifier. Then, the bandpass sampling analog-to-digital converter performs frequency conversion processing so that the intermediate frequency signal output by the mixer is higher than that of the low intermediate frequency or zero intermediate frequency architecture, which is used to improve the suppression capability of the image rejection low noise amplifier.

2. The radio frequency receiver chip according to claim 1, characterized in that: The image suppression low-noise amplifier includes a first-stage matching circuit and a second-stage suppression circuit. The first-stage circuit is used to match the single-ended impedance of the received signal, and the second-stage circuit is used to filter out the noise superposition during mixing in the real domain by the mixer and to perform image suppression.

3. The radio frequency receiver chip according to claim 1, characterized in that: The primary matching circuit is equipped with a low-noise amplifier with a single-ended source, which saves the external balun by matching the single-ended impedance of the received signal.

4. The radio frequency receiver chip according to claim 1, characterized in that: The secondary suppression circuit includes a common-source amplifier and a common-gate amplifier, which are used to implement the in-chip balun function.

5. A radio frequency receiver chip capable of two-stage frequency conversion, characterized in that: This includes a mirror-suppressed low-noise amplifier, an active balun, mixer A, passive multinomial network A, passive multinomial network B, complex domain mixer BI, complex domain mixer BQ, filters, variable gain amplifiers, bandpass sampling analog-to-digital converters, and frequency synthesizers. The mixer A converts the differential signal output by the active balun into an orthogonal signal through a passive multiphase network A and performs image noise suppression. Then, the orthogonal signal is mixed by the second-stage complex domain mixer BI and complex domain mixer BQ to output a real domain signal without image interference.

Images