A method for realizing packet cache sorting and extraction based on FPGA

Abstract

The application provides a method for packet cache sorting and extraction based on FPGA, aiming to improve the data packet processing efficiency in high-speed network environment. The method utilizes the parallel processing advantage of FPGA and realizes the reception, preprocessing, classification, cache allocation, sorting and extraction of data packets through a series of logical steps. The core algorithm adopts a score comparison mechanism to calculate the score of each data packet and quickly locate the position of the sorted data packet through cumulative score to achieve efficient extraction. In addition, the application also includes a resource dynamic allocation strategy, which dynamically adjusts resource allocation according to real-time traffic, and a forwarding resource recycling logic to ensure timely recycling and reuse of resources. This technical solution is suitable for network communication systems that require high-speed data processing and forwarding, not only improving the speed and accuracy of data packet processing, but also optimizing the allocation and utilization of FPGA internal resources, reducing system delay, and enhancing the real-time performance and stability of network communication.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, and more specifically to a method for message buffering, sorting, and extraction based on FPGA. Background Technology

[0002] In the field of modern electronic engineering, especially against the backdrop of the rapid development of network communication technology, FPGAs (Field-Programmable Gate Arrays) are playing an increasingly important role in high-speed data transmission and processing. With the widespread application of 100G high-speed interface technology, network equipment upgrades face new challenges and opportunities. In these application scenarios, FPGAs not only need to process large amounts of data, but also ensure high efficiency and accuracy in data transmission, which places higher demands on the allocation of internal resources and routing within the FPGA.

[0003] Traditionally, CPUs are used to process network packets, including operations such as receiving, table lookup, fragmentation, and encapsulation. However, with the surge in data volume, CPU packet processing faces problems such as difficulty in controlling interrupt sources, high resource consumption, and low efficiency. Therefore, FPGAs, due to their parallel processing capabilities and low latency, have become the preferred solution for processing network packets. FPGAs can complete the reception, processing, and forwarding of data packets. In each processing stage, packets are buffered and parsed simultaneously. After parsing, the buffered data is retrieved and processed accordingly.

[0004] However, FPGAs also face internal routing limitations and resource allocation issues when processing high-speed data. In packet-switched architectures with mismatched port rates, the FPGA's internal data buffer uses Block RAM to handle large data traffic, requiring many Block RAM blocks to be combined. Simultaneously, forwarding data at 100G line speed to multiple ports necessitates data switching across all data buffers, resulting in complex, localized use of significant routing resources internally. The contradiction between the large number of data bandwidth and buffer modules and the even distribution of internal resources is a challenge faced by FPGA 100G ports in such applications.

[0005] Furthermore, FPGAs face challenges in high-speed data transmission, particularly regarding data width and clock synchronization. Data width limitations limit the bandwidth of data during transmission, while clock synchronization ensures accurate time coordination for data transfer between different devices. There are two main synchronization methods for data transmission between FPGAs: system synchronization and source synchronization. System synchronization relies on a unified clock signal to coordinate data exchange between multiple FPGAs, while source synchronization uses independent clock sources and specific synchronizers to ensure accurate data transmission between different FPGAs.

[0006] In summary, while FPGAs offer significant advantages in high-speed data transmission and message processing, they also present numerous technical challenges, including efficient allocation of internal resources, complex routing issues, and data width and clock synchronization problems. These challenges have spurred the industry to continuously explore and develop new FPGA application technologies to meet the ever-increasing demand for high-speed data processing. Summary of the Invention

[0007] Therefore, to address the aforementioned problems, this invention provides a method for message buffer sorting and retrieval based on FPGA. This method optimizes FPGA performance in high-speed data transmission through sophisticated logic design. With the development of technologies such as cloud computing, big data, and 5G, the demands for data processing speed and efficiency are increasing. FPGA, due to its parallel processing and low latency characteristics, has become a key technology for achieving efficient message buffer sorting and retrieval. The core of this invention's logic design lies in efficiently processing and sorting messages, and quickly and accurately retrieving messages from the buffer. This invention includes the following key logic modules: a message receiving module, a buffer allocation module, a message sorting module, a message retrieval module, and a resource scheduling and reclamation module.

[0008] The following is a specific implementation method of the present invention: Message Receiving Module: This module receives messages from the network interface and stores them in the FPGA's Block RAM. Its logic is designed to parse the Ethernet frame structure, extract the frame header information, and perform preliminary message classification based on the header information. The classified messages are then sent to the buffer allocation module for further processing.

[0009] Cache allocation module: This module is responsible for packet storage and cache management. It employs a multi-level cache structure, with each level having independent control logic to handle packets of different priorities or types. The logic design of the cache allocation module includes a cache allocation algorithm that dynamically allocates cache space based on packet size and priority, ensuring fast access to critical packets.

[0010] Message Sorting Module: This module is responsible for sorting the messages in the cache. It uses a comparison-based sorting method for fast sorting. The sorting logic is designed considering the arrival order and priority of the messages, ensuring that they are processed in the predetermined order. The sorting results are stored in the cache allocation module for use by the message retrieval module.

[0011] Message Extraction Module: This module is responsible for retrieving sorted messages from the cache list. Its logical design includes a fast lookup algorithm, employing a combination of binary search and hash tables to achieve rapid message location. The module also contains data path control logic to manage message transmission from the cache to the output port.

[0012] Resource Scheduling and Reclamation Module: This module is responsible for dynamically adjusting the use of internal FPGA resources. Its logic design includes a resource allocation algorithm that dynamically adjusts the allocation of logic, storage, and I / O resources based on real-time traffic and packet processing requirements. The resource scheduling and reclamation module ensures efficient resource utilization and avoids resource conflicts and deadlocks.

[0013] In its specific implementation, the present invention employs the following technical means: 1) Pipeline technology: Pipeline technology breaks down the message processing process into multiple stages, with each stage being processed in parallel, which greatly improves the processing speed.

[0014] 2) Asynchronous reset and synchronous release: In order to ensure the stability of the system, the present invention adopts an asynchronous reset and synchronous release strategy in the logic design to avoid the impact of the reset signal on data processing.

[0015] 3) Clock Domain Crossing (CDC): When processing signals between different clock domains, this invention uses CDC technology to ensure the correct transmission of signals between different clock domains.

[0016] 4) Dynamic Partial Reconfiguration (DPR): In order to improve resource utilization, this invention adopts DPR technology in the logic design, which allows parts of the FPGA to be reconfigured at runtime.

[0017] Through the implementation method of the above logic design, the present invention not only improves the data processing efficiency of FPGA in high-speed data transmission, reduces the message processing delay, optimizes the allocation of internal resources of FPGA, simplifies the internal wiring of FPGA, and improves the stability and reliability of the system, but also has important practical application value.

[0018] The beneficial effects of this invention are as follows: 1. Improved data processing efficiency: This invention significantly improves data processing speed and reduces latency by optimizing the internal resource allocation and routing design of the FPGA, enabling the FPGA to process a large number of packets in high-speed networks more efficiently.

[0019] 2. Enhanced system stability: By adopting advanced logic design and redundancy technology, this invention enhances the system's fault tolerance, reduces system crashes caused by resource conflicts and deadlocks, and ensures long-term stable operation.

[0020] 3. Improve resource utilization: Dynamic resource scheduling strategies enable FPGA resources to be allocated and utilized more rationally, reducing resource waste and improving the overall system's energy efficiency and performance. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is an overall architecture diagram of the message extraction module of the present invention, which is a method for message buffering, sorting and extraction based on FPGA.

[0023] Figure 2 This is a logic diagram of the score comparison sorting algorithm of the method for message buffer sorting and retrieval based on FPGA of the present invention. Detailed Implementation

[0024] The technical solution of the invention will be described in detail below with reference to the accompanying drawings: Figure 1 The entire process, from receiving packets at the network interface to their complete processing and extraction, is described in detail, including key components such as the packet receiving module, preprocessing module, classification module, buffer allocation module, sorting module, and extraction module. The function and data flow of each module are clearly marked, demonstrating the packet flow path and processing logic within the FPGA.

[0025] Message Receiving Module: This module receives messages from the network interface and stores them in the FPGA's Block RAM. Its logic is designed to parse the Ethernet frame structure, extract the frame header information, and perform preliminary message classification based on the header information. The classified messages are then sent to the buffer allocation module for further processing.

[0026] Cache allocation module: This module is responsible for packet storage and cache management. It employs a multi-level cache structure, with each level having independent control logic to handle packets of different priorities or types. The logic design of the cache allocation module includes a cache allocation algorithm that dynamically allocates cache space based on packet size and priority, ensuring fast access to critical packets.

[0027] Message Sorting Module: This module is responsible for sorting the messages in the cache. It uses a comparison-based sorting method for fast sorting. The sorting logic is designed considering the arrival order and priority of the messages, ensuring that they are processed in the predetermined order. The sorting results are stored in the cache allocation module for use by the message retrieval module.

[0028] Message Extraction Module: This module is responsible for retrieving sorted messages from the cache list. Its logical design includes a fast lookup algorithm, employing a combination of binary search and hash tables to achieve rapid message location. The module also contains data path control logic to manage message transmission from the cache to the output port.

[0029] Resource Scheduling and Reclamation Module: This module is responsible for dynamically adjusting the use of internal FPGA resources. Its logic design includes a resource allocation algorithm that dynamically adjusts the allocation of logic, storage, and I / O resources based on real-time traffic and packet processing requirements. The resource scheduling and reclamation module ensures efficient resource utilization and avoids resource conflicts and deadlocks.

[0030] like Figure 2 As shown, the present invention describes the specific logic selection of the score comparison sorting algorithm for a method of message buffer sorting and retrieval based on FPGA.

[0031] In this embodiment, the present invention employs the following technical means: 1) Pipeline technology: Pipeline technology breaks down the message processing process into multiple stages, with each stage being processed in parallel, which greatly improves the processing speed.

[0032] 2) Asynchronous reset and synchronous release: In order to ensure the stability of the system, the present invention adopts an asynchronous reset and synchronous release strategy in the logic design to avoid the impact of the reset signal on data processing.

[0033] 3) Clock Domain Crossing (CDC): When processing signals between different clock domains, this invention uses CDC technology to ensure the correct transmission of signals between different clock domains.

[0034] 4) Dynamic Partial Reconfiguration (DPR): In order to improve resource utilization, this invention adopts DPR technology in the logic design, which allows parts of the FPGA to be reconfigured at runtime.

[0035] The specific steps are as follows: Step 1: System Initialization and Configuration. First, the FPGA loads a pre-designed configuration file via JTAG. This file contains the logic and routing information required to implement this invention. This information defines the connection methods and operating modes of the FPGA's internal logic modules, as well as the communication protocol with the external network interface. Next, the FPGA's internal clock frequency, interface parameters, and cache parameters are set to match the operating conditions of the network devices. This includes configuring the parameters of the high-speed serial interface and the read / write mode of the internal Block RAM. Furthermore, initialization also includes setting the FPGA's internal state machine to ensure that all logic modules start operating from a known state. This step is fundamental to the normal operation of the entire system, ensuring that the FPGA's logic modules can correctly respond to network traffic. Additionally, dynamic partial reconfiguration is supported, facilitating customizable resource allocation.

[0036] Step Two: Message Reception. This step employs clock domain interleaving technology to ensure the integrity of network data received from the physical layer. This invention designs a network interface monitoring module that can monitor data streams from the network and capture incoming messages when network activity is detected. This step involves synchronizing and decoding physical layer signals, as well as parsing the Ethernet frame structure. The captured messages are then sent to a preprocessing module, which is responsible for removing physical layer overhead and performing error detection. The preprocessing module, considering the characteristics of different network protocols such as Ethernet, IP, and TCP / UDP, pre-sets corresponding parsing algorithms for each type to ensure correct parsing of various message types. Furthermore, this invention includes a state machine to control the message reception process, including frame synchronization, data verification, and frame end detection.

[0037] Step 3: Message Classification and Buffer Allocation. In this step, the invention implements frame header parsing and message classification. Frame header parsing extracts key message information, such as type, source address, destination address, and priority. This information is typically contained in the Ethernet frame, IP header, and transport layer protocol header. Based on this information, the message classification module assigns messages to different processing priorities. Subsequently, the buffer allocation module dynamically allocates BlockRAM resources within the FPGA as buffer space according to the message priority and size to adapt to different traffic patterns and message sizes. The buffer allocation logic also implements buffer space fragmentation management to avoid performance degradation caused by frequent memory allocation and deallocation.

[0038] Step Four: Cache Management. The cache management logic module is the core step of this invention, responsible for message storage and cache management. This step includes a multi-level cache structure, with each level having independent control logic to handle messages of different priorities or types. The cache allocation module monitors cache usage to ensure efficient use of cache space and prevent overflow. This invention uses the MESI cache consistency protocol and the Least Recently Used (LRU) algorithm for cache line replacement to achieve cache synchronization, ensuring data consistency across the multi-level cache structure. The cache management logic also handles cache read / write conflicts, ensuring data integrity and consistency.

[0039] Step 5: Message Sorting. The message sorting module is responsible for sorting the messages in the cache. This invention uses a hardware score comparison sorting algorithm to achieve fast sorting. The score comparison sorting algorithm first calculates a score for each data: if the data is greater than all other data, the score is 0, and merge sort is used; if the data is equal to other data and is at the beginning of the sequence, the score is 0, otherwise it is 1, and insertion sort is used; if the data is less than other data, the score is 1, and fast sort is used. Next, in the second clock cycle, the scores of each data are accumulated to form a score array. In the third clock cycle, the data is assigned to the new array according to the score, with data with a score of 1 assigned to the first position, data with a score of 2 assigned to the second position, and so on. Finally, in the fourth clock cycle, the sorted new array is output for fast message retrieval. This algorithm utilizes the parallel processing capability of the FPGA, allowing the comparison and score calculation of multiple data to be performed simultaneously, thereby improving processing speed, reducing the required clock cycles, and providing flexibility to adapt to different message sizes and quantities, ensuring that high-priority messages can be retrieved quickly. The sorting results are stored in the cache allocation module for later retrieval. The sorting logic is designed to consider both the arrival order and priority of messages, ensuring that messages are processed in the predetermined order. Furthermore, the sorting logic also handles out-of-order arrival and loss of messages, ensuring that the system can correctly recover the message sequence.

[0040] Step Six: Message Extraction. This step employs a pipelined processing technique. By finely controlling the information frame format, it quickly extracts key message information, such as length, 5-tuple, and matching strategy. A FIFO mechanism is used for caching, optimizing timing and reducing resource consumption. This module determines the message processing path through table lookups and matching strategies. Simultaneously, during pipelined operations, it recalculates and caches checksums and flag information to improve performance. This design not only enhances the efficiency and accuracy of message processing but also achieves line-speed processing performance by fully utilizing the FPGA's high-speed I / O resources and parallel processing capabilities, enhancing system reusability. The message extraction module is responsible for retrieving sorted messages from the cache and sending them to the message forwarding module.

[0041] Step Seven: Message Forwarding. The message forwarding logic is responsible for forwarding messages from the buffer unit to the output port. Based on message formatting and protocol requirements, the forwarding logic module includes message encapsulation and decapsulation logic to ensure messages are correctly sent to the external network. This invention pre-defines forwarding rules for different network protocols. Furthermore, the forwarding logic includes flow control and congestion avoidance mechanisms to ensure network stability and efficiency.

[0042] Step 8: Resource Scheduling and Optimization. The resource monitoring and scheduling logic can monitor the usage of internal FPGA resources in real time and dynamically adjust resource allocation based on current traffic and system load. The resource scheduling logic uses a dynamic priority allocation algorithm and multiple resource reclamation and reuse algorithms to address the limited nature of internal FPGA resources. Based on the different resource requirements of different tasks, it improves resource utilization and system response speed.

[0043] Step Nine: Resource Reclamation. This step employs asynchronous reset and synchronous release techniques to promptly reclaim the resources allocated to the packet after successful forwarding, allowing these resources to be reallocated to new packet processing tasks. When a packet enters the forwarding process, the resources allocated to each packet (such as buffer space, bandwidth, etc.) are marked. This includes creating a resource usage record for each packet, recording its resource details. After the packet is successfully sent to the network, an acknowledgment signal is received from the network interface. This acknowledgment signal indicates that the packet has been successfully forwarded and its occupied resources can be released. Upon receiving the forwarding acknowledgment signal, the resource reclamation logic immediately initiates, releasing all resources associated with the packet. This includes clearing packet data from the cache, releasing occupied buffers, and marking bandwidth resources as available. The state of the system resource pools, including the cache resource pool and the processing resource pool, is updated. This step ensures that the global view of system resources is up-to-date, allowing the resource scheduling and reclamation module to accurately understand current resource availability. A resource reclamation strategy is designed to handle lost or corrupted data. The resource reclamation logic can detect anomalies and release resources at appropriate times to prevent resource leaks. To improve the efficiency of resource recycling, a statistical prediction and optimization algorithm is designed to predict the timing of resource release, prepare for resource recycling in advance, and reduce resource idle time.

[0044] Through the above embodiments, the present invention provides a method for high-speed packet buffer sorting and retrieval based on FPGA, covering the entire process from system initialization to packet processing, buffer management, sorting, and forwarding. Through these steps, the present invention can effectively process a large number of packets in high-speed networks while maintaining system stability and reliability. Those skilled in the art can make appropriate adjustments and optimizations to the above steps according to the actual network environment and performance requirements. Various aspects of the invention are described in this disclosure with reference to the accompanying drawings, which illustrate numerous illustrative embodiments. The embodiments of this disclosure are not necessarily defined to include all aspects of the invention. It should be understood that the various concepts and embodiments described above, as well as those described in more detail below, can be implemented in any of many ways, because the concepts and embodiments disclosed in this invention are not limited to any particular implementation. Furthermore, some aspects of the present invention can be used alone or in any suitable combination with other aspects of the present invention.

[0045] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. The present invention provides a method for message buffer sorting and retrieval based on FPGA, characterized in that, The method includes a message receiving module, a buffer allocation module, a message sorting module, a message extraction module, and a resource scheduling and reclamation module. The specific steps are as follows: a message receiving step, used to receive messages in the network data stream; a message classification step, used to parse the message header information and classify the messages according to message type, source address, destination address, and priority; and a buffer allocation step, used to dynamically allocate the Block RAM resources inside the FPGA as buffer space according to the priority and size of the messages. The message sorting step is used to sort the messages in the cache to ensure that high-priority messages can be retrieved quickly; the message retrieval step is used to retrieve the sorted messages from the cache and send them to the message forwarding module.

2. The message sorting according to claim 1, characterized in that, The message sorting steps include: a score calculation step, used to calculate a score for each message and compare it with other messages based on the message size; a score accumulation step, used to accumulate the scores of each message to form a score array; a message assignment step, used to assign the message to the corresponding position in the new array according to the score array; and a new array output step, used to output the sorted new array for rapid message extraction. This algorithm utilizes the parallel processing capabilities of the FPGA, allowing multiple data comparisons and score calculations to be performed simultaneously, thereby improving processing speed, reducing the required clock cycles, and providing flexibility to adapt to different message sizes and quantities.

3. The dynamic resource allocation according to claim 1, characterized in that, This includes a dynamic resource allocation step, which adjusts the resource allocation of each cache unit based on real-time data traffic. This step monitors current traffic and system load to dynamically adjust the allocation of logical, storage, and I / O resources, optimizing system performance and resource utilization. The dynamic resource allocation step ensures efficient resource utilization, avoids resource conflicts and deadlocks, and improves the overall system's energy efficiency and performance.

4. The forwarding resource recycling according to claim 1, characterized in that, This includes a forwarding resource reclamation step, which promptly reclaims the resources allocated to a packet after successful forwarding. This step is responsible for marking and tracking the resources allocated to each packet, releasing these resources after successful packet transmission, updating the system resource pool status, and ensuring that resources can be reallocated to new packet processing tasks. The forwarding resource reclamation step improves resource reuse, reduces resource idle time, and enhances the overall efficiency of the system.

5. The FPGA logic module according to claim 1, used to implement the method according to any one of claims 1 to 4, characterized in that, The FPGA logic design includes: a message receiving logic module for implementing message receiving; a message classification logic module for implementing message classification; a buffer allocation logic module for implementing buffer allocation; a message sorting logic module for implementing message sorting; a message extraction logic module for implementing message extraction; a dynamic resource allocation logic module for implementing dynamic resource allocation; a forwarding resource reclamation logic module for implementing forwarding resource reclamation; and a system monitoring and maintenance logic module for monitoring system indicators. This FPGA logic design, through meticulous division of logic modules, implements each stage of message processing, ensuring high efficiency and accuracy in data processing.

6. The system monitoring and maintenance according to claim 5, characterized in that, This includes a system monitoring and maintenance logic module, used to monitor system performance metrics and detect faults and anomalies. This module is responsible for performance monitoring and fault detection, monitoring system performance metrics such as processing latency, throughput, and error rate, and detecting faults and anomalies such as hardware failures and logical errors. The system monitoring and maintenance logic module ensures system stability and reliability, promptly identifies and responds to system problems, and performs system maintenance operations such as resource reconfiguration and faulty module replacement.

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