Solar cell and method of manufacturing the same
By depositing barrier layers of varying thicknesses and selective emitters on the back side of a P-type silicon substrate, the complex fabrication process and low yield of P-type IBC cells were solved, achieving high cell conversion efficiency and low leakage current.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 扬州阿特斯太阳能电池有限公司
- Filing Date
- 2024-12-20
- Publication Date
- 2026-06-23
Smart Images
Figure CN122269865A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of photovoltaics, and more particularly to a method for preparing a solar cell and the method thereof. Background Technology
[0002] Currently, PERC monocrystalline solar cells based on P-type silicon wafers are the type of photovoltaic cells with the largest market share. However, due to limitations in the technological mechanism, the conversion efficiency of P-type PERC monocrystalline solar cells has encountered a bottleneck.
[0003] IBC monocrystalline solar cells can solve the problem of shading by the front grid lines, and have higher cell conversion efficiency and potential, making them a popular choice for next-generation cell technology in the industry. TOPCon cells have good passivation effects, and their conversion efficiency is significantly improved. Products combining IBC and TOPCon cell technologies have been launched successively.
[0004] However, the existing P-type IBC battery manufacturing process is complex and has a low yield.
[0005] In view of this, it is necessary to provide an improved solar cell and its fabrication method to solve the above-mentioned technical problems. Summary of the Invention
[0006] This invention provides a method for preparing a solar cell and a solar cell, which helps to improve the process flow and increase the yield of the cell.
[0007] To achieve one of the above-mentioned objectives, the present invention adopts the following technical solution:
[0008] A method for fabricating a solar cell includes the following steps: depositing a tunneling layer and an amorphous silicon layer on the back side of a P-type silicon substrate, wherein the back side of the P-type silicon substrate has a first region and a second region; fabricating a barrier layer of a first thickness in the electrode region of the first region and a barrier layer of a second thickness in the non-electrode region of the first region, wherein the first thickness is less than the second thickness; diffusion doping the amorphous silicon layer using an N-type doping source to form an N-type doped crystalline silicon layer and an oxide layer; removing the oxide layer and the N-type doped crystalline silicon layer in the second region; fabricating a first electrode in the electrode region of the first region and a second electrode in the electrode region of the second region.
[0009] In one embodiment, the first thickness is 1 nm to 10 nm, and / or the second thickness is 11 nm to 30 nm.
[0010] In one embodiment, the barrier layer is selected from one or more combinations of alumina, silicon oxide, silicon nitride, and silicon oxynitride.
[0011] In one embodiment, preparing the barrier layer in the first region includes the following steps: preparing a barrier layer of a second thickness on the entire back side of the amorphous silicon layer, and then removing the barrier layer in the second region to reduce the thickness of the barrier layer in the electrode region of the first region to the first thickness.
[0012] In one embodiment, preparing the barrier layer in the first region includes the following steps: preparing a barrier layer of a first thickness throughout the first region, and then continuing to prepare a barrier layer to a second thickness in the non-electrode region of the first region.
[0013] In one embodiment, preparing the barrier layer in the first region includes the following steps: preparing a barrier layer slurry of a first thickness in the electrode region of the first region, preparing a barrier layer slurry of a second thickness in the non-electrode region of the first region, and drying and curing the barrier layer slurry to form the barrier layer. The barrier layer slurry is at least one or a combination of alumina slurry, silicon oxide slurry, silicon nitride slurry, and silicon oxynitride slurry.
[0014] In one embodiment, the preparation of the barrier layer in the first region includes the following steps: using a PECVD process, the introduced gas is silane, ammonia, or nitrous oxide, the deposition pressure is 1200 mTorr to 2200 mTorr, the radio frequency power is 30000 W to 40000 W, and the temperature is 450°C to 550°C, forming a silicon oxynitride layer with a thickness of 11 nm to 30 nm as the barrier layer; in the second region, the entire barrier layer is removed using a laser process, selecting an ultraviolet picosecond laser or a filtered picosecond laser, with a laser power of 45 W to 6 W. The laser power is 5W, the spot diameter is 100μm~150μm, the laser frequency is 200kHz~400kHz, and the scanning speed is 40m / s~80m / s. In the electrode region of the first region, a portion of the blocking layer is removed by laser technology. An ultraviolet picosecond laser or a filtered picosecond laser is selected, with a laser power of 23W~40W, a spot diameter of 100μm~150μm, a laser frequency of 400kHz~600kHz, and a scanning speed of 40m / s~80m / s. The thickness of the remaining blocking layer is 1nm~10nm.
[0015] In one embodiment, forming the barrier layer includes the following steps: preparing a barrier layer of a first thickness throughout the first region, and then preparing a barrier layer of a second thickness in the non-electrode region of the first region, wherein the second thickness is greater than the first thickness.
[0016] In one embodiment, forming the barrier layer includes the following steps: preparing a barrier layer slurry of a second thickness in the non-electrode region of the first region, preparing a barrier layer slurry of a first thickness in the electrode region of the first region, and drying and curing to form the barrier layer, wherein the second thickness is greater than the first thickness, and the barrier layer slurry is at least one or a combination of alumina slurry, silicon oxide slurry, silicon nitride slurry, and silicon oxynitride slurry.
[0017] In one embodiment, the N-type dopant source is a phosphorus source, the phosphorus source is phosphorus oxychloride, and the phosphorus diffusion doping temperature is 850°C to 950°C, and the pressure is 50 mbar to 200 mbar.
[0018] In one embodiment, the doping concentration of the phosphorus-doped silicon layer in the electrode region is 4E20 atoms / cm². 3 ~8E20atoms / cm 3 The doping concentration of the phosphorus-doped silicon layer in the non-electrode region is 8E19 atoms / cm. 3 ~2E20atoms / cm 3 .
[0019] In one embodiment, "removing the oxide layer and N-type doped silicon layer in the second region" includes: removing the oxide layer in the second region by using a laser grooving process; removing the oxide layers coated around the front and side surfaces of the silicon substrate; using a texturing alkaline solution to remove the N-type doped silicon layer in the second region, while simultaneously removing the N-type doped silicon layer coated around the front surface, and forming a textured structure in the second region and on the front surface of the silicon substrate.
[0020] In one embodiment, the silicon substrate has a pyramidal textured surface, with the width of the pyramids ranging from 1 μm to 3 μm and a reflectivity of 7% to 10%.
[0021] In one embodiment, before fabricating the first electrode and the second electrode, the method for fabricating the solar cell further includes the following steps: fabricating a passivation layer on both sides, wherein the passivation layer is an aluminum oxide layer with a thickness of 3 nm to 10 nm; and fabricating an antireflection layer on both sides, wherein the antireflection layer is selected from one or more stacked films of silicon nitride, silicon oxynitride, and silicon oxide, and the thickness of the antireflection layer is 70 nm to 90 nm.
[0022] In one embodiment, the back antireflection layer and the back passivation layer of the electrode region in the second region are removed; metal paste is printed in the electrode regions of the first region and the electrode regions of the second region respectively, and sintered to form the first electrode and the second electrode.
[0023] A solar cell, comprising:
[0024] A P-type silicon substrate has a first region and a second region on its back side, the first region having an electrode region and a non-electrode region;
[0025] The tunneling layer and N-type doped silicon layer are located in the first region. The doping concentration of the N-type doped silicon layer in the electrode region is greater than that in the non-electrode region.
[0026] The first electrode is located in the electrode region of the first region;
[0027] The second electrode is located in the second region.
[0028] In one embodiment, the N-type doped silicon layer is a phosphorus-doped silicon layer, and the doping concentration of the phosphorus-doped silicon layer in the electrode region is 4E20 atoms / cm. 3 ~8E20atoms / cm 3 The doping concentration of the phosphorus-doped silicon layer in the non-electrode region is 8E19 atoms / cm. 3 ~2E20atoms / cm 3 .
[0029] In one embodiment, the reflectivity of the front side of the P-type silicon substrate is 7%-10%, and the reflectivity of the back side is 35%-40%.
[0030] In one embodiment, the solar cell further includes: a front passivation layer and / or a front antireflection layer located on the front side of the silicon substrate; and / or a back passivation layer and / or a back antireflection layer located on the back side; wherein the front passivation layer and / or the back passivation layer are aluminum oxide layers with a thickness of 3 nm to 10 nm; the front antireflection layer and / or the back antireflection layer are selected from one or more stacked films of silicon nitride, silicon oxynitride, and silicon oxide, with a thickness of 70 nm to 90 nm.
[0031] The beneficial effects of this invention are as follows: In the solar cell fabrication method of this invention, a barrier layer of varying thickness is formed in the first region before phosphorus diffusion. The barrier layer in the electrode region is thinner, thus having a weaker effect on preventing phosphorus diffusion inward, resulting in a higher doping concentration of the N-type doped silicon layer in the electrode region. Conversely, the barrier layer in the non-electrode region is thicker, thus having a stronger effect on preventing phosphorus diffusion inward, resulting in a lower doping concentration of the N-type doped silicon layer in the non-electrode region. This allows for the formation of a selective emitter in the first region, improving the metal contact in the electrode region. Furthermore, the barrier layer is resistant to alkaline solutions, protecting the N-type doped silicon layer in the first region during subsequent processes while effectively removing the N-type doped silicon layer in the second region. Attached Figure Description
[0032] Figure 1 This is a flowchart of a method for preparing a solar cell according to one embodiment of the present invention;
[0033] Figure 2 This is a schematic diagram of the first region on the back side of the amorphous silicon layer after the barrier layer has been fabricated according to the present invention;
[0034] Figure 3 This is a flowchart of a method for preparing a solar cell according to one embodiment of the present invention;
[0035] Figure 4 This is a flowchart of a method for preparing a solar cell according to one embodiment of the present invention;
[0036] Figure 5 This is a schematic diagram of the structure of a solar cell according to an embodiment of the present invention;
[0037] Figure 6 This is a schematic diagram of the structure of a solar cell according to another embodiment of the present invention.
[0038] Among them, 1-silicon substrate, 2-tunneling layer, 3-amorphous silicon layer, 4-barrier layer, 5-N-type doped crystalline silicon layer, 6-first electrode, 7-second electrode, 8-passivation layer, and 9-antireflection layer. Detailed Implementation
[0039] The present invention will now be described in detail with reference to the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional modifications made by those skilled in the art based on these embodiments are included within the scope of protection of the present invention.
[0040] In the various figures of this invention, for ease of illustration, some dimensions of structures or parts may be exaggerated relative to other structures or parts; therefore, only the basic structure of the subject matter of this invention is used to illustrate the invention.
[0041] For ease of description, taking silicon substrate 1 as a reference, the light-receiving surface (main light-receiving surface) of silicon substrate 1 is defined as the front side, and the back side (secondary light-receiving surface) of silicon substrate 1 is defined as the back side. Film layers located on the front side of silicon substrate 1 are collectively referred to as front-side films. The surface of the front-side film layer that faces away from or away from silicon substrate 1 is the front side, and the surface of the front-side film layer that faces silicon substrate 1 is the back side. Film layers located on the back side of silicon substrate 1 are collectively referred to as back-side films. The surface of the back-side film layer that faces silicon substrate 1 is the front side, and the surface of the back-side film layer that faces away from or away from silicon substrate 1 is the back side.
[0042] like Figures 1-4 As shown, this invention proposes a method for fabricating solar cells using a P-type silicon wafer as the silicon substrate.
[0043] The back side of the silicon substrate 1 has a first region and a second region disposed adjacent to each other, and both the first region and the second region have an electrode region in contact with a metal electrode and a non-electrode region not in contact with a metal electrode. The method for fabricating a solar cell includes the following steps:
[0044] S1 deposits a tunneling layer 2 and an amorphous silicon layer 3 on the back side of the silicon substrate 1;
[0045] S2 prepares a barrier layer 4 in the first region on the back side of the amorphous silicon layer 3; specifically, a barrier layer 4 of a first thickness is prepared in the electrode region of the first region, and a barrier layer 4 of a second thickness is prepared in the non-electrode region of the first region, wherein the first thickness is less than the second thickness.
[0046] S3 uses an N-type doping source to diffuse and dope the amorphous silicon layer 3 to form an N-type doped crystalline silicon layer 5 (N-poly layer) and an oxide layer;
[0047] S4 removes the oxide layer and N-type doped silicon layer 5 in the second region;
[0048] S5 prepares a first electrode 6 in the electrode region of the first region and a second electrode 7 in the electrode region of the second region.
[0049] It should be noted that the width of the electrode region can be the same as the width of the electrode. In the first region, the electrode region has the same width as the first electrode 6, and in the second region, the electrode region has the same width as the second electrode 7. Alternatively, the electrode region can be wider than the electrode. In the first region, the electrode region is wider than the first electrode 6, and in the second region, the electrode region is wider than the second electrode 7. This ensures that the electrode falls within the electrode region even if there are errors or inaccuracies in electrode fabrication.
[0050] The silicon substrate 11 is a P-type single-crystal silicon wafer. The silicon wafer undergoes pretreatment before use.
[0051] In one embodiment, the pretreatment includes: firstly, removing the damaged layer on the surface of the silicon substrate 1 using a mixed solution of potassium hydroxide (KOH) and hydrogen peroxide (H2O2). Then, polishing is performed on the silicon wafer using a polishing alkali solution to form a base on the wafer surface. The base is approximately 15 μm in size and has a reflectivity of approximately 40%. The polishing alkali solution is a sodium hydroxide solution or a potassium hydroxide solution mixed with polishing additives.
[0052] In step S1, the tunneling layer 2 and the amorphous silicon layer 3 can be prepared using processes relevant to the art.
[0053] In one embodiment, the tunneling layer 2 is formed using LPCVD or PECVD processes. The tunneling layer 2 is a silicon oxide layer or a silicon carbide layer, with a thickness of 1 nm to 3 nm, preferably 1 nm to 2.5 nm, and more preferably 1.5 nm to 2 nm.
[0054] The amorphous silicon layer 3 is formed using LPCVD and PECVD processes. The thickness of the amorphous silicon layer 3 is 100 nm to 150 nm.
[0055] Step S2 involves forming a barrier layer 4 in the first region before phosphorus diffusion. This layer allows phosphorus to diffuse inward but also hinders its diffusion, preventing N-type dopant from diffusing into the silicon substrate 1. Furthermore, compared to using laser grooving and alkaline etching to remove the N-poly layer in the second region, this invention utilizes the PSG layer generated by phosphorus diffusion to block alkaline polishing from etching the first region. By setting the barrier layer 4, the invention provides corrosion resistance to alkaline solutions, protecting the N-poly layer in the first region during subsequent processes while completely removing the N-poly layer in the second region; thus eliminating the risk of over-polishing.
[0056] The barrier layer 4 is selected from one or more combinations of aluminum oxide, silicon oxide, silicon nitride, and silicon oxynitride.
[0057] In this invention, such as Figure 2 As shown, the first thickness is less than the second thickness, meaning the thickness of the barrier layer 4 located in the electrode region of the first region is less than the thickness of the barrier layer 4 located in the non-electrode region of the first region. The barrier layers 4 of different thicknesses have different blocking effects on the inward diffusion of phosphorus, forming a selective emitter in the electrode region and the non-electrode region, improving the metal contact in the electrode region, and increasing battery efficiency.
[0058] Further research by the inventors revealed that the thickness of the barrier layer 4 significantly impacts its performance. If the barrier layer 4 is too thin, it cannot effectively prevent the alkaline etching solution from corroding the internal N-poly layer during the de-plating cleaning and removal of the N-poly layer in the second region. If the barrier layer 4 is too thick, it will exacerbate the barrier effect on phosphorus diffusion, affecting ohmic contact.
[0059] In one embodiment, the first thickness is 1 nm to 10 nm, and / or the second thickness is 11 nm to 30 nm.
[0060] Forming barrier layers of varying thicknesses 4 can be achieved through several methods, including but not limited to the following.
[0061] In one embodiment, forming the barrier layer 4 of different thicknesses includes the following steps: first, a barrier layer 4 of a second thickness is prepared on the entire back side of the amorphous silicon layer 3, then the barrier layer 4 of the second region is removed, and the thickness of the barrier layer 4 of the electrode region in the first region is reduced to the first thickness.
[0062] First, a second-thickness barrier layer 4 is deposited using processes such as PECVD. Then, the barrier layer 4 in the second region is removed and the thickness of the barrier layer 4 in the electrode region is reduced by processes such as laser etching.
[0063] In one specific embodiment, a barrier layer 4 is deposited using a PECVD process. The deposition pressure is 1200 mTorr to 2200 mTorr, the RF power is 30000 W to 40000 W, the temperature is 450°C to 550°C, and the introduced gas is silane, ammonia, or nitrous oxide. A silicon oxynitride layer with a thickness of 11 nm to 30 nm is deposited as the barrier layer 4.
[0064] In the second region, all the blocking layer 4 is removed by laser process. Ultraviolet picosecond laser or filter picosecond laser is selected. The laser power is 45W to 65W, the spot diameter is 100μm to 150μm, the laser frequency is 200kHz to 400kHz, and the scanning speed is 40m / s to 80m / s. After laser etching, there is no barrier layer 4 residue in the second region.
[0065] In the electrode region of the first region, a portion of the blocking layer 4 is removed using a laser process. An ultraviolet picosecond laser or a filtered picosecond laser is selected, with a laser power of 23W to 40W, a spot diameter of 100μm to 150μm, a laser frequency of 400kHz to 600kHz, and a scanning speed of 40m / s to 80m / s. After laser etching, the thickness of the remaining blocking layer 4 is 1nm to 10nm.
[0066] In another embodiment, forming the barrier layer 4 includes the following steps: preparing a barrier layer 4 of a first thickness throughout the first region, and then continuing to prepare the barrier layer 4 to a second thickness in the non-electrode region of the first region.
[0067] In one specific embodiment, the second region is blocked by a first mask. A barrier layer 4 with a thickness of 1 nm to 10 nm is first prepared in the entire first region using a PECVD process. Then, the electrode region and the second region of the first region are blocked by a second mask, and deposition continues only in the non-electrode region of the first region, so that the thickness of the barrier layer 4 reaches 11 nm to 30 nm. The PECVD process is the same as in the above embodiment and will not be described in detail here.
[0068] In another embodiment, forming the barrier layer includes the following steps: preparing a barrier layer slurry of a first thickness in the electrode region of the first region, preparing a barrier layer slurry of a second thickness in the non-electrode region of the first region, and drying and curing the barrier layer slurry to form the barrier layer 4.
[0069] The barrier layer slurry is at least one or a combination of alumina slurry, silica slurry, silicon nitride slurry, and silicon oxynitride slurry.
[0070] Barrier layer slurries of different thicknesses are prepared in the electrode area and non-electrode area through processes such as spraying, coating, printing or transfer, and then dried and cured to form barrier layers of different thicknesses 4.
[0071] In one embodiment, the drying temperature is 100℃~200℃ and the curing temperature is 300℃~500℃.
[0072] The N-type doping source in step S3 includes, but is not limited to, phosphorus sources, arsenic sources, etc. After diffusion on the back side in the diffusion device, a corresponding oxide layer is formed on the surface.
[0073] In one embodiment, the N-type dopant source is a phosphorus source, the phosphorus source is phosphorus oxychloride, the phosphorus diffusion doping temperature is 850°C to 950°C, the pressure is 50 mbar to 200 mbar, and the formed oxide layer is a PSG layer.
[0074] In this process, the barrier layer 4 in the electrode region of the first region is thin, resulting in a small barrier effect on phosphorus and a high doping concentration of the N-poly layer in the electrode region; conversely, the barrier layer 4 in the non-electrode region is thick, resulting in a large barrier effect on phosphorus and a low doping concentration of the N-poly layer in the non-electrode region. Therefore, the phosphorus doping concentration in the electrode region of the first region is greater than that in the non-electrode region. This invention forms a selective emitter in the first region through a one-step phosphorus diffusion process, which is simpler and less costly than conventional secondary diffusion processes.
[0075] In one embodiment, the doping concentration of the phosphorus-doped silicon layer in the electrode region of the first region is 4E20 atoms / cm². 3 ~8E20atoms / cm 3 The doping concentration of the phosphorus-doped silicon layer in the non-electrode region of the first region is 8E19 atoms / cm. 3 ~2E20atoms / cm 3 .
[0076] Step S4 includes the following steps:
[0077] S41 removes the oxide layer in the second region. This invention employs a laser grooving process to remove the oxide layer in the second region. The laser grooving is preferably performed using ultraviolet picosecond laser or green picosecond laser, which minimizes damage to the film.
[0078] The ultraviolet picosecond laser has a power of 3W to 20W, a spot diameter of 100μm to 150μm, a laser frequency of 500kHz to 600kHz, and a scanning speed of 40m / s to 80m / s.
[0079] The green picosecond laser has a power of 5W to 50W, a spot diameter of 100μm to 500μm, a laser frequency of 500kHz to 600kHz, and a scanning speed of 40m / s to 80m / s.
[0080] S42 removes the PSG layers on the front and side surfaces of the silicon substrate 1. In one embodiment, the oxide layers on the front and side surfaces are removed by single-sided cleaning with an HF solution. The HF solution is selected from HF solutions with a volume concentration of 5% to 20% or HF solutions with a volume concentration of 0.01 mol / L to 0.03 mol / L.
[0081] S43 removes the N-type doped silicon layer 5 in the second region, and simultaneously removes the N-poly layer deposited around the front side. Preferably, a texturing alkaline solution is used. After removing the N-poly layer, a textured structure is formed on the second region and the front side of the silicon substrate 1, specifically forming a pyramid textured surface. The width of the pyramid is 1 μm to 3 μm, and the reflectivity is 7% to 10%.
[0082] In this invention, the width dimension of the pyramid refers to the width dimension of the pyramid base. The base is square, and the side length of the square is referred to as the base width or base dimension in the industry.
[0083] During this process, the N-poly layer in the first region is protected by the barrier layer 4 and will not be corroded, which ensures that the N-poly layer in the second region is completely removed. At the same time, liquid etching removes the plating around the front and edges.
[0084] Finally, remove barrier layer 4. Barrier layer 4 can be removed using hydrofluoric acid, or it can be removed during RCA cleaning.
[0085] Before preparing the first electrode 6 and the second electrode 7, the method for preparing solar energy further includes: preparing a passivation layer 8 on both sides to form a back passivation layer and a front passivation layer.
[0086] In this invention, the back passivation layer and the front passivation layer are aluminum oxide layers, prepared using the ALD process, with precisely controllable thickness. In one embodiment, the thickness of the aluminum oxide layer is 3 nm to 10 nm.
[0087] The method for preparing solar energy further includes: preparing antireflection layers 9 on both sides to form a back antireflection layer and a front antireflection layer; to further reduce the light reflectivity on both sides.
[0088] The back antireflection layer and the front antireflection layer are selected from one or more stacked films of silicon nitride, silicon oxynitride, and silicon oxide, with a thickness of 70nm to 90nm; they are deposited using PECVD process.
[0089] In one embodiment, the reflectivity of the back surface is 35%–40%.
[0090] In step S5, the back antireflection layer and back passivation layer of the electrode area in the second region are removed first; then metal paste is printed in the electrode areas of the first region and the electrode areas of the second region respectively and sintered to form the first electrode 6 and the second electrode 7.
[0091] In summary, the solar cell fabrication method of the present invention involves forming barrier layers 4 of varying thicknesses in the first region before phosphorus diffusion. The barrier layer 4 in the electrode region has a smaller thickness, resulting in less obstruction of phosphorus diffusion and a higher N-poly layer doping concentration in the electrode region. Conversely, the barrier layer 4 in the non-electrode region has a larger thickness, resulting in greater obstruction of phosphorus diffusion and a lower N-poly layer doping concentration in the non-electrode region. This forms a selective emitter in the first region and improves metal contact in the electrode region. Furthermore, the barrier layer 4 is resistant to alkaline solutions, protecting the N-poly layer in the first region during subsequent processes while effectively removing the N-poly layer in the second region.
[0092] The following provides a specific embodiment and comparative examples to illustrate in detail the method for preparing the solar cell of the present invention.
[0093] Example 1
[0094] Step 1) Select a P-type monocrystalline silicon wafer. First, remove the damaged layer on the surface of the silicon wafer in a mixed solution of KOH and H2O2. Then, perform alkaline polishing in a sodium hydroxide solution or potassium hydroxide solution to form a planar base on the surface of the silicon wafer. The base width is 15μm and the reflectivity is 40%.
[0095] Step 2) A 1.5 nm thick tunneling layer and a 120 nm thick intrinsic amorphous silicon layer are prepared on the back side of the silicon wafer using LPCVD process.
[0096] Step 3) Prepare silicon nitride slurry in the first region on the back side by spraying process. The thickness of silicon nitride slurry in the electrode region is 8nm and the thickness of silicon nitride slurry in the non-electrode region is 18nm. After drying at 150℃~180℃ and annealing and curing at 350℃~400℃, a stable barrier layer 4 is formed on the back side of the first region.
[0097] Step 4) High-temperature phosphorus diffusion is performed on the back side of the silicon wafer using a tubular diffusion apparatus to achieve doping and crystallization of the amorphous silicon layer 3, transforming it into a phosphorus-doped polycrystalline silicon layer. The diffusion temperature is 750℃~950℃, and the phosphorus doping concentration in the electrode region of the first region is 6E20 atoms / cm³. 3 The phosphorus doping concentration in the non-electrode region of the first region is 9E19 atoms / cm. 3 The junction depth is 150nm.
[0098] Step 5) First, a laser grooving process is used to remove the PSG layer in the second region, with a laser power of 50W. Then, RCA cleaning is performed to remove the PSG layers coated on the front and sides. Next, a tank texturing device is used to add potassium hydroxide solution to remove the phosphorus-doped silicon layer in the second region on the front and back sides of the silicon substrate 1, while forming a textured surface structure; the pyramid width of the second region on the front and back sides is 2μm, and the reflectivity is 8%.
[0099] Step 6) Using an ALD device, deposit aluminum oxide films with a thickness of 6 nm on the front and back sides.
[0100] Step 7) Using a PECVD device, deposit silicon nitride films with a thickness of 80 nm on the front and back sides.
[0101] Step 8) Using laser grooving technology, patterned film is opened in the second region to remove the aluminum oxide film and silicon nitride film in the electrode area of the second region.
[0102] Step 9) Screen printing is performed on the back side to form interdigitated emitters, thus obtaining a P-type TBC monocrystalline solar cell.
[0103] Comparative Example 1
[0104] The only difference between Comparative Example 1 and Example 1 is that step 3) was removed, phosphorus diffusion was performed under the same conditions, and the phosphorus doping concentration in the electrode region was 6E20 atoms / cm. 3 The phosphorus doping concentration in the non-electrode region is 9E19 atoms / cm. 3 The junction depth is 150nm.
[0105] The battery test results for Example 1 and Comparative Example 1 are shown in Table 1.
[0106] Table 1
[0107] ITEM Voc(mV) <![CDATA[Jsc(mA / cm 2 )]]> FF (%) EFF (%) IRev2(A) Example 1 724.5 41.77 84.12 25.46 2.1 Comparative Example 1 720.3 41.72 83.88 25.21 4.3
[0108] Note: Voc represents open-circuit voltage, Jsc represents short-circuit current density, FF represents fill factor, EFF represents conversion efficiency, and IRev2 represents leakage current.
[0109] As shown in Table 1, the battery prepared using the method of this invention forms an S3 structure in the first region, while the barrier layer 4 increases the alkali resistance time and reduces leakage current. The battery in Example 1 has a 0.25% higher efficiency and a 2.2A lower leakage current than that in Comparative Example 1, indicating that the solar cell preparation method of this invention has higher conversion efficiency and lower leakage current, while also achieving a higher yield.
[0110] like Figure 5 and Figure 6 As shown, the present invention also provides a solar cell, which can be prepared by the above-described preparation method or by other processes.
[0111] The solar cell includes a P-type silicon substrate, a tunneling layer, an N-type doped crystalline silicon layer and a first electrode located in a first region on the back side of the silicon substrate, and a second electrode located in a second region on the back side of the silicon substrate.
[0112] As described above, the P-type silicon substrate has a front reflectance of 7%-10%, which can improve the light-limiting effect and increase the light absorption rate; the back reflectance is 35%-40%, which can also ensure good light absorption effect.
[0113] In one embodiment, the tunneling layer 2 is a silicon oxide layer or a silicon carbide layer with a thickness of 1 nm to 3 nm, preferably 1 nm to 2.5 nm, and more preferably 1.5 nm to 2 nm.
[0114] In one embodiment, the doping concentration of the N-type doped silicon layer located in the electrode region is greater than that of the N-type doped silicon layer located in the non-electrode region. The N-type doped silicon layer is a selective emitter, which improves the metal contact in the electrode region.
[0115] In one embodiment, the thickness of the N-type doped silicon layer is 100 nm to 150 nm. The N-type doped silicon layer is a phosphorus-doped silicon layer, and the doping concentration of the phosphorus-doped silicon layer in the electrode region is 4E20 atoms / cm. 3 ~8E20atoms / cm 3 The doping concentration of the phosphorus-doped silicon layer in the non-electrode region is 8E19 atoms / cm. 3 ~2E20atoms / cm 3 .
[0116] In one embodiment, the solar cell further includes a back passivation layer located on the back side to passivate the first and second regions and improve the open-circuit voltage.
[0117] In one embodiment, the back passivation layer is an aluminum oxide layer with a thickness of 3 nm to 10 nm. On the one hand, the aluminum oxide layer provides good passivation for both the first and second regions, and it can be prepared using the ALD process, allowing for precise and controllable thickness.
[0118] In one embodiment, the solar cell further includes a back antireflection layer located on the back side to reduce back reflectivity.
[0119] In one embodiment, the back antireflection layer is selected from one or more stacked films of silicon nitride, silicon oxynitride, and silicon oxide, and has a thickness of 70nm to 90nm, which can further reduce the back reflectivity.
[0120] In one embodiment, the back side of the solar cell has both a back passivation layer and a back antireflection layer. The back antireflection layer is located behind the back passivation layer, which improves the back passivation effect, increases the light absorption of the back side, and increases the open-circuit voltage and short-circuit current.
[0121] The first electrode is located in the electrode region of the first region and is in contact with the N-type doped silicon layer of the electrode region, resulting in low contact resistance. The second electrode is located in the electrode region of the second region.
[0122] In one embodiment, the solar cell further includes a front passivation layer located on the front side of the silicon substrate to passivate the first region and the second region, thereby reducing surface recombination.
[0123] In one embodiment, the front passivation layer is an aluminum oxide layer with a thickness of 3 nm to 10 nm. On the one hand, the aluminum oxide layer provides good passivation for both the first and second regions, and it can be prepared using the ALD process, allowing for precise and controllable thickness.
[0124] In one embodiment, the solar cell further includes a front antireflection layer located on the front side to reduce front reflectivity.
[0125] In one embodiment, the front antireflection layer is selected from one or more stacked films of silicon nitride, silicon oxynitride, and silicon oxide, with a thickness of 70nm to 90nm, which can further reduce the front reflectivity and improve battery efficiency.
[0126] In summary, in the solar cell of the present invention, the doping concentration of the N-type doped silicon layer in the electrode region is greater than that in the non-electrode region. The N-type doped silicon layer is a selective emitter, which improves the metal contact in the electrode region and increases the cell efficiency.
[0127] It should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.
[0128] The detailed descriptions listed above are merely specific descriptions of feasible embodiments of the present invention, and are not intended to limit the scope of protection of the present invention. All equivalent embodiments or modifications made without departing from the spirit of the present invention should be included within the scope of protection of the present invention.
Claims
1. A method for preparing a solar cell, characterized in that, Includes the following steps: A tunneling layer and an amorphous silicon layer are deposited on the back side of a P-type silicon substrate, wherein the back side of the P-type silicon substrate has a first region and a second region; A barrier layer of first thickness is prepared in the electrode region of the first region, and a barrier layer of second thickness is prepared in the non-electrode region of the first region, wherein the first thickness is less than the second thickness. The amorphous silicon layer is diffused and doped using an N-type doping source to form an N-type doped crystalline silicon layer and an oxide layer. Remove the oxide layer and N-type doped silicon layer in the second region; The first electrode is prepared in the electrode region of the first region, and the second electrode is prepared in the electrode region of the second region.
2. The method for preparing a solar cell according to claim 1, characterized in that: The first thickness is 1 nm to 10 nm, and / or the second thickness is 11 nm to 30 nm.
3. The method for preparing a solar cell according to claim 1, characterized in that: The barrier layer is selected from one or more combinations of alumina, silicon oxide, silicon nitride, and silicon oxynitride.
4. The method for preparing a solar cell according to claim 1, characterized in that: The preparation of the barrier layer in the first region includes the following steps: preparing a barrier layer of second thickness on the entire back side of the amorphous silicon layer, then removing the barrier layer in the second region, and reducing the thickness of the barrier layer in the electrode region of the first region to the first thickness; Alternatively, the preparation of the barrier layer in the first region may include the following steps: preparing a barrier layer of a first thickness throughout the first region, and then continuing to prepare a barrier layer to a second thickness in the non-electrode region of the first region; Alternatively, the preparation of the barrier layer in the first region may include the following steps: preparing a barrier layer slurry of a first thickness in the electrode region of the first region, preparing a barrier layer slurry of a second thickness in the non-electrode region of the first region, and drying and curing the barrier layer slurry to form the barrier layer, wherein the barrier layer slurry is at least one or a combination of alumina slurry, silicon oxide slurry, silicon nitride slurry, and silicon oxynitride slurry.
5. The method for preparing a solar cell according to claim 4, characterized in that: The preparation of the barrier layer in the first region includes the following steps: using PECVD process, the introduced gas is silane, ammonia or nitrous oxide, the deposition pressure is 1200mTorr~2200mTorr, the radio frequency power is 30000W~40000W, the temperature is 450℃~550℃, and a silicon oxynitride layer with a thickness of 11nm~30nm is formed as the barrier layer. In the second zone, a laser process is used to remove all the blocking layers. An ultraviolet picosecond laser or a filter picosecond laser is selected. The laser power is 45W to 65W, the spot diameter is 100μm to 150μm, the laser frequency is 200kHz to 400kHz, and the scanning speed is 40m / s to 80m / s. In the electrode region of the first region, a portion of the blocking layer is removed using a laser process. An ultraviolet picosecond laser or a filtered picosecond laser is selected, with a laser power of 23W to 40W, a spot diameter of 100μm to 150μm, a laser frequency of 400kHz to 600kHz, a scanning speed of 40m / s to 80m / s, and a remaining blocking layer thickness of 1nm to 10nm.
6. The method for preparing a solar cell according to claim 1, characterized in that: The N-type dopant source is phosphorus oxychloride, and the phosphorus diffusion doping temperature is 850℃~950℃, and the pressure is 50mbar~200mbar.
7. The method for preparing a solar cell according to claim 6, characterized in that: The doping concentration of the phosphorus-doped silicon layer in the electrode region is 4E20 atoms / cm. 3 ~8E20atoms / cm 3 The doping concentration of the phosphorus-doped silicon layer in the non-electrode region is 8E19 atoms / cm. 3 ~2E20atoms / cm 3 .
8. The method for preparing a solar cell according to claim 1, characterized in that: "Removal of the oxide layer and N-type doped silicon layer in the second region" includes: To remove the oxide layer in the second zone, a laser grooving process is used. Remove the oxide layer deposited around the front and side surfaces of the silicon substrate; A texturing alkaline solution is used to remove the N-type doped silicon layer in the second region, and at the same time remove the N-type doped silicon layer that is coated around the front side, forming a texturing structure in the second region and on the front side of the silicon substrate.
9. The method for preparing a solar cell according to claim 8, characterized in that: The front side of the silicon substrate has a pyramidal textured surface, with the width of the pyramids ranging from 1 μm to 3 μm and a reflectivity of 7% to 10%.
10. The method for preparing a solar cell according to claim 1, characterized in that: Before preparing the first electrode and the second electrode, the method for preparing the solar cell further includes the following steps: A passivation layer is prepared on both sides. The passivation layer is an aluminum oxide layer with a thickness of 3nm to 10nm. An antireflection layer is prepared on both sides. The antireflection layer is selected from one or more stacked films of silicon nitride, silicon oxynitride, and silicon oxide. The thickness of the antireflection layer is 70 nm to 90 nm. Remove the antireflection layer and passivation layer from the electrode region of the second region.
11. A solar cell, characterized in that, include: A P-type silicon substrate has a first region and a second region on its back side, the first region having an electrode region and a non-electrode region; The tunneling layer and N-type doped silicon layer are located in the first region. The doping concentration of the N-type doped silicon layer in the electrode region is greater than that in the non-electrode region. The first electrode is located in the electrode region of the first region; The second electrode is located in the second region.
12. The solar cell according to claim 11, characterized in that: The N-type doped silicon layer is a phosphorus-doped silicon layer, with a doping concentration of 4E20 atoms / cm² in the electrode region. 3 ~8E20atoms / cm 3 The doping concentration of the phosphorus-doped silicon layer in the non-electrode region is 8E19 atoms / cm. 3 ~2E20atoms / cm 3 .
13. The solar cell according to claim 11, characterized in that: The reflectivity of the front side of a P-type silicon substrate is 7%-10%, and the reflectivity of the back side is 35%-40%.
14. The solar cell according to claim 11, characterized in that: Also includes: A passivation layer and / or an antireflection layer located on the front side of a silicon substrate; And / or, a back passivation layer and / or a back antireflection layer located on the back side; The front passivation layer and / or the back passivation layer are aluminum oxide layers with a thickness of 3nm to 10nm; the front antireflection layer and / or the back antireflection layer are selected from one or more stacked films of silicon nitride, silicon oxynitride, and silicon oxide, with a thickness of 70nm to 90nm.