I2c-based slave controller, control method, and electronic device
By dividing the I2C controller into an interface module and an application module, serial-to-parallel conversion and protocol conversion are achieved, solving the problem of low development efficiency in existing technologies and improving code readability and module reusability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NANNING QIANHAI YANXIANG ELECTRONIC TECHNOLOGY CO LTD
- Filing Date
- 2026-02-13
- Publication Date
- 2026-06-26
AI Technical Summary
The development efficiency of existing I2C slave controllers is low, and the user application logic and interface logic are glued together, resulting in poor code readability and difficulty in module reuse.
The I2C controller is divided into an interface module and an application module. The interface module connects to the main controller through the I2C bus to realize serial-to-parallel conversion and protocol conversion. The application module processes user logic and realizes data transmission through the user interface, thus isolating the I2C bus protocol from user logic.
It improves the reusability and code readability of the interface module, enhances subsequent development efficiency, and simplifies the development process.
Smart Images
Figure CN122293708A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of controllers, and in particular to an I2C-based slave controller, control method, and electronic device. Background Technology
[0002] I2C (Inter-Integrated Circuit) is a widely used serial communication protocol, also commonly used for communication between Field-Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs) and external devices. In FPGA / CPLD-based I2C slave controller designs, the FPGA / CPLD often acts as an I2C slave controller, providing a read / write interface for external microcontroller units (MCUs). This allows the MCU to read the FPGA's internal status registers and perform write operations to control other modules within the FPGA.
[0003] However, how to design the interaction between the I2C slave controller and other user logic is a problem that every software and hardware R&D field must face. Related technologies often place the user application logic and the I2C slave controller's interface logic in the same module, resulting in tightly coupled logic, poor code readability, and a tendency to be application-specific, making the module largely unusable and leading to low subsequent development efficiency.
[0004] In summary, the I2C slave controller in related technologies suffers from low efficiency in subsequent development. Summary of the Invention
[0005] This application aims to propose an I2C-based slave controller, control method, and electronic device that can improve subsequent development efficiency.
[0006] In a first aspect, embodiments of this application provide an I2C-based slave controller, the slave controller comprising: An interface module is provided, which is connected to an external I2C bus, which is used to connect to the main controller. User interface; The application module is connected to the interface module through the user interface; The interface module is configured to, in response to receiving first target data transmitted by the main controller via the I2C bus, perform protocol conversion and serial-to-parallel conversion on the first target data to obtain converted first target data, and send the converted first target data to the application module through the user interface; the application module is configured to execute corresponding functions based on the converted first target data; and / or, The application module is used to send second target data to the interface module through the user interface; the interface module is used to perform protocol conversion and serial-to-parallel conversion on the second target data to obtain converted second target data, and to send the converted second target data to the main controller through the I2C bus.
[0007] According to some embodiments of this application, the user interface includes features disposed on the interface module: The transmission cycle sub-interface is used to send the bus cycle valid signal; The send request sub-interface is used for sending data signals; The first data sending sub-interface is used to send the first target data; The request receiving sub-interface is used to send data receiving signals; And, set on the application module: The send response sub-interface is used to send a send response signal corresponding to the data send signal; The second data sending sub-interface is used to send the second target data; The receive response sub-interface is used to send a receive response signal corresponding to the receive request.
[0008] According to some embodiments of this application, the user interface includes features disposed on the application module: A clock extension sub-interface is used to send a clock extension enable signal.
[0009] According to some embodiments of this application, the application module includes a register read / write application module, which includes: The address processing logic unit is used to parse the converted first target data and generate corresponding address information and read / write enable information. A first register table is used to perform corresponding read and write operations based on the converted first target data, the address information, and the read / write enable information.
[0010] According to some embodiments of this application, the application module includes a data stream application module, which includes: A second register table is used to buffer the converted first target data; A third register table is used to buffer the second target data; A read / write request response processing logic unit is used to respond to read request signals and write request signals sent by the user interface.
[0011] According to some embodiments of this application, the user interface includes a clock extension sub-interface disposed on the application module, the clock extension sub-interface being used to send a clock extension enable signal, and the application module further includes: A clock extension processing logic module is used to generate the clock extension enable signal.
[0012] Secondly, embodiments of this application provide an I2C-based slave controller control method, applied to the I2C-based slave controller as described in the first aspect embodiment; the method includes: In response to receiving first target data transmitted by the main controller via the I2C bus, the interface module performs protocol conversion and serial-to-parallel conversion on the first target data to obtain converted first target data, and sends the converted first target data to the application module through the user interface; the application module executes corresponding functions based on the converted first target data; and / or, The application module sends the second target data to the interface module through the user interface; the interface module performs protocol conversion and serial-to-parallel conversion on the second target data to obtain the converted second target data, and sends the converted second target data to the main controller through the I2C bus.
[0013] According to some embodiments of this application, the application module is a register read / write application module, which performs corresponding functions based on the converted first target data, including: The application module performs register read and write operations based on the converted first target data.
[0014] According to some embodiments of this application, the application module is a data stream application module, which performs corresponding functions based on the converted first target data, including: The application module buffers the converted first target data stream; and / or, The application module sends the second target data to the interface module through the user interface, including: The application module stores the second target data into a buffer; The second target data in the buffer is sent to the interface module through the user interface.
[0015] Thirdly, embodiments of this application provide an electronic device, the device comprising: a main controller and an I2C-based slave controller as described in the first aspect embodiment, the main controller and the slave controller being connected via an I2C bus.
[0016] The I2C-based slave controller, control method, and electronic device of this application have at least the following beneficial effects: In this embodiment, the controller is divided into an interface module and an application module. The interface module is connected to the main controller via an I2C bus, and data transmission between the interface module and the application module is achieved through a user interface. This application implements serial-to-parallel conversion and protocol conversion functions through the interface module, and implements user logic through the application module. By isolating the I2C bus protocol from the user logic, the reusability and code readability of the interface module are improved, which can improve the efficiency of subsequent development.
[0017] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description
[0018] The present application will be further described below with reference to the accompanying drawings and embodiments, wherein: Figure 1 A schematic diagram of the structure of the I2C-based slave controller provided in this application; Figure 2 An interface diagram of the I2C-based slave controller interface module provided in this application; Figure 3 A schematic diagram of the interface of the application module in the I2C-based slave controller provided in this application; Figure 4 A schematic diagram of the I2C bus start-up conditions in the I2C-based slave controller provided for this application; Figure 5 A schematic diagram of the I2C bus transmission cycle in the I2C-based slave controller provided for this application; Figure 6 A schematic diagram of the write timing of the user interface in the I2C-based slave controller provided in this application; Figure 7 A schematic diagram of the read timing of the user interface in the I2C-based slave controller provided in this application; Figure 8 A timing diagram of the o_usr_cyc signal in the I2C-based slave controller after the Restart write, provided for this application; Figure 9A timing diagram of the o_usr_cyc signal in the I2C-based slave controller after Restart read, provided for this application; Figure 10 A schematic diagram of the structure of the I2C-based slave controller register read / write application module provided in this application; Figure 11 This is a schematic diagram of the structure of the data flow class application module in the I2C-based slave controller provided in this application. Detailed Implementation
[0019] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.
[0020] In this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, without necessarily requiring or implying any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.
[0021] To address the problems of the prior art, embodiments of this application provide an I2C-based slave controller 200, a control method, and an electronic device. The I2C-based slave controller 200 provided in this application embodiment will be described first below.
[0022] Figure 1 A schematic diagram of the structure of an I2C-based slave controller 200 provided in an embodiment of this application is shown. An I2C-based slave controller 200 includes: Interface module 210 is connected to an external I2C bus, which is used to connect to the main controller 100. User interface; Application module 220 is connected to interface module 210 through user interface; The interface module 210 is configured to, in response to receiving first target data transmitted by the main controller 100 via the I2C bus, perform protocol conversion and serial-to-parallel conversion on the first target data to obtain converted first target data, and send the converted first target data to the application module 220 via the user interface; the application module 220 is configured to execute corresponding functions based on the converted first target data; and / or, Application module 220 is used to send second target data to interface module 210 through user interface; interface module 210 is used to perform protocol conversion and serial-to-parallel conversion on the second target data to obtain converted second target data, and to send the converted second target data to main controller 100 through I2C bus.
[0023] In this embodiment, the slave controller 200 is divided into an interface module 210 and an application module 220. The interface module 210 is connected to the master controller 100 via an I2C bus, and data transmission between the interface module 210 and the application module 220 is achieved through a user interface. This application implements serial-to-parallel conversion and protocol conversion functions through the interface module 210, and implements user logic through the application module 220. By isolating the I2C bus protocol from the user logic, the reusability and code readability of the interface module 210 are improved, which can improve the efficiency of subsequent development.
[0024] It should be noted that I2C is a common serial communication protocol, mainly used for short-distance communication between microcontrollers and various peripheral devices. The I2C protocol uses two lines for communication: the serial data line (SDA) and the serial clock line (SCL).
[0025] It should be noted that in this embodiment, the master controller 100 can be an MCU, and the slave controller 200 can be an FPGA or a CPLD. The FPGA / CPLD acts as an I2C slave device, providing a read and write operation interface for external MCU-type devices, allowing the MCU to read the status register inside the FPGA and perform write operations to control other modules.
[0026] Specifically, the interface module 210 is connected to the main controller 100 via the I2C bus. This means that the interface module 210 sends and receives data related to the I2C bus protocol with the main controller 100 via the I2C bus. In this embodiment, the interface module 210 only retains the serial-to-parallel conversion and protocol conversion functions of the slave controller 200. The serial-to-parallel conversion performed by the interface module 210 refers to the conversion between serial data streams and parallel data formats. It should be understood that the serial-to-parallel conversion has different forms depending on the direction of data transmission. When the main controller 100 sends data to the interface module 210, the interface module 210 performs serial-to-parallel conversion. When the interface module 210 sends data to the main controller 100, the interface module 210 performs parallel-to-serial conversion. Under this design, the application module 220 can only process parallel data and does not need to pay attention to the timing of I2C.
[0027] The data sent and received by the interface module 210 is connected to the application module 220 through the user interface. Different application functions are implemented in the application module 220, such as register class, data stream buffer function, etc. When implementing different functions, the application module 220 needs to be configured to the corresponding type.
[0028] The aforementioned first target data refers to the data sent by the master controller 100 to the slave controller 200, such as register configuration, control, or information transmission to the slave device.
[0029] The aforementioned second target data refers to the data sent from controller 200 to main controller, such as feedback status, return measurement results, or response to main controller requests. The second target data can be generated by controller 200 itself, or it can be data received by controller 200 from other modules of the device and then forwarded to main controller 100.
[0030] In this embodiment, since the interface module 210 and the application module 220 are connected via a user interface, the I2C bus protocol is isolated from the application logic. The interaction logic between the interface module 210 and the application module 220 is clear, and the code readability is good. The logic in the interface module 210 is responsible for completing the I2C bus link layer protocol and serial-to-parallel conversion, and does not involve any specific application, giving the module good reusability. In subsequent development, users only need to focus on the interface timing of the user interface to implement parallel data reading and writing, without needing to pay attention to the I2C protocol. Compared to relearning the I2C protocol and the processing and interaction of various information in the interface module 210, development efficiency can be greatly improved.
[0031] In some implementations, the user interface may include: (The following is an example of a feature provided on interface module 210:) The transmission cycle sub-interface is used to send the bus cycle valid signal; The send request sub-interface is used for sending data signals; The first data sending sub-interface is used to send the first target data; The request receiving sub-interface is used to send data receiving signals; And, set on application module 220: The send response sub-interface is used to send a send response signal corresponding to the data send signal; The second data sending sub-interface is used to send the second target data; The receive response sub-interface is used to send the receive response signal corresponding to the receive request.
[0032] In this embodiment, the user interface is formed by the transmission cycle sub-interface, the send request sub-interface, the first data send sub-interface, and the receive request sub-interface set on the interface module 210, and the send response sub-interface, the second data send sub-interface, and the receive response sub-interface set on the application module 220. This enables efficient and stable data transmission between the interface module 210 and the application module 220. The user interface has simple logic and clear read / write operation timing, which can quickly complete the relevant applications of the application module 220.
[0033] refer to Figure 2 and Figure 3 As shown, the user interface set on interface module 210 includes a transmission cycle sub-interface o_usr_cyc, a send request sub-interface o_usr_txreq, a first data send sub-interface o_usr_txdat, and a receive request sub-interface o_usr_rxreq; the user interface on application module 220 includes a send response sub-interface i_usr_txack, a second data send sub-interface i_usr_rxdat, and a receive response sub-interface i_usr_rxack.
[0034] Specifically, the transmission cycle sub-interface o_usr_cyc sends a bus cycle valid signal, i.e., the cyc signal, to the application module 220. A high level indicates an I2C transmission cycle; it is pulled high after address matching and pulled low after STOP. Users can parse data packets based on the cyc signal. The send request sub-interface o_usr_txreq generates a data send signal txreq, i.e., a request to send data to the application module 220. The data send signal txreq is active high. It is pulled low after detecting the send response signal txack from the application module 220. The application module 220 can parse the required address / data from the sent data. The receive request sub-interface o_usr_rxreq sends a data receive signal rxreq, indicating a need to receive data from the application module 220. The data receive signal rxreq is active high.
[0035] Specifically, the first data transmission sub-interface, o_usr_txdat, is used to transmit the first target data, which refers to sending the data received via the I2C bus to the application module 220. The transmit response sub-interface, i_usr_txack, is used to send the transmit response signal txack from the application module 220 to the data transmission signal txreq, indicating that the application module 220 has received the data, and the transmit response signal txack is active high. The second data transmission sub-interface, i_usr_rxdat, is used to transmit the second target data rxdat, which is the feedback data sent by the application module 220 to the interface module 210, and then sent by the interface module 210 to the main controller 100 via the I2C bus. The receive response sub-interface, i_usr_rxack, is used to send the receive response signal from the application module 220 to the data receive signal rxreq, and is synchronized with the second target data rxdat.
[0036] It should be understood that the transmission cycle sub-interface o_usr_cyc, send request sub-interface o_usr_txreq, first data send sub-interface o_usr_txdat, and receive request sub-interface o_usr_rxreq on the aforementioned user interface all have corresponding receive interfaces set on application module 220. Similarly, the send response sub-interface i_usr_txack, second data send sub-interface i_usr_rxdat, and receive response sub-interface i_usr_rxack on application module 220 all have corresponding receive interfaces set on interface module 210, which will not be described in detail here.
[0037] It should be noted that, in addition to the user interface, the interface module 210 also includes an I2C serial interface, a system reset interface i_rst, a system clock interface i_clk, etc.
[0038] It should be noted that, in addition to the user interface, the application module 220 is also equipped with a system reset interface i_rst, a system clock interface i_clk, and user-side data and control information interfaces for sending and receiving signals such as gpi, gpo, wr data bus, and rd data bus.
[0039] The workflow of interface module 210 and user interface is described in detail below: First, let's introduce the data transmission of the I2C bus, referring to... Figure 4As shown, when the I2C clock line remains high and the data line transitions from high to low, it indicates the I2C Start signal, signifying the start of data transmission. Conversely, when the clock line remains high and the data line transitions from low to high, it indicates the I2C Stop signal, signifying the end of data transmission. The start to stop sequence on the I2C bus represents one complete data transmission cycle. When the master controller 100 completes the current data transmission and needs to initiate a new cycle, it can resend the Start signal instead of the Stop signal to begin a new data transmission cycle. This resent Start signal is defined as Restart or Start repeat. Figure 5 As shown, after the master controller 100 sends the Start signal, it must send the address and read / write flag of the slave controller 200 for addressing. Only slave devices whose slave controller 200 address is the same as the received device address can respond to the transmission of the master controller 100.
[0040] like Figure 6 , Figure 7 As shown in condition ①, after receiving the start signal sent by the main controller 100, the interface module 210 receives the addressing information sent by the main controller 100. If the address received by the interface module 210 is the same as its own preset address, o_usr_cyc jumps from low level to high level, indicating that data transmission has started.
[0041] like Figure 6 , Figure 7 As shown in condition ②, after the interface module 210 receives the stop signal sent by the main controller 100, o_usr_cyc jumps from high level to low level, indicating the end of data transmission.
[0042] If interface module 210 receives a start signal again after not receiving a stop signal, interface module 210 first checks whether the new addressing information matches its own address. If they do not match, it pulls o_usr_cyc low to end data transmission. If the addresses match, it then checks the read / write flag. If it is a write flag, it pulls o_usr_cyc low and then pulls it high again. Figure 8 As shown in conditions ② and ③; if it is a read flag, then o_usr_cyc remains high, indicating the end of the data transmission cycle, as shown in condition ③. Figure 9 As shown.
[0043] The write sequence of the user interface is as follows: Figure 6As shown, the o_usr_txreq signal represents a write data request. When the interface module 210 receives 8 bits of data from the main controller 100, it outputs a high level (o_usr_txdat also outputs 8 bits of data). After receiving this signal, the application module 220 outputs a high-level pulse for the i_usr_txack signal. After receiving this signal, the interface module 210 pulls o_usr_txreq low. Figure 6 As shown, ③ indicates that interface module 210 pulls o_usr_txreq high and outputs data on the falling edge of SCL after receiving the 8th bit of data; ④ indicates that application module 220 outputs a high-level pulse signal (i_usr_txack) after receiving the o_usr_txreq high-level signal from interface module 210; ⑤ indicates that interface module 210 pulls o_usr_txreq low after receiving the i_usr_txack high-level signal. This completes a write data operation.
[0044] The read timing of the user interface is as follows: Figure 7 As shown, the o_usr_rxreq signal represents a read data request. When the interface module 210 receives the addressing information from the main controller 100 and confirms that the read / write flag is 1, it outputs a high level. Upon receiving this signal, the application module 220 outputs a high-level pulse for the i_usr_rxack signal and the data i_usr_rxdat fed back to the interface module 210. After receiving the i_usr_rxack signal, the interface module 210 pulls o_usr_rxreq low and converts the parallel data into serial data SDA. Figure 7 As shown in the diagram, ③ indicates that the interface module 210 pulls o_usr_rxreq high when it receives the rising edge of the ACK bit scl; ④ indicates that after receiving the high-level o_usr_rxreq signal from the interface module 210, the application module 220 outputs a high-level pulse signal (i_usr_rxack) and the read data (i_usr_rxdat) fed back to the interface module 210; ⑤ indicates that after receiving the high-level i_usr_rxack signal, the interface module 210 pulls o_usr_rxreq low, completing a read data operation.
[0045] The user interface of this application converts the parallel data after serial-to-parallel conversion by the interface module 210 into an interface protocol that is easy for the application module 220 to understand. The application module 220 does not need to care about the I2C protocol itself. The protocol after conversion by the user interface is simple, thus further improving development efficiency.
[0046] In some implementations, the user interface may also include features located on application module 220: The clock extension sub-interface is used to send clock extension enable signals.
[0047] In this embodiment, a clock extension sub-interface can be set on the user interface to realize the clock extension function and improve the reliability of data transmission.
[0048] It should be noted that the user interface sends the clock extension enable signal i_stretch_en through the clock extension sub-interface o_usr_stretch. The clock extension enable signal indicates that the application module 220 or other modules on the application side need time to process data and request a delay in data transmission. After receiving the rxreq request, if the application module 220 needs more than X clock cycles to prepare the data, it will either pull i_stretch_en high, or the main controller 100 will reduce the I2C frequency, or add dummy data at the message layer.
[0049] In some implementations, application module 220 includes register read / write application module 221, which may include: The address processing logic unit is used to parse the converted first target data and generate corresponding address information and read / write enable information. The first register table is used to perform corresponding read and write operations based on the converted first target data, address information, and read / write enable information.
[0050] In this embodiment, register read / write functionality can be achieved by configuring application module 220 as register read / write application module 221.
[0051] It should be noted that when application module 220 is configured as register read / write application module 221, the data and control information interface is connected to the register table, the status signal gpi is written to the register, and the control signal gpo is output synchronously with the register value. Similarly, the wr data bus signal and the rd data bus signal can also be written to and read from the register.
[0052] For details, please refer to Figure 10As shown, the register read / write application module 221 includes address processing logic and a first register table. The values in the first register table are affected by GPI, WR databus, and user interface write control. The address processing logic unit primarily performs address resolution processing on the I2C output data, i.e., the first target data. Typically, it agrees with the master controller 100 to first send the read or write address to the slave controller 200 after the start of the transmission cycle, and then proceed with subsequent operations. The specific operation process can be divided into the following types. The detailed operation protocol of the register read / write application module 221 is described below: Single register write operation: After usr_cyc is pulled high, the interface module 210 first sends an address, the application module 220 locks the address, and then sends a piece of data. usr_cyc is then pulled low, completing one data transmission.
[0053] Successive register write operations: When usr_cyc is pulled high, the interface module 210 first sends an address, the application module 220 sets this address as the starting address, and then sends one data. usr_cyc is held, and then one data is sent. The application module 220 sets this address as the starting address + 1, then sends another data. The application module 220 sets this address as the starting address + 2, and so on, until all data transmission is completed. Finally, usr_cyc is pulled low, and the transmission ends.
[0054] Discrete register write operation: A single register write operation can be repeated, or a new write operation can be initiated after the main controller 100 issues a Restart signal. It should be noted that for the application module 220, the above operations are the same as a single register write operation; the user interface will pull usr_cyc low after Restart to restart the new data transmission.
[0055] Single register read operation: After usr_cyc is pulled high, an address is received first. Then, the main controller 100 sends a Restart and a read request. During the process of converting the write address to read data, usr_cyc remains high. After the application module 220 locks the read address sent by the user interface, it feeds back the register data of the corresponding address through the user interface when it receives the read request. Finally, usr_cyc is pulled low, and the transmission ends.
[0056] Continuous register read operations: When usr_cyc is pulled high, an address arrives first. The application module 220 sets this address as the starting address, and then a read request arrives. usr_cyc remains active, and then a data transmission arrives. The application module 220 sets this address as the starting address + 1, and then another data transmission arrives with the address set to the starting address + 2. This process continues until all data transmissions are completed, at which point usr_cyc is pulled low, ending the transmission.
[0057] Discrete register read operation: A new read operation is initiated after a single register read operation is repeated or after the main controller 100 issues a Restart signal. It should be noted that for application module 220, similar to a single register write operation, if a write operation follows a Restart, the user interface will pull usr_cyc low to restart the new data transmission.
[0058] The operation of writing to one register first, and then reading from one register: When the read and write addresses are the same: After writing, the main controller 100 sends a ReStart signal and then starts the register read operation.
[0059] When the read and write addresses are different: After writing, the main controller 100 sends a Stop signal and then starts the register read operation; or after writing, the main controller 100 sends a restart signal and then starts the complete read operation.
[0060] The operation of reading one register first and then writing to another register is the same as the operation of a single register. After reading, the main controller 100 sends a Stop signal and then the register writing operation begins; or after reading, the main controller 100 sends a restart signal and then the register writing operation begins.
[0061] In some implementations, application module 220 is a data stream application module 222, which may include: The second register table is used to buffer the converted first target data; The third register table is used to buffer the second target data; The read / write request response processing logic unit is used to respond to read request signals and write request signals sent by the user interface.
[0062] In this embodiment, by configuring the application module 220 as a data stream application module 222, the data stream caching function can be implemented.
[0063] refer to Figure 11As shown, the data flow application module 222 includes a second register table (wr FIFO), a third register table (rd FIFO), a read / write request response processing logic unit (WR ack process logic), and a second clock extension processing logic unit (stretch process logic). The second register table (wr FIFO) receives the first target data from an I2C write request, buffers the data, and allows other user modules to retrieve the data from the rd bus. Conversely, the third register table (rd FIFO) receives data from other user modules, buffers the data, and allows I2C to retrieve the data from read requests. The read / write request response processing logic (WR ack process logic) primarily responds to read and write requests from the user interface.
[0064] The user interface read / write operation timing requires a high-level pulse for one clock cycle. It should be noted that if the wr FIFO is full but the user has not read any data, the user needs to have logic to handle data loss, or the application module 220 should send an interrupt signal to the main controller 100 to notify the main controller 100 that the wr FIFO is full or the rd FIFO is empty, thus suspending the I2C operation.
[0065] It should be noted that application module 220 can be configured as two, that is, simultaneously configuring register read / write application module 221 and data stream application module 222; it can simultaneously implement register read / write and data stream buffering functions, thereby improving the functional types of the slave controller 200.
[0066] It should be noted that the register read / write application module 221 and the data flow application module 222 cover most of the application requirements of the controller 200. Therefore, by setting up the register read / write application module 221 and the data flow application module 222 according to the above implementation method, the user's development needs can be fully met. The user does not need to pay attention to the I2C bus protocol, and the development is simple and efficient.
[0067] In some implementations, the user interface includes a clock extension sub-interface disposed on the application module 220, the clock extension sub-interface being used to send a clock extension enable signal, and the application module 220 further includes: A clock extension processing logic module is used to generate the clock extension enable signal.
[0068] In this embodiment, by setting a clock extension processing logic module within the application module 220, the clock extension function can be implemented, thereby improving the reliability of data transmission.
[0069] refer to Figure 10 and Figure 11As shown, both register read / write application module 221 and data flow application module 222 can be configured with a clock extension processing logic unit (stretch process logic). The clock extension processing logic needs to confirm the I2C operation speed with the main controller 100 and the response time of the application module 220 to the user interface before development. If the response time exceeds half a cycle of the I2C clock, clock extension is required, i.e., a clock extension enable signal is generated, specifically by pulling usr_strectch high, and then the interface module 210 pulls the scl clock low to notify the main controller 100 to suspend data transmission.
[0070] This application also relates to an I2C-based control method for a slave controller 200, used in the slave controller 200 described in the above embodiments; the control method includes: Interface module 210 is configured to, in response to receiving first target data transmitted by main controller 100 via I2C bus, perform protocol conversion and serial-to-parallel conversion on the first target data to obtain converted first target data, and send the converted first target data to application module 220 via user interface; application module 220 is configured to execute corresponding functions based on the converted first target data; and / or, Application module 220 is used to send second target data to interface module 210 through user interface; interface module 210 is used to perform protocol conversion and serial-to-parallel conversion on the second target data to obtain converted second target data, and to send the converted second target data to main controller 100 through I2C bus.
[0071] The control method of this application embodiment is applied to the I2C-based slave controller 200 in the above embodiment. Its specific processing procedure is the same as that of the I2C-based slave controller 200 in the above embodiment, and will not be described in detail here.
[0072] In some implementations, application module 220 is a register read / write application module 221. Application module 220 performs corresponding functions based on the first target data, and may include: Application module 220 performs register read and write operations based on the converted first target data.
[0073] The specific steps of register read / write application module 221 in performing register read / write operations based on the first target data have been described in detail in the above embodiments, and will not be repeated here.
[0074] In some implementations, application module 220 is a data stream application module 222. Application module 220 performs corresponding functions based on the first target data, and may include: Application module 220 performs data stream buffering on the converted first target data; And / or, the application module sends second target data to the interface module 210 through the user interface, including: Application module 220 stores the second target data into a buffer; The second target data in the buffer is sent to the interface module 210 through the user interface.
[0075] The specific process of the data stream application module 222 buffering the first target data and the second target data has been described in detail in the above embodiments, and will not be repeated here.
[0076] This application also relates to an electronic device, which includes a main controller 100 and an I2C-based slave controller 200 as described in the above embodiments, wherein the main controller 100 and the slave controller 200 are connected via an I2C bus.
[0077] It should be clarified that this application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of this application is not limited to the specific steps described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the order of steps, after understanding the spirit of this application.
[0078] The functional blocks shown in the above-described structural diagram can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application-specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of this application are programs or code segments used to perform the required tasks. Programs or code segments can be stored on a machine-readable medium or transmitted over a transmission medium or communication link via data signals carried on a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, etc. Code segments can be downloaded via computer networks such as the Internet, intranets, etc.
[0079] It should also be noted that the exemplary embodiments mentioned in this application describe methods or systems based on a series of steps or apparatus. However, this application is not limited to the order of the above steps; that is, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.
[0080] The aspects of this disclosure have been described above with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that these instructions, executable via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It is also understood that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can also be implemented by special-purpose hardware performing the specified functions or actions, or can be implemented by a combination of special-purpose hardware and computer instructions.
[0081] The above description is merely a specific implementation of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.
Claims
1. A slave controller based on I2C, characterized in that, The slave controller includes: An interface module is provided, which is connected to an external I2C bus, which is used to connect to the main controller. User interface; The application module is connected to the interface module through the user interface; The interface module is configured to, in response to receiving first target data transmitted by the main controller via the I2C bus, perform protocol conversion and serial-to-parallel conversion on the first target data to obtain converted first target data, and send the converted first target data to the application module through the user interface; the application module is configured to execute corresponding functions based on the converted first target data; and / or, The application module is used to send second target data to the interface module through the user interface; the interface module is used to perform protocol conversion and serial-to-parallel conversion on the second target data to obtain converted second target data, and to send the converted second target data to the main controller through the I2C bus.
2. The I2C-based slave controller according to claim 1, characterized in that, The user interface includes features configured on the interface module: The transmission cycle sub-interface is used to send the bus cycle valid signal; The send request sub-interface is used to send data and signals; The first data sending sub-interface is used to send the converted first target data; The request receiving sub-interface is used to send data receiving signals; And, set on the application module: The send response sub-interface is used to send a send response signal corresponding to the data send signal; The second data sending sub-interface is used to send the second target data; The receive response sub-interface is used to send a receive response signal corresponding to the data receive signal.
3. The I2C-based slave controller according to claim 1, characterized in that, The user interface includes features configured on the application module: A clock extension sub-interface is used to send a clock extension enable signal.
4. The I2C-based slave controller according to claim 1, characterized in that, The application module includes a register read / write application module, which includes: The address processing logic unit is used to parse the converted first target data and generate corresponding address information and read / write enable information. A first register table is used to perform corresponding read and write operations based on the converted first target data, the address information, and the read / write enable information.
5. The I2C-based slave controller according to claim 1, characterized in that, The application module includes a data stream application module, which includes: A second register table is used to buffer the converted first target data; A third register table is used to buffer the second target data; A read / write request response processing logic unit is used to respond to read request signals and write request signals sent by the user interface.
6. The I2C-based slave controller according to claim 4 or 5, characterized in that, The user interface includes a clock extension sub-interface configured on the application module, the clock extension sub-interface being used to send a clock extension enable signal, and the application module further includes: A clock extension processing logic module is used to generate the clock extension enable signal.
7. A slave controller control method based on I2C, characterized in that, Applied to any one of claims 1 to 6, the method comprises: In response to receiving first target data transmitted by the main controller via the I2C bus, the interface module performs protocol conversion and serial-to-parallel conversion on the first target data to obtain converted first target data, and sends the converted first target data to the application module through the user interface; the application module executes corresponding functions based on the converted first target data; and / or, The application module sends the second target data to the interface module through the user interface; the interface module performs protocol conversion and serial-to-parallel conversion on the second target data to obtain the converted second target data, and sends the converted second target data to the main controller through the I2C bus.
8. The I2C-based slave controller control method according to claim 7, characterized in that, The application module is a register read / write application module. The application module executes corresponding functions based on the converted first target data, including: The application module performs register read and write operations based on the converted first target data.
9. The I2C-based slave controller control method according to claim 7, characterized in that, The application module is a data stream application module. The application module executes corresponding functions based on the transformed first target data, including: The application module buffers the converted first target data stream; and / or, The application module sends the second target data to the interface module through the user interface, including: The application module stores the second target data into a buffer; The second target data in the buffer is sent to the interface module through the user interface.
10. An electronic device, characterized in that, The device includes: a main controller and an I2C-based slave controller as described in any one of claims 1 to 6, wherein the main controller and the slave controller are connected via an I2C bus.