A power management chip

Abstract

The application discloses a power management chip, comprising: an I2C interface circuit connected with a logic pin of the chip, used for communicating with an external main controller to transfer an adjustment parameter set by the main controller; and a driving circuit used for converting a switching signal into a driving signal and applying the driving signal to a control end of a power switch in the power management chip, adjusting power transmission from an input end to an output end of the power management chip by controlling turn-on and turn-off of the power switch, and providing a stable output voltage, wherein the switching signal is obtained based on the adjustment parameter, and wherein the driving rate of the driving circuit and / or the power supply voltage of the I2C interface circuit can be adjusted, so that the communication accuracy of the chip can be improved by adjusting the driving rate of the driving circuit and / or the power supply voltage of the I2C interface circuit when communication of the I2C interface is interfered.

Description

Technical Field

[0001] This invention relates to the field of power management technology, and more specifically to a power management chip. Background Technology

[0002] With the rapid development of 5G and the Internet of Things, various electronic devices are constantly being upgraded, and the demand is increasing. These electronic devices generally do not use the power grid or batteries for direct power supply. Instead, they convert external high voltage into a precise and stable power supply voltage through voltage regulators such as switching power supply converters. Therefore, power management integrated circuits are very important for these electronic devices.

[0003] In power management chips that require I2C communication, serial data (SDA) and serial clock (SCL) pins are typically used to exchange information between the external host and internal registers, allowing users to flexibly configure charging and discharging parameters and read the power supply status.

[0004] Figure 1 A circuit diagram of an existing I2C interface circuit 100 for a power management chip is shown. Figure 1 As shown, the I2C interface circuit 100 includes a trigger module 110 powered by the I / O voltage and an output buffer 120 powered by the internal voltage.

[0005] The trigger module 110 includes an input terminal 111, which receives the logic input signal SCL_in and couples it to the gates of transistors M1 to M4. Transistors M1 to M4 are sequentially connected between the supply voltage VDIO and the ground voltage Vss, where the supply voltage VDIO is an internal I / O voltage specifically designed for the interface circuit, and the ground voltage Vss is the chip's internal noise ground. The input terminal of inverter 112 is connected to the drains of transistors M2 and M3 at node p1, and its output terminal is connected to the gate of transistor M7 in the output buffer 120. The input terminal of inverter 113 is connected to the output terminal of inverter 112, and its output terminal is connected to the gate of transistor M8 in the output buffer 120. The source of transistor M5 is connected to the drain of transistor M1 and the source of transistor M2, and the drain is connected to ground voltage Vss. The source of transistor M6 is connected to the source of transistor M3 and the drain of transistor M4, and the drain is connected to the supply voltage VDIO. The gates of transistors M5 and M6 are connected to the output of inverter 113 at node p2.

[0006] The output buffer 120 also includes transistors M9 and M10. The sources of transistors M9 and M10 are connected to the power supply voltage VDD. The gate of transistor M9 is connected to the drain of transistor M10. The gate of transistor M10 is connected to the drain of transistor M9. The drains of transistors M9 and M10 are also connected to the drains of transistors M7 and M8, respectively. The sources of transistors M7 and M8 are connected to the ground voltage Vss. The drain of transistor M8 is also connected to the logic output signal SCL_out.

[0007] also, Figure 1 The resistor R1 and transistor M0 are the peripheral circuits of the chip. The resistor R1 and transistor M0 are connected in sequence between the voltage VREF_out and the ground voltage Vss_out, where the voltage VREF_out and the ground voltage Vss_out are the power supply and ground of the peripheral circuit, respectively.

[0008] When there is no voltage difference between the ground and power supply in the internal and external circuits of the chip, the host control signal Host Control controls the conduction and turn-off of transistor M0 by controlling the gate voltage of transistor M0. When transistor M0 is turned on, the logic input signal SCL_in is equal to Vss_out + Vds(M0), which is approximately equal to the ground voltage Vss_out; when transistor M0 is turned off, the logic input signal SCL_in is equal to the voltage VREF_out - VR1, which is approximately equal to the voltage VREF_out.

[0009] When the logic input signal SCL_in is low, transistors M1, M2, and M6 are turned on, while transistors M3 to M5 are turned off. The voltage at nodes p1 and p2 is approximately equal to the supply voltage VDIO. Subsequently, transistor M8 is turned on, pulling the logic output signal SCL_out low to ground voltage Vss. When the logic input signal SCL_in transitions from low to high, if the voltage of the logic input signal SCL_in is greater than the turn-on threshold of transistor M4, transistor M4 is turned on first, followed by transistor M3. Then, transistors M1 and M2 are turned off, nodes p1 and p2 are pulled low to Vss, transistor M8 is turned off, and the logic output signal SCL_out is pulled high to the power supply VDD, ultimately achieving the transition of the logic output signal SCL_out from low to high. Similarly, this circuit can also generate a transition of the logic output signal SCL_out from high to low, realizing the level conversion between the logic signal of the external power rail (i.e., HostControl) and the logic signal of the internal power rail.

[0010] However, in practical applications, the ground and power supply of the chip's internal and external circuits may have a certain voltage difference due to noise or connection methods. When there is a voltage difference between the power rails of the chip's internal and external circuits, it may cause false triggering or missed triggering of signals in the internal circuits and I2C communication.

[0011] Taking the case where the internal ground voltage is lower than the external ground voltage as an example, such as Figure 2 The diagram shows the operating waveforms of the existing I2C interface circuit 100. Figure 2 The diagram shows the level changes of the logic input signal SCL_in and the logic output signal SCL_out, respectively. Figure 2 The slashed area in the diagram represents the effective input voltage range under ideal conditions, while the shaded area represents the effective input voltage range under actual conditions. Ideally, the low level of the logic input signal SCL_in falls within Vss to VDD_lmax, and the high level falls within Vin_hmin to VDIO (e.g., ...). Figure 2 When the slanted area is shown in the diagram, the internal I2C interface circuit can correctly recognize the logic input signal SCL_in and the output will flip (as shown by the dashed line of the SCL_out signal). However, when the ground voltage of the internal I2C interface circuit decreases due to the switching noise of the power transistors in the switching power supply converter, the effective voltage range decreases accordingly. Figure 2 As shown in the shaded area, the high and low levels of the logic input signal SCL_in may fall outside the voltage range defined by the shaded area, causing the internal I2C interface circuit to fail to properly recognize the level changes of the logic input signal SCL_in and resulting in a leakage flip, such as... Figure 2 The solid line in SCL_out indicates that this interferes with I2C communication. Summary of the Invention

[0012] In view of this, the purpose of the present invention is to provide a power management chip that can adjust the power supply voltage of the I2C interface circuit, thereby improving the communication stability of the I2C interface while balancing the efficiency of the DC / DC converter.

[0013] According to an embodiment of the present invention, a power management chip is provided, comprising: an I2C interface circuit connected to a logic pin of the chip for communicating with an external main controller to transmit adjustment parameters set by the main controller; and a drive circuit for converting a switching signal into a drive signal and applying it to a control terminal of a power switch in the power management chip, thereby regulating the power transfer from the input terminal to the output terminal of the power management chip by controlling the on and off states of the power switch to provide a stable output voltage, wherein the switching signal is obtained based on the adjustment parameters, and the drive rate of the drive circuit and / or the supply voltage of the I2C interface circuit can be adjusted.

[0014] Optionally, the driving circuit includes: a buffer, the input of which is used to receive the switching signal; a first totem pole circuit and a second totem pole circuit connected in parallel, the first totem pole circuit and the second totem pole circuit being used to charge and discharge the control terminal of the power switch based on the output of the buffer; and a driving control module, used to receive a first adjustment signal and control the signal path between the second totem pole circuit and the buffer based on the first adjustment signal, thereby adjusting the driving rate of the driving circuit by controlling the opening and closing of the second totem pole circuit.

[0015] Optionally, the I2C interface circuit includes: a power supply voltage generation module for providing a power supply voltage to the trigger module, the power supply voltage generation module also being used to receive a second adjustment signal and adjust the voltage value of the power supply voltage according to the second adjustment signal; the trigger module for receiving a logic input signal from the logic pin of the chip and comparing the logic input signal with a threshold voltage to generate a first signal; and an output buffer for shaping the first signal to obtain a logic output signal.

[0016] Optionally, the second totem pole circuit includes: a first transistor and a second transistor connected between a first voltage and a second voltage, the control terminals of the first transistor and the second transistor being connected to the output of the drive control module, and the intermediate node of the first transistor and the second transistor being connected to the control terminal of the power switch.

[0017] Optionally, the drive control module includes: a first switch connected between the output of the buffer and the control terminal of the first transistor; and a second switch connected between the output of the buffer and the control terminal of the second transistor, wherein the first adjustment signal controls the signal path between the buffer and the second totem pole circuit by controlling the on and off states of the first and second switches.

[0018] Optionally, the drive control module further includes: a third transistor, the first end of which is connected to the first voltage, the second end of which is connected to the control terminal of the first transistor, and the control terminal is connected to the first adjustment signal; and a fourth transistor, the first end of which is connected to the control terminal of the second transistor, the second end of which is connected to the second voltage, and the control terminal is connected to the inverted signal of the first adjustment signal.

[0019] Optionally, when the first adjustment signal is high, the first switch and the second switch are turned on, and the third transistor and the fourth transistor are turned off. The first transistor and the second transistor are turned on non-overlapping according to the output of the buffer. When the first adjustment signal is low, the first switch and the second switch are turned off, and the third transistor and the fourth transistor are turned on, thus turning off the first transistor and the second transistor.

[0020] Optionally, the first transistor and the third transistor are P-channel transistors, and the second transistor and the fourth transistor are N-channel transistors.

[0021] Optionally, the power supply voltage generation module includes: a first current source, a fifth transistor, a sixth transistor, and a first resistor connected sequentially between the power supply voltage and the ground voltage, wherein the fifth transistor and the sixth transistor are respectively connected as MOS diodes; a seventh transistor and a second current source connected sequentially between the power supply voltage and the ground voltage, wherein the control terminal of the seventh transistor is connected to the second terminal of the first current source, and the second terminal of the seventh transistor is used to output the power supply voltage; an inverter, wherein the input terminal of the inverter is used to receive the second adjustment signal; and an eighth transistor connected in parallel with the sixth transistor, wherein the control terminal of the eighth transistor is connected to the output terminal of the inverter.

[0022] Optionally, the trigger module is a Schmitt trigger.

[0023] Optionally, the ground voltage is the noise ground inside the chip.

[0024] Optionally, the power management chip further includes: a power circuit, including at least one power switch and an inductor, wherein the power switch is used to regulate the power transfer from the input terminal to the output terminal of the power management chip to provide a stable output voltage; a logic control circuit, used to receive the adjustment parameters input from the I2C interface circuit and convert them into parameter information that can be realized by the switch controller; and the switch controller, used to generate the corresponding switch signal according to the parameter information.

[0025] Optionally, the adjustment signals for the driving rate of the driving circuit and / or the power supply voltage of the I2C interface circuit can come from external adjustment signals or from the logic control circuit.

[0026] The power management chip provided by this invention includes an I2C interface circuit and can provide a first adjustment signal and / or a second adjustment signal when interference occurs in the I2C interface circuit communication. This adjustment signal regulates the drive rate of the drive circuit and / or the supply voltage of the I2C interface circuit, thereby reducing the converter's drive speed or even increasing the supply voltage of the I2C interface circuit when I2C communication is interfered with, thus improving communication accuracy. Furthermore, the power management chip of this invention can optimize and balance corresponding functions according to actual applications, thereby balancing converter efficiency while improving communication accuracy. Attached Figure Description

[0027] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings.

[0028] Figure 1 A circuit diagram of an existing I2C interface circuit 100 for a power management chip is shown.

[0029] Figure 2 The waveform diagram of the existing I2C interface circuit is shown.

[0030] Figure 3 A structural block diagram of a control system for a power management chip according to an embodiment of the present invention is shown;

[0031] Figure 4 A structural block diagram of a power management chip according to an embodiment of the present invention is shown;

[0032] Figure 5 A circuit diagram of a drive circuit in a power management chip according to an embodiment of the present invention is shown;

[0033] Figure 6 A circuit diagram of the I2C interface circuit in a power management chip according to an embodiment of the present invention is shown. Detailed Implementation

[0034] The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown in the drawings.

[0035] Many specific details of the invention, such as the structure, materials, dimensions, processing methods, and techniques of the components, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without following these specific details.

[0036] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it may be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0037] Figure 3 A block diagram of a control system for a power management chip according to an embodiment of the present invention is shown. Figure 3 As shown, the control system includes a power management chip 200 and a main controller 300. The power management chip 200 is used to supply power to the various functional modules of the terminal. The main controller 300 is used to detect the power supply voltage and actual power consumption of each functional module and transmit the adjustment parameters corresponding to the requirements to the power management chip 200. The power management chip 200 is also used to output the power supply voltage to each functional module according to the adjustment parameters.

[0038] In a preferred embodiment, both the main controller 300 and the power management chip 200 are equipped with communication modules to ensure that the main controller 300 can correctly transmit adjustment parameters to the power management chip 200. Furthermore, both the communication module of the main controller 300 and the internal communication module of the power management chip 200 are I2C communication modules, ensuring the stability of information transmission. In a preferred embodiment, the main controller 300 and the power management chip 200 are connected via an I2C bus, using the serial data (SDA) and serial clock (SCL) lines of the I2C bus to exchange information between the external host and the internal registers of the chip. This allows users to flexibly configure charging and discharging parameters and read the current state of the power supply.

[0039] Figure 4 The diagram shows a structural block diagram of a power management chip according to an embodiment of the present invention. The power management chip of the present invention is also known as a programmable power management chip (or output voltage programmable power chip, or simply chip). It includes: a power circuit 201, an I2C interface circuit 202, a logic control circuit 204, a switch controller 205, and a drive circuit 206.

[0040] The power circuit 201 includes one or more switching elements and filter elements (e.g., inductors and / or capacitors), which are configured to regulate the power transfer from the input to the output of the switching converter in response to a switching drive signal, so as to convert the input voltage Vin into a stable and continuous output voltage Vout.

[0041] In some embodiments, according to the topology classification of the power circuit 201, it can be divided into a buck converter, a boost converter, a flyback converter, and a buck-boost converter.

[0042] In this embodiment, the power circuit 201 is implemented using a buck topology, including a power switch Mx and peripheral inductors Lx and rectifier diodes D1. The first terminal of the power switch Mx is connected to the input voltage Vin, and the second terminal is connected to the anode of the rectifier diode D1. The cathode of the rectifier diode D1 is grounded. The common terminal of the power switch Mx and the rectifier diode D1 forms a switching node SW. The first terminal of the inductor Lx is connected to this switching node, and the second terminal is connected to the output voltage Vout. The power switch Mx can be any controllable semiconductor switching device, such as a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated-gate bipolar transistor (IGBT).

[0043] It should be noted that although a MOSFET is used as a switching element in this embodiment, any other suitable switching element of any type can be used without departing from the principles of the invention. Furthermore, although this embodiment is described using a non-synchronous buck converter, the invention is not limited thereto; the invention is equally applicable to synchronous buck converters, and those skilled in the art can use a synchronous rectifier switching element instead of the rectifier diode D1 in the above embodiment.

[0044] The I2C interface circuit 202 is connected to the serial clock (SCL) pin and serial data (SDA) pin of the chip. It is mainly responsible for communicating with the I2C controller of the main controller and transmitting the adjustment parameters set by the main controller.

[0045] The logic control circuit 204 receives adjustment parameters input from the I2C interface circuit 202 and converts them into parameter information that the switch controller 205 can implement. This module can be enabled by an external host. Specifically, the logic control circuit 204 can use a DAC to convert the input adjustment parameters into a level signal or into a pulse signal with an adjustable duty cycle, thereby controlling the switch controller 205. Of course, the logic control circuit 204 of this invention is not limited to the above-described manner.

[0046] The switch controller 205 is the main control component of the power management chip. It controls the switching of the power supply branch via the power switch Mx, thereby achieving different output voltage values. Specifically, the switch controller 205 is connected to the chip's feedback signal FB, used to obtain a voltage divider signal for the output voltage Vout based on the feedback signal, and adjusts the switching of the power switch Mx according to this voltage divider signal to stabilize the output voltage Vout. In some embodiments, the voltage divider value of the output voltage Vout is obtained through a voltage divider network composed of external resistors R1 and R2. Furthermore, the switch controller in this invention may include a pulse width modulation (PWM), pulse frequency modulation (PFM), or pulse-width modulation-frequency modulation (PWM-PFM) controller.

[0047] The drive circuit 206 is used to generate a drive signal for the power switch Mx according to the switch signal output by the switch controller 205 and apply it to the gate of the power switch Mx to control the power switch Mx to turn on and off.

[0048] To address the issue of false triggering or missed triggering of the I2C interface circuit caused by switching noise of the power switch Mx in the prior art, the power management chip 200 of this embodiment further includes switching the driving speed of the driving circuit 206 based on the first adjustment signal CTR1 or adjusting the power supply voltage of the I2C interface circuit based on the second adjustment signal CTR2, so as to improve the communication stability of the I2C interface circuit and balance the efficiency problem of the DC / DC converter.

[0049] In one embodiment, the first adjustment signal CTR1 and the second adjustment signal CTR2 can be obtained through external trimming. In another embodiment, the logic control circuit 204 can also generate the first adjustment signal CTR1 and / or the second adjustment signal CTR2 when interference occurs in the communication of the I2C interface circuit 201. The first adjustment signal CTR1 is used to adjust the driving speed of the drive circuit 206, and the second adjustment signal CTR2 is used to adjust the supply voltage of the I2C interface circuit 201. This can reduce the driving speed of the converter or even increase the supply voltage of the I2C interface circuit 201 when interference occurs in I2C communication, thereby improving the communication accuracy. When the supply voltage of the I2C interface circuit 201 cannot be adjusted, the logic control circuit 204 can also adjust the driving speed of the drive circuit 206 to adapt to the communication accuracy of the I2C interface. Therefore, the power management chip 200 of this embodiment can optimize and balance the corresponding functions according to the actual application.

[0050] Figure 5 A circuit diagram of a drive circuit in a power management chip according to an embodiment of the present invention is shown. In this embodiment, the drive circuit 206 uses several totem-pole circuits to drive the power switch Mx. For example... Figure 5As shown, the driving circuit 206 includes a buffer 261, a first totem pole circuit 262, and a second totem pole circuit 263, which are implemented by multiple cascaded totem pole circuits.

[0051] The input terminal of the buffer 261 is connected to the input terminal of the buffer from the buffer. Figure 4 The switching controller 205 is connected to the switching signal DRV and applies the output signal to the input terminals of the first totem pole circuit 262 and the second totem pole circuit 263. The first totem pole circuit 262 and the second totem pole circuit 263 are connected in parallel between the voltage VSW+ΔV and the switching node VSW. Their output terminals are connected to the gate of the power switch Mx and are used to charge and discharge the gate of the power switch Mx to turn the power switch Mx on or off.

[0052] Specifically, the first totem-pole circuit 262 includes transistors M11 and M12, and the second totem-pole circuit 263 includes transistors M13 and M14. Transistors M11 and M13 are, for example, P-channel transistors, and transistors M12 and M14 are, for example, N-channel transistors. The gates of transistors M11 and M12 are connected to the output of buffer 261. The source of transistor M11 is connected to voltage VSW+ΔV, and its drain is connected to the drain of transistor M12 and the gate of power switch Mx. The source of transistor M12 is connected to the switching node VSW. The source of transistor M13 is connected to voltage VSW+ΔV, and its drain is connected to the drain of transistor M14 and the gate of power switch Mx. Transistors M11 and M12 are complementary in conduction, as are transistors M13 and M14. Transistors M11 and M13 charge the gate of power switch Mx to turn it on when it is on, while transistors M12 and M14 discharge the gate of power switch Mx to turn it off when it is on. During the turn-off process of power switch Mx, rectifier diode D1 freewheels through inductor Lx, pulling the internal ground voltage of the chip down. This generates noise that is difficult to eliminate in the chip's I2C interface circuit.

[0053] To address this issue, the drive circuit 206 in this embodiment further includes a drive control module 264. The drive control module 264 controls the signal path between the second totem pole circuit 263 and the buffer 261 based on the first adjustment signal CTR1, thereby controlling the switching of the second totem pole circuit 263 and thus adjusting the drive rate of the power switch Mx.

[0054] The first adjustment signal CTR1 can be enabled to be either logic high or low. When the first adjustment signal CTR1 is high, the second totem-pole circuit 263 is turned on. At this time, the power switch Mx is driven by both the first totem-pole circuit 262 and the second totem-pole circuit 263. The switching rate of the power switch Mx is relatively fast, but the noise in the I2C interface circuit is also relatively high. When the first adjustment signal CTR1 is low, the second totem-pole circuit 263 is turned off. At this time, the power switch Mx is driven only by the first totem-pole circuit 262. Because the time constant from the pre-stage buffer to the power switch Mx is relatively small, the switching rate of the power switch Mx is slower, and the noise in the I2C interface circuit is also lower.

[0055] Specifically, the drive control module 264 in this embodiment includes an inverter INV1, a switch 301, a switch 302, and transistors M15 and M16.

[0056] The inverter INV1 has an input terminal for receiving the first adjustment signal CTR1 and an output terminal for outputting the inverted signal of the first adjustment signal.

[0057] The input terminal of switch 301 is connected to the output of buffer 261, and the output terminal is connected to the gate of transistor M13. The switching on and off of switch 301 is controlled by a first adjustment signal CTR1. When switch 301 is on, it connects the signal path between buffer 261 and the gate of transistor M13; when switch 301 is off, it disconnects the signal path between buffer 261 and the gate of transistor M13. Switch 301 can be implemented, for example, by parallel connection of an N-channel transistor M17 and a P-channel transistor M18. The first terminals of transistors M17 and M18 are interconnected as the input terminal of switch 301, connected to the output of buffer 261. The second terminals of transistors M17 and M18 are interconnected as the output terminal of switch 301, connected to the gate of transistor M13. The gate of transistor M17 is connected to the first adjustment signal CTR1, and the gate of transistor M18 is connected to the inverted signal of the first adjustment signal CTR1.

[0058] Transistor M15 is a P-channel transistor. Its gate is connected to the first adjustment signal CTR1, its source is connected to the voltage VSW+ΔV, and its drain is connected to the gate of transistor M13.

[0059] The input terminal of switch 302 is connected to the output of buffer 261, and the output terminal is connected to the gate of transistor M14. The switching on and off of switch 302 is controlled by a first adjustment signal CTR1. When switch 302 is on, it connects the signal path between buffer 261 and the gate of transistor M14; when switch 302 is off, it disconnects the signal path between buffer 261 and the gate of transistor M14. Switch 302 can be implemented, for example, by parallel connection of an N-channel transistor M19 and a P-channel transistor M20. The first terminals of transistors M19 and M20 are interconnected as the input terminal of switch 302, connected to the output of buffer 261. The second terminals of transistors M19 and M20 are interconnected as the output terminal of switch 302, connected to the gate of transistor M14. The gate of transistor M19 is connected to the first adjustment signal CTR1, and the gate of transistor M20 is connected to the inverted signal of the first adjustment signal CTR1.

[0060] Transistor M16 is an N-channel transistor. Its gate is connected to the inverted signal of the first adjustment signal CTR1, its source is connected to the voltage VSW, and its drain is connected to the gate of transistor M14.

[0061] When the first adjustment signal CTR1 is low, switches 301 and 302 are turned off, breaking the signal path between buffer 261 and the gates of transistors M13 and M14. Simultaneously, transistors M15 and M16 are turned on, pulling the gate of transistor M13 up to voltage VSW+ΔV and pulling the gate of transistor M14 down to voltage VSW, respectively, thus turning off transistors M13 and M14. When the first adjustment signal CTR1 is high, switches 301 and 302 are turned on, transistors M15 and M16 are turned off, and transistors M13 and M14 are complementaryly turned on according to the output of buffer 261, participating in the driving process of power switch Mx.

[0062] As can be seen from the above description, the power management chip in this embodiment can reduce the noise generated in the I2C interface circuit by reducing the switching rate of the power switch. However, the reduction in the driving rate will cause the power switch to consume energy during the turn-on and turn-off process, thereby losing the power conversion efficiency.

[0063] Figure 6 A circuit diagram of the I2C interface circuit in a power management chip according to an embodiment of the present invention is shown. Figure 6 As shown, the I2C interface circuit 202 in this embodiment includes a power supply voltage generation module 221, a trigger module 222, and an output buffer 223. The power supply voltage generation module 221 generates a power supply voltage VDIO for the trigger module 222 based on the power supply voltage VDD, and the output buffer 223 is directly powered by the power supply voltage VDD.

[0064] The power supply voltage generation module 221 includes current sources I1 and I2, inverter INV2, resistor R12, and transistors M21 to M24. Transistors M21 to M24 are N-channel transistors. The first terminal of current source I1 is connected to the power supply voltage VDD, and the second terminal is connected to the gate and drain of transistor M21. The source of transistor M21 is connected to the drain and gate of transistor M22. The source of transistor M22 is connected to the first terminal of resistor R12, and the second terminal of resistor R12 is connected to ground voltage Vss. The input terminal of inverter INV2 is connected to the second adjustment signal CTR2, and the output terminal is connected to the gate of transistor M23. The drain of transistor M23 is connected to the drain of transistor M22, and the source of transistor M23 is connected to the source of transistor M22. The drain of transistor M24 is connected to the power supply voltage VDD, the gate is connected to the common node between current source I1 and transistor M21, the source is used to output the power supply voltage VDIO, and the current source I2 is connected between the source of transistor M24 and the ground voltage Vss.

[0065] When the second adjustment signal CTR2 is low, transistor M23 is turned on, thus short-circuiting transistor M22. According to the formula VDIO = I1 × R12 + Vth_M21 - Vth_M24, where Vth_M21 and Vth_M24 are the turn-on thresholds of transistors M21 and M24, respectively, the first voltage value of the supply voltage VDIO can be calculated, for example, 1.2V. When the second adjustment signal CTR2 is high, transistor M23 is turned off. According to the formula VDIO = I1 × R12 + Vth_M21 + Vth_M22 - Vth_M24, where Vth_M22 is the turn-on threshold of transistor M22, the second voltage value of the supply voltage VDIO can be calculated, for example, 1.8V. According to the I2C communication protocol, increasing the supply voltage can make the logic input signal of the flip-flop module 222 change a wider range. Even if the voltage difference between the internal ground and the external ground of the chip is relatively large, the flip-flop module 222 can more easily identify the switching of the SDA and SCL signals.

[0066] Furthermore, the trigger module 222 is implemented, for example, using a Schmitt trigger, and includes an input terminal 111, which receives the logic input signal SCL_in and couples it to the gates of transistors M1 to M4. Transistors M1 to M4 are sequentially connected between the supply voltage VDIO and the ground voltage Vss, where the supply voltage VDIO is an internal I / O voltage specifically designed for the interface circuit, and the ground voltage Vss is the chip's internal noise ground. The input terminal of inverter 112 is connected to the drains of transistors M2 and M3 at node p1, and its output terminal is connected to the gate of transistor M7 in output buffer 223. The input terminal of inverter 113 is connected to the output terminal of inverter 112, and its output terminal is connected to the gate of transistor M8 in output buffer 223. Output buffer 223 is used to shape the output signals of inverters 112 and 113 to obtain the logic output signal SCL_out. The source of transistor M5 is connected to the drain of transistor M1 and the source of transistor M2, and the drain is connected to ground voltage Vss. The source of transistor M6 is connected to the source of transistor M3 and the drain of transistor M4, and the drain is connected to the supply voltage VDIO. The gates of transistors M5 and M6 are connected to the output of inverter 113 at node p2.

[0067] The output buffer 223 also includes transistors M9 and M10. The sources of transistors M9 and M10 are connected to the power supply voltage VDD. The gate of transistor M9 is connected to the drain of transistor M10. The gate of transistor M10 is connected to the drain of transistor M9. The drains of transistors M9 and M10 are also connected to the drains of transistors M7 and M8, respectively. The sources of transistors M7 and M8 are connected to the ground voltage Vss. The drain of transistor M8 is also connected to the output terminal of the logic output signal SCL_out.

[0068] In this circuit, transistors M1, M2, M5, M9, and M10 are P-channel transistors, while transistors M3, M4, M6, M7, and M8 are N-channel transistors. When the logic input signal SCL_in is low, transistors M1, M2, and M6 are turned on, while transistors M3 through M5 are turned off. The voltage at nodes p1 and p2 is approximately equal to the supply voltage VDIO. Subsequently, transistor M8 is turned on, pulling the logic output signal SCL_out low to ground voltage Vss. When the logic input signal SCL_in transitions from low to high, if the voltage of the logic input signal SCL_in is greater than the turn-on threshold of transistor M4, transistor M4 is turned on first, followed by transistor M3. Then, transistors M1 and M2 are turned off, nodes p1 and p2 are pulled low to Vss, transistor M8 is turned off, and the logic output signal SCL_out is pulled high to the power supply VDD, ultimately achieving the transition of the logic output signal SCL_out from low to high. Similarly, this circuit can also generate a transition from high to low level for the logic output signal SCL_out, realizing the level conversion between the logic signal of the external power rail (i.e., HostControl) and the logic signal of the internal power rail.

[0069] In summary, the power management chip provided by this invention includes an I2C interface circuit and can provide a first adjustment signal and / or a second adjustment signal when interference occurs in the I2C interface circuit communication. This allows for adjustment of the drive rate of the drive circuit and / or the supply voltage of the I2C interface circuit, thereby reducing the converter's drive speed or even increasing the supply voltage of the I2C interface circuit when I2C communication is interfered with, thus improving communication accuracy. Furthermore, the power management chip of this invention can optimize and balance corresponding functions according to actual applications, thereby balancing converter efficiency while improving communication accuracy.

[0070] It should be noted that although devices are described herein as N-channel or P-channel devices, or N-type or P-type doped regions, those skilled in the art will understand that complementary devices are also possible according to the present invention. Those skilled in the art will understand that conductivity type refers to the mechanism by which conductivity occurs, such as conduction through holes or electrons; therefore, conductivity type relates to doping type, such as P-type or N-type, rather than doping concentration. Those skilled in the art will understand that the terms “during,” “when,” and “when…” used herein in relation to circuit operation are not strict terms indicating an action that occurs immediately at the start of a startup action, but rather that there may be one or more small but reasonable delays between the startup action and the reaction action initiated by it, such as various propagation delays. The terms “approximately” or “substantially” used herein mean that an element value has a parameter expected to be close to the declared value or location. However, as is well known in the art, there are always small deviations that make it difficult for the value or location to be strictly the declared value. It has been properly determined in the art that a deviation of at least 10 percent (10%) (or at least 20 percent (20%) for semiconductor doping concentration) is a reasonable deviation from the described accurate ideal target. When used in conjunction with signal states, the actual voltage value or logic state of the signal (e.g., "1" or "0") depends on whether positive or negative logic is used.

[0071] Furthermore, it should be noted that in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0072] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A power management chip, comprising: The I2C interface circuit is connected to the logic pins of the chip and is used to communicate with the external main controller to transmit the adjustment parameters set by the main controller. as well as A drive circuit is used to convert the switching signal into a drive signal and apply it to the control terminal of the power switch in the power management chip. By controlling the on and off of the power switch, the power transfer from the input terminal to the output terminal of the power management chip is adjusted to provide a stable output voltage. The switching signal is obtained based on the adjustment parameters. The driving rate of the driving circuit and / or the power supply voltage of the I2C interface circuit can be adjusted. The driving circuit includes: A buffer, the input of which is used to receive the switching signal; A first totem-pole circuit and a second totem-pole circuit are connected in parallel. The first totem-pole circuit and the second totem-pole circuit are used to charge and discharge the control terminal of the power switch based on the output of the buffer; and The drive control module is used to receive a first adjustment signal and control the signal path between the second totem pole circuit and the buffer based on the first adjustment signal, thereby adjusting the drive rate of the drive circuit by controlling the opening and closing of the second totem pole circuit.

2. The power management chip according to claim 1, wherein, The I2C interface circuit includes: A power supply voltage generation module is used to provide a power supply voltage to the trigger module. The power supply voltage generation module is also used to receive a second adjustment signal and adjust the voltage value of the power supply voltage according to the second adjustment signal. The trigger module is configured to receive logic input signals from the logic pins of the chip, and to compare the logic input signals with a threshold voltage to generate a first signal; and An output buffer is used to shape the first signal to obtain a logic output signal.

3. The power management chip according to claim 1, wherein, The second totem pole circuit includes: A first transistor and a second transistor are connected between a first voltage and a second voltage. The control terminals of the first transistor and the second transistor are connected to the output of the drive control module. The intermediate node of the first transistor and the second transistor is connected to the control terminal of the power switch.

4. The power management chip according to claim 3, wherein, The drive control module includes: A first switch is connected between the output of the buffer and the control terminal of the first transistor; and The second switch is connected between the output of the buffer and the control terminal of the second transistor. The first adjustment signal controls the signal path between the buffer and the second totem pole circuit by controlling the on and off states of the first and second switches.

5. The power management chip according to claim 4, wherein, The drive control module also includes: A third transistor, wherein a first terminal is connected to the first voltage, a second terminal is connected to the control terminal of the first transistor, and the control terminal is connected to the first adjustment signal; and The fourth transistor has its first terminal connected to the control terminal of the second transistor, its second terminal connected to the second voltage, and its control terminal connected to the inverted signal of the first adjustment signal.

6. The power management chip according to claim 5, wherein, When the first adjustment signal is high, the first and second switches are turned on, and the third and fourth transistors are turned off. The first and second transistors are turned on non-overlapping according to the output of the buffer. When the first adjustment signal is low, the first switch and the second switch are turned off, the third transistor and the fourth transistor are turned on, and the first transistor and the second transistor are turned off.

7. The power management chip according to claim 5, wherein, The first transistor and the third transistor are P-channel transistors, and the second transistor and the fourth transistor are N-channel transistors.

8. The power management chip according to claim 2, wherein, The power supply voltage generation module includes: A first current source, a fifth transistor, a sixth transistor, and a first resistor are sequentially connected between the power supply voltage and the ground voltage, wherein the fifth transistor and the sixth transistor are respectively connected as MOS diodes; A seventh transistor and a second current source are sequentially connected between the power supply voltage and the ground voltage. The control terminal of the seventh transistor is connected to the second terminal of the first current source, and the second terminal of the seventh transistor is used to output the power supply voltage. An inverter, the input of which is used to receive the second adjustment signal; and An eighth transistor is connected in parallel with the sixth transistor, and the control terminal of the eighth transistor is connected to the output terminal of the inverter.

9. The power management chip according to claim 2, wherein, The trigger module is a Schmitt trigger.

10. The power management chip according to claim 8, wherein, The ground voltage is the noise ground inside the chip.

11. The power management chip according to claim 1, wherein, Also includes: The power circuit includes at least one of the power switches and an inductor, wherein the power switch is used to regulate the power transfer from the input terminal to the output terminal of the power management chip to provide a stable output voltage; A logic control circuit is used to receive the adjustment parameters input from the I2C interface circuit and convert them into parameter information that the switch controller can implement; and The switch controller is used to generate the corresponding switch signal based on the parameter information.

12. The power management chip according to claim 11, wherein, The adjustment signals for the drive rate of the drive circuit and / or the power supply voltage of the I2C interface circuit can come from external adjustment signals or from the logic control circuit.

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