High-voltage cross double-sampling circuit, analog-to-digital converter and battery management system

Abstract

The application provides a high-voltage cross double sampling circuit, an analog-to-digital converter and a battery management system, wherein the high-voltage cross double sampling circuit comprises a switched capacitor module, an enable control module and a capacitor initial setting module; after the switched capacitor module is turned on, the high-voltage signal and the low-voltage signal are cross double sampled through switch switching; the enable control module is connected with the switched capacitor module and is used for turning on the switched capacitor module when an enable signal is valid; and the capacitor initial setting module is connected with the switched capacitor module and is used for setting the initial state of each capacitor in the switched capacitor module when the enable signal is invalid. The application solves the problem of low battery voltage detection speed of the existing high-voltage sampling circuit.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design technology, and in particular relates to a high-voltage cross-dual sampling circuit, an analog-to-digital converter, and a battery management system. Background Technology

[0002] Battery management systems (BMS) battery packs consist of multiple cell units connected in series. The voltage values ​​at the positive and negative terminals of each cell are sequentially increased to a higher voltage as the pack is stacked. Therefore, high-voltage sampling circuits are typically used for battery voltage detection. However, due to limitations in device manufacturing processes, high-voltage sampling circuits often operate at relatively low frequencies, limiting the battery voltage detection speed. To improve the detection speed, the current conventional approach is to use multiple circuits to perform voltage measurements in parallel, but this significantly increases circuit area and power consumption. Therefore, how to improve the detection speed without significantly increasing circuit area and power consumption is a pressing technical problem that those skilled in the art wish to solve.

[0003] It should be noted that the above description of the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of the present invention and facilitating understanding by those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because they have been described in the background section of this invention. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a high-voltage cross dual sampling circuit, an analog-to-digital converter, and a battery management system to solve the problem of low battery voltage detection speed in existing high-voltage sampling circuits.

[0005] To achieve the above and other related objectives, the present invention provides a high-voltage cross-dual sampling circuit, the high-voltage cross-dual sampling circuit comprising:

[0006] Switched capacitor module, enable control module and capacitor initialization module;

[0007] After the switched capacitor module is turned on, it performs cross-sampling of high voltage and low voltage signals by switching.

[0008] The enable control module is connected to the switched capacitor module and is used to turn on the switched capacitor module when the enable signal is valid.

[0009] The capacitor initialization module is connected to the switched capacitor module and is used to set the initial state of each capacitor in the switched capacitor module when the enable signal is invalid.

[0010] Optionally, the switched capacitor module includes a switching control unit and a switched capacitor unit;

[0011] The switch control unit is used to generate four control signals based on a set of non-overlapping clock signals;

[0012] The switched capacitor unit is connected to the switch control unit and is used to perform cross-sampling of the high voltage signal and the low voltage signal by switching under the control of various control signals.

[0013] Optionally, the switch control unit includes a first inverter, a second inverter, a third inverter, and a fourth inverter. The input terminal of the first inverter is connected to a first clock signal, the output terminal of the first inverter is connected to the input terminal of the second inverter and outputs a fourth control signal, the output terminal of the second inverter outputs a first control signal, the input terminal of the third inverter is connected to a second clock signal, the output terminal of the third inverter is connected to the input terminal of the fourth inverter and outputs a second control signal, and the output terminal of the fourth inverter outputs a third control signal. The first clock signal and the second clock signal are a set of non-overlapping clock signals.

[0014] Optionally, the switched capacitor unit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor. The gate of the first NMOS transistor is connected to the gate of the second NMOS transistor and to the drain of the third NMOS transistor. The gate of the third NMOS transistor is connected to the gate of the fourth NMOS transistor and to the drain of the second NMOS transistor. The gate of the first PMOS transistor is connected to the gate of the second PMOS transistor and to the drain of the third PMOS transistor. The gate of the third PMOS transistor is connected to the gate of the fourth PMOS transistor and to the drain of the second PMOS transistor. The source of the first NMOS transistor, the source of the second NMOS transistor, and the third NMOS transistor... The source of the first PMOS transistor and the source of the fourth NMOS transistor are connected to each other and serve as the low-voltage input terminal of the switched capacitor module. The sources of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor are connected to each other and serve as the high-voltage input terminal of the switched capacitor module. The drain of the first NMOS transistor is connected to the drain of the first PMOS transistor and serves as the first output terminal of the switched capacitor module. The drain of the second NMOS transistor is connected to the first control signal via the first capacitor. The drain of the second PMOS transistor is connected to the second control signal via the second capacitor. The drain of the third NMOS transistor is connected to the third control signal via the third capacitor. The drain of the third PMOS transistor is connected to the fourth control signal via the fourth capacitor. The drain of the fourth NMOS transistor is connected to the drain of the fourth PMOS transistor and serves as the second output terminal of the switched capacitor module.

[0015] Optionally, the enable control module includes two input enable units and / or two output enable units. The two input enable units are respectively connected to the two input terminals of the switched capacitor module, and the two output enable units are respectively connected to the two output terminals of the switched capacitor module. They are used to pull down the two input terminals and / or two output terminals of the switched capacitor module when the enable signal is invalid, and to turn on the switched capacitor module when the enable signal is valid.

[0016] Optionally, when the enable control module includes an input enable unit, the input enable unit includes a fifth NMOS transistor, wherein the gate of the fifth NMOS transistor is connected to the inverted signal of the enable signal, the drain of the fifth NMOS transistor is connected to the low-voltage input terminal or the high-voltage input terminal of the switched capacitor module, and the source of the fifth NMOS transistor is connected to a reference ground; when the enable control module includes an output enable unit, the output enable unit includes a sixth NMOS transistor, wherein the gate of the sixth NMOS transistor is connected to the inverted signal of the enable signal, the drain of the sixth NMOS transistor is connected to the first output terminal or the second output terminal of the switched capacitor module, and the source of the sixth NMOS transistor is connected to a reference ground.

[0017] Optionally, the capacitor initialization module includes two N-side capacitor initialization units and two P-side capacitor initialization units. The two N-side capacitor initialization units are respectively connected to the first capacitor and the third capacitor located on the NMOS side in the switched capacitor module, and the two P-side capacitor initialization units are respectively connected to the second capacitor and the fourth capacitor located on the PMOS side in the switched capacitor module. This is used to set the initial state of the corresponding capacitor by discharging the first capacitor and the second capacitor when the enable signal is invalid, and to set the initial state of the corresponding capacitor by charging the third capacitor and the fourth capacitor.

[0018] Optionally, the N-side capacitor initial setting unit includes a seventh NMOS transistor, wherein the gate of the seventh NMOS transistor is connected to the inverted signal of the enable signal, the drain of the seventh NMOS transistor is connected to the first capacitor or the third capacitor, and the source of the seventh NMOS transistor is connected to the reference ground.

[0019] Optionally, the P-side capacitor initial setting unit includes an eighth NMOS transistor and a diode, wherein the gate of the eighth NMOS transistor is connected to the inverted signal of the enable signal, the drain of the eighth NMOS transistor is connected to the second capacitor or the fourth capacitor, the source of the eighth NMOS transistor is connected to the anode of the diode, and the cathode of the diode is connected to the reference ground.

[0020] Optionally, the high-voltage cross-dual sampling circuit further includes a clamping acceleration module connected to the switched capacitor module, used to quickly pull up the gate voltage of the PMOS transistor in the switched capacitor module after the switched capacitor module is turned on, and to clamp and protect the gate-source voltage of the PMOS transistor in the switched capacitor module.

[0021] Optionally, when the switched capacitor module includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor, the clamping acceleration module includes a first clamping transistor and a second clamping transistor. The anode of the first clamping transistor is connected to the gate of the first PMOS transistor and the gate of the second PMOS transistor, the cathode of the first clamping transistor is connected to the source of the first PMOS transistor and the source of the second PMOS transistor, the anode of the second clamping transistor is connected to the gate of the third PMOS transistor and the gate of the fourth PMOS transistor, and the cathode of the second clamping transistor is connected to the source of the third PMOS transistor and the source of the fourth PMOS transistor.

[0022] The present invention also provides an analog-to-digital converter, the analog-to-digital converter including the high-voltage cross-dual sampling circuit as described in any of the above claims.

[0023] Optionally, the analog-to-digital converter includes a Σ-Δ analog-to-digital converter.

[0024] The present invention also provides a battery management system, the battery management system including the analog-to-digital converter as described above.

[0025] As described above, the high-voltage cross-dual sampling circuit, analog-to-digital converter, and battery management system of the present invention perform cross-dual sampling of high-voltage and low-voltage signals through a switched capacitor module and utilize charge pump control voltage technology to improve signal sampling speed. Through the design of the enable control module and capacitor initialization module, the capacitors are initially set when the switched capacitor module is not turned on, thereby improving circuit reliability. Through the design of the clamping acceleration module, not only can high-voltage devices be protected, but circuit setup can also be accelerated, which helps to further improve the signal sampling speed. Attached Figure Description

[0026] Figure 1 The diagram shown is a schematic of the high-voltage cross-dual sampling circuit in Embodiment 1 of the present invention.

[0027] Figure 2 The diagram shows the relevant signal waveforms of the high-voltage cross-dual sampling circuit in Embodiment 1 of the present invention.

[0028] Figure 3 The diagram shown is a schematic diagram of the analog-to-digital converter in Embodiment 2 of the present invention.

[0029] Component designation explanation

[0030] 10 Analog-to-Digital Converters

[0031] 100 High-voltage cross-dual sampling circuit

[0032] 110 Switched Capacitor Module

[0033] 111 Switch Control Unit

[0034] 112 Switched Capacitor Unit

[0035] 120 Enable Control Module

[0036] 121 Input Enable Unit

[0037] 122 Output Enable Unit

[0038] 123 Signal Providing Unit

[0039] 130 Capacitor Initial Design Module

[0040] 131 N-channel capacitor initial design unit

[0041] 132 P-side capacitor initial design unit

[0042] 140 Clamping Acceleration Module

[0043] 100' First-stage high-voltage sampling circuit

[0044] 200' First-stage integrator circuit

[0045] 300' First-stage feedback circuit

[0046] 400' Second-stage low-voltage sampling circuit

[0047] 500' Second-stage integrator circuit

[0048] 600' Second-stage feedback circuit

[0049] 700' comparator circuit Detailed Implementation

[0050] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0051] Please see Figures 1 to 3 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the shape, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0052] Example 1

[0053] like Figure 1 As shown, this embodiment provides a high-voltage cross-dual sampling circuit 100, including a switched capacitor module 110, an enable control module 120, and a capacitor initialization module 130. Furthermore, it also includes a clamping acceleration module 140.

[0054] After the switched capacitor module 110 is turned on, it performs cross-sampling of the high voltage signal VH and the low voltage signal VL by switching, thereby realizing signal detection. The switched capacitor module 110 uses charge pump control voltage technology to realize fast and direct signal detection, which is beneficial to improving the signal detection speed.

[0055] In one implementation, such as Figure 1 As shown, the switched capacitor module 110 includes a switch control unit 111 and a switched capacitor unit 112.

[0056] The switch control unit 111 is used to generate four control signals based on a set of non-overlapping clock signals. As an example, such as... Figure 1 As shown, the switch control unit 111 includes a first inverter INV1, a second inverter INV2, a third inverter INV3, and a fourth inverter INV4. The input terminal of the first inverter INV1 is connected to a first clock signal PH1. The output terminal of the first inverter INV1 is connected to the input terminal of the second inverter INV2 and outputs a fourth control signal CL4. The output terminal of the second inverter INV2 outputs the first control signal CL1. The input terminal of the third inverter INV3 is connected to a second clock signal PH2. The output terminal of the third inverter INV3 is connected to the input terminal of the fourth inverter INV4 and outputs a second control signal CL2. The output terminal of the fourth inverter INV4 outputs a third control signal CL3. In the example above, the first clock signal PH1 and the second clock signal PH2 are a set of non-overlapping clock signals. The first control signal CL1 is the same as the first clock signal PH1, the second control signal CL2 is the opposite of the second clock signal PH2, the third control signal CL3 is the same as the second clock signal PH2, and the fourth control signal CL4 is the opposite of the first clock signal PH1. The waveforms of the above signals are as follows: Figure 2 As shown.

[0057] The switched capacitor unit 112 is connected to the switch control unit 111 and is used to perform cross-sampling of the high-voltage signal VH and the low-voltage signal VL by switching under the control of various control signals. As an example, such as... Figure 1As shown, the switched capacitor unit 112 includes a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4; wherein, the gate of the first NMOS transistor NM1 is connected to the gate of the second NMOS transistor NM2 and is connected to the drain of the third NMOS transistor NM3, the gate of the third NMOS transistor NM3 is connected to the gate of the fourth NMOS transistor NM4 and is connected to the drain of the second NMOS transistor NM2, and the first PMOS transistor NM1... The gate of S-MOSFET PM1 is connected to the gate of the second PMOS transistor PM2 and to the drain of the third PMOS transistor PM3. The gate of the third PMOS transistor PM3 is connected to the gate of the fourth PMOS transistor PM4 and to the drain of the second PMOS transistor PM2. The sources of the first NMOS transistor NM1, the second NMOS transistor NM2, the third NMOS transistor NM3, and the fourth NMOS transistor NM4 are interconnected and serve as the low-voltage input terminal of the switched capacitor module 110 to receive the low-voltage signal VL. The sources of the first PMOS transistor PM1, the second PMOS transistor PM2, the third PMOS transistor PM3, and the fourth PMOS transistor PM4 are connected to each other. This connection serves as the high-voltage input terminal of the switched capacitor module 110 to receive the high-voltage signal VH. The drain of the first NMOS transistor NM1 is connected to the drain of the first PMOS transistor PM1 and serves as the first output terminal VSP of the switched capacitor module 110. The drain of the second NMOS transistor NM2 is connected to the first control signal CL1 via the first capacitor C1, that is, the drain of the second NMOS transistor NM2 is connected to the first terminal of the first capacitor C1, and the second terminal of the first capacitor C1 is connected to the first control signal CL1. The drain of the second PMOS transistor PM2 is connected to the second control signal CL2 via the second capacitor C2, that is, the drain of the second PMOS transistor PM2 is connected to the first terminal of the second capacitor C2, and the second capacitor C2... The second terminal of the third NMOS transistor NM3 is connected to the second control signal CL2. The drain of the third NMOS transistor NM3 is connected to the third control signal CL3 via the third capacitor C3. That is, the drain of the third NMOS transistor NM3 is connected to the first terminal of the third capacitor C3. The second terminal of the third capacitor C3 is connected to the third control signal CL3. The drain of the third PMOS transistor PM3 is connected to the fourth control signal CL4 via the fourth capacitor C4. That is, the drain of the third PMOS transistor PM3 is connected to the first terminal of the fourth capacitor C4. The second terminal of the fourth capacitor C4 is connected to the fourth control signal CL4. The drain of the fourth NMOS transistor NM4 is connected to the drain of the fourth PMOS transistor PM4 and serves as the second output terminal VSN of the switched capacitor module 110.

[0058] The enable control module 120 is connected to the switched capacitor module 110 and is used to turn on the switched capacitor module 110 when the enable signal EN is valid. By adding the enable control module 120, the switched capacitor module 110 is controlled to be turned on or off by the enable signal EN, so as to facilitate the setting of the initial state of each capacitor in the switched capacitor module 110, which is beneficial to the accurate switching of each MOS transistor (including each NMOS transistor and each PMOS transistor) in the switched capacitor module 110, thereby improving the reliability of the circuit.

[0059] In one embodiment, the enable control module 120 includes two input enable units 121; in another embodiment, the enable control module 120 includes two output enable units 122; in yet another embodiment, the enable control module 120 includes two input enable units 121 and two output enable units 122, such as... Figure 1 As shown.

[0060] When the enable control module 120 includes two input enable units 121, the two input enable units 121 are respectively connected to the two input terminals of the switched capacitor module 110. That is, one input enable unit 121 is connected to the low-voltage input terminal of the switched capacitor module 110, and the other input enable unit 121 is connected to the high-voltage input terminal of the switched capacitor module 110. This is used to pull down the two input terminals of the switched capacitor module 110 when the enable signal EN is invalid, and to turn on the switched capacitor module 110 when the enable signal EN is valid. As an example, such as... Figure 1 As shown, the input enable unit 121 includes a fifth NMOS transistor NM5; wherein, the gate of the fifth NMOS transistor NM5 is connected to the inverted signal ENB of the enable signal, the drain of the fifth NMOS transistor NM5 is connected to the low voltage input terminal or the high voltage input terminal of the switched capacitor module 110, and the source of the fifth NMOS transistor NM5 is connected to the reference ground.

[0061] When the enable control module 120 includes two output enable units 122, the two output enable units 122 are respectively connected to the two output terminals of the switched capacitor module 110. That is, one output enable unit 122 is connected to the first output terminal of the switched capacitor module 110, and the other output enable unit 122 is connected to the second output terminal of the switched capacitor module 110. This is used to pull down the two output terminals of the switched capacitor module 110 when the enable signal EN is invalid, and to turn on the switched capacitor module 110 when the enable signal EN is valid. As an example, such as... Figure 1 As shown, the output enable unit 122 includes a sixth NMOS transistor NM6; wherein, the gate of the sixth NMOS transistor NM6 is connected to the inverted signal ENB of the enable signal, the drain of the sixth NMOS transistor NM6 is connected to the first output terminal or the second output terminal of the switched capacitor module 110, and the source of the sixth NMOS transistor NM6 is connected to the reference ground.

[0062] In practical applications, the peripheral circuits connected to the high-voltage cross-dual sampling circuit 100 in this embodiment may contain low-voltage devices. In order to protect the low-voltage devices, the enable control module 120 is usually designed to include two input enable units 121 and two output enable units 122. In this way, when the enable signal EN is invalid, the input and output terminals of the switched capacitor module 110 are pulled low through the input enable unit 121 and the output enable unit 122, which can protect the low-voltage devices.

[0063] Additionally, the enable control module 120 also includes a signal providing unit 123 for providing an inverted enable signal ENB. As an example, the signal providing unit 123 includes a fifth inverter INV5; wherein the input terminal of the fifth inverter INV5 is connected to the enable signal EN, and the output terminal of the fifth inverter INV5 outputs the inverted enable signal ENB. It should be noted that, in addition to providing the inverted enable signal ENB to each enable unit, the signal providing unit 123 also provides the inverted enable signal ENB to the capacitor initialization module 130.

[0064] The capacitor initialization module 130 is connected to the switched capacitor module 110 and is used to set the initial state of each capacitor in the switched capacitor module 110 when the enable signal EN is invalid. Before the switched capacitor module 110 is turned on, the initial state of each capacitor is set. In this way, after the switched capacitor module 110 is turned on, each MOS transistor (including each NMOS transistor and each PMOS transistor) can accurately switch on and off, avoiding functional errors and improving circuit reliability.

[0065] In one implementation, such as Figure 1 As shown, the capacitor initialization module 130 includes two N-side capacitor initialization units 131 and two P-side capacitor initialization units 132.

[0066] Two N-side capacitor initialization units 131 are respectively connected to the first capacitor C1 and the third capacitor C3 located on the NMOS side of the switched capacitor module 100. That is, one N-side capacitor initialization unit 131 is connected to the first capacitor C1 in the switched capacitor module 110, and the other N-side capacitor initialization unit 131 is connected to the third capacitor C3 in the switched capacitor module 110. This is used to set the initial state of the two capacitors by discharging the first capacitor C1 and charging the third capacitor C3 when the enable signal EN is invalid. As an example, Figure 1As shown, the N-side capacitor initial setting unit 131 includes a seventh NMOS transistor NM7; wherein, the gate of the seventh NMOS transistor NM7 is connected to the inverted signal ENB of the enable signal, the drain of the seventh NMOS transistor NM7 is connected to the first capacitor C1 or the third capacitor C3 (for example, connected to the first terminal of the first capacitor C1 or the first terminal of the third capacitor C3), and the source of the seventh NMOS transistor NM7 is connected to the reference ground.

[0067] Two P-side capacitor initialization units 132 are respectively connected to the second capacitor C2 and the fourth capacitor C4 located on the PMOS side of the switched capacitor module 110. That is, one P-side capacitor initialization unit 132 is connected to the second capacitor C2 in the switched capacitor module 110, and the other P-side capacitor initialization unit 132 is connected to the fourth capacitor C4 in the switched capacitor module 110. This is used to set the initial state of the two capacitors by discharging the second capacitor C2 and charging the fourth capacitor C4 when the enable signal EN is invalid. As an example, Figure 1 As shown, the P-side capacitor initial setting unit 132 includes an eighth NMOS transistor NM8 and a diode D. The gate of the eighth NMOS transistor NM8 is connected to the inverted signal ENB of the enable signal, the drain of the eighth NMOS transistor NM8 is connected to the second capacitor C2 or the fourth capacitor C4 (for example, connected to the first terminal of the second capacitor C2 or the first terminal of the fourth capacitor C4), the source of the eighth NMOS transistor NM8 is connected to the anode of the diode D, and the cathode of the diode D is connected to the reference ground. By adding a forward-conducting diode D on the source side of the eighth NMOS transistor NM8, the problem of the entire P-side capacitor initial setting unit 132 being turned on due to the negative voltage on the PMOS transistor side being turned on when the enable signal EN is valid but the inverted signal ENB of the enable signal is invalid can be avoided.

[0068] The clamping acceleration module 140 is connected to the switched capacitor module 110 and is used to quickly pull up the gate voltage of the PMOS transistors in the switched capacitor module 110 after the switched capacitor module 110 is turned on, and to clamp and protect the gate-source voltage of the PMOS transistors in the switched capacitor module 110. Through the design of the clamping acceleration module 140, not only is the gate-source voltage of each PMOS transistor clamped and protected, but also the gate voltage of each PMOS transistor can be quickly pulled up after the switched capacitor module 110 is turned on, which can speed up the circuit setup and help to further improve the signal detection speed.

[0069] In one implementation, such as Figure 1As shown, the clamping acceleration module 140 includes a first clamping transistor Z1 and a second clamping transistor Z2; wherein, the anode of the first clamping transistor Z1 is connected to the gate of the first PMOS transistor PM1 and the gate of the second PMOS transistor PM2, the cathode of the first clamping transistor Z1 is connected to the source of the first PMOS transistor PM1 and the source of the second PMOS transistor PM2, the anode of the second clamping transistor Z2 is connected to the gate of the third PMOS transistor PM3 and the gate of the fourth PMOS transistor PM4, and the cathode of the second clamping transistor Z2 is connected to the source of the third PMOS transistor PM3 and the source of the fourth PMOS transistor PM4.

[0070] It should be noted that all MOS transistors (including all NMOS transistors and all PMOS transistors) in this embodiment are fabricated using high-voltage processes, such as LDMOS (Laterally Diffused Metal-Oxide Semiconductor) processes. Of course, other high-voltage processes can also be used, and this embodiment does not limit this.

[0071] Please refer to the following. Figure 1 and Figure 2 The working principle of the high-voltage double-cross sampling circuit 100 in this embodiment will be explained in detail.

[0072] When the enable signal EN = 0 and its inverted signal ENB = 1, the first clock signal PH1 = 0, the second clock signal PH2 = 1, the first control signal CL1 = 0, the second control signal CL2 = 0, the third control signal CL3 = 1, and the fourth control signal CL4 = 1. At this time:

[0073] In the enable control module 120, the fifth NMOS transistor NM5 in the input enable unit 121 is turned on, pulling the two input terminals of the switched capacitor module 110 low, and the sixth NMOS transistor NM6 in the output enable unit 122 is turned on, pulling the two output terminals of the switched capacitor module 110 low. Thus, the switched capacitor module 110 is turned off.

[0074] In the capacitor initialization module 130, the seventh NMOS transistor NM7 in the N-side capacitor initialization unit 131 is turned on. Since CL1 = 0 and CL3 = 1, the initial state of the first capacitor C1 is set to a low potential (e.g., zero potential), and the initial state of the third capacitor C3 is set to a high potential (e.g., 4.5V power supply potential). The eighth NMOS transistor NM8 in the P-side capacitor initialization unit 132 is turned on. Since CL2 = 0 and CL4 = 1, the initial state of the second capacitor C2 is set to a low potential (e.g., zero potential), and the initial state of the fourth capacitor C4 is set to a high potential (e.g., 4.5V power supply potential). In this way, the initial state of each capacitor is set.

[0075] When the enable signal EN = 1 and the inverted signal ENB = 0:

[0076] In the enable control module 120, the fifth NMOS transistor NM5 in the input enable unit 121 is turned off, the sixth NMOS transistor NM6 in the output enable unit 122 is turned off, and the switched capacitor module 110 is turned on.

[0077] In the capacitor initial setting module 130, the seventh NMOS transistor NM7 in the N-side capacitor initial setting unit 131 is turned off, and the eighth NMOS transistor NM8 in the P-side capacitor initial setting unit 132 is turned off, thus ending the setting of the initial state of each capacitor.

[0078] In switched capacitor module 110:

[0079] When PH1 = 1 and PH2 = 0, CL1 = CL2 = 1, CL3 = CL4 = 0; for the third NMOS transistor NM3 and the fourth NMOS transistor NM4, the gate-source voltage satisfies the formula: Then the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are turned on, transmitting the low-voltage signal VL to the second output terminal VSN, that is, VSN = VL; for the first PMOS transistor PM1 and the second PMOS transistor PM2, the gate-source voltage satisfies the formula: Then the first PMOS transistor PM1 and the second PMOS transistor PM2 are turned on, transmitting the high voltage signal VH to the first output terminal VSP, that is, VSP = VH;

[0080] Wherein, Vgs_nm3 is the gate-source voltage of the third NMOS transistor NM3, Vgs_nm4 is the gate-source voltage of the fourth NMOS transistor NM4, Ccs is the charge pump exchange capacitor and Ccs=C1=C2=C3=C4, VDD is the power supply for each inverter, its typical value is 5V, Cg_nm3 is the gate parasitic capacitance of the third NMOS transistor NM3, Cg_nm4 is the gate parasitic capacitance of the fourth NMOS transistor NM4, Cd_nm2 is the drain parasitic capacitance of the second NMOS transistor NM2, Vgs_pm1 is the gate-source voltage of the first PMOS transistor PM1, Vgs_pm2 is the gate-source voltage of the second PMOS transistor PM2, Cg_pm1 is the gate parasitic capacitance of the first PMOS transistor PM1, Cg_pm2 is the gate parasitic capacitance of the second PMOS transistor PM2, and Cd_pm3 is the drain parasitic capacitance of the third PMOS transistor PM3;

[0081] When PH1 = 0 and PH2 = 1, CL1 = CL2 = 0, CL3 = CL4 = 1; similarly, the first NMOS transistor NM1 and the second NMOS transistor NM2 are turned on, transmitting the low-voltage signal VL to the first output terminal VSP, that is, VSP = VL; the third PMOS transistor PM3 and the fourth PMOS transistor PM4 are turned on, transmitting the high-voltage signal VH to the second output terminal VSN, that is, VSN = VH;

[0082] Thus, under the control of the first clock signal PH1 and the second clock signal PH2, the relevant NMOS transistors and relevant PMOS transistors are alternately turned on and off, so that the high voltage signal VH is transmitted to the first output terminal VSP in the PH1 phase and to the second output terminal VSN in the PH2 phase, and the low voltage signal VL is transmitted to the second output terminal VSN in the PH1 phase and to the first output terminal VSP in the PH2 phase, thereby reliably and quickly establishing and stably and accurately sampling the signal.

[0083] In the clamping acceleration module 140, the first clamping transistor Z1 accelerates the conduction of the first PMOS transistor PM1 and the second PMOS transistor PM2 by rapidly increasing their gate voltages, thereby enabling the rapid establishment of the circuit. It also clamps the gate-source voltages of the first PMOS transistor PM1 and the second PMOS transistor PM2 to protect the device. The second clamping transistor Z2 accelerates the conduction of the third PMOS transistor PM3 and the fourth PMOS transistor PM4 by rapidly increasing their gate voltages, thereby enabling the rapid establishment of the circuit. It also clamps the gate-source voltages of the third PMOS transistor PM3 and the fourth PMOS transistor PM4 to protect the device.

[0084] Example 2

[0085] like Figure 3 As shown, this embodiment provides an analog-to-digital converter 10, including a high-voltage cross-dual sampling circuit 100. Of course, it may also include other functional circuits, which are not limited thereto. The high-voltage cross-dual sampling circuit 100 is implemented using the circuit structure described in Embodiment 1. The analog-to-digital converter 10 implemented based on the high-voltage cross-dual sampling circuit 100 can be reliably applied to systems with faster sampling speeds, such as vehicle-rail battery management systems.

[0086] In one embodiment, the analog-to-digital converter 10 includes a Σ-Δ analog-to-digital converter. Taking a second-order incremental Σ-Δ analog-to-digital converter as an example, the specific structure of the analog-to-digital converter 10 is shown in the figure, including a first-stage high-voltage sampling circuit 100', a first-stage integrator circuit 200', a first-stage feedback circuit 300', a second-stage low-voltage sampling circuit 400', a second-stage integrator circuit 500', a second-stage feedback circuit 600', and a comparator circuit 700'. The first-stage high-voltage sampling circuit 100', the first-stage integrator circuit 200', and the first-stage feedback circuit 300' constitute the first stage, while the second-stage low-voltage sampling circuit 400', the second-stage integrator circuit 500', and the second-stage feedback circuit 600' constitute the second stage. 'Constitutes the second stage; in the above example, the first stage high-voltage sampling circuit 100' is implemented using a high-voltage cross-dual sampling circuit 100, wherein the sampling capacitor Cs samples VH and VL onto its respective capacitor in phase Q1D, and samples VL and VH onto its respective capacitor in phase Q2D. Q1 and Q2 are non-overlapping clocks, Q1D is the delayed phase of Q1, corresponding to the first clock signal PH1 in the high-voltage cross-dual sampling circuit 100, and Q2D is the delayed phase of Q2, corresponding to the second clock signal PH2 in the high-voltage cross-dual sampling circuit 100. In addition, the design of the delayed phase is mainly to reduce the influence of charge injection.

[0087] Example 3

[0088] This embodiment provides a battery management system, including an analog-to-digital converter 10, wherein the analog-to-digital converter 10 is implemented using the structure described in Embodiment 2; of course, the battery management system may also include other parts, such as a battery pack, a comparator, a controller, etc., and this embodiment does not limit this.

[0089] In summary, the high-voltage cross-dual sampling circuit, analog-to-digital converter, and battery management system of this invention perform cross-dual sampling of high-voltage and low-voltage signals through a switched-capacitor module, and utilize charge pump control voltage technology to improve signal sampling speed. Through the design of the enable control module and capacitor initialization module, the capacitors are initially set when the switched-capacitor module is not enabled, improving circuit reliability. The clamping acceleration module not only protects high-voltage devices but also accelerates circuit setup, further contributing to improved signal sampling speed. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0090] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A high voltage cross double sampling circuit, characterized by, The high-voltage cross-dual sampling circuit includes: Switched capacitor module, enable control module and capacitor initialization module; After the switched capacitor module is turned on, it performs cross-sampling of high voltage and low voltage signals by switching. The enable control module is connected to the switched capacitor module and is used to turn on the switched capacitor module when the enable signal is valid. The capacitor initialization module is connected to the switched capacitor module and is used to set the initial state of each capacitor in the switched capacitor module when the enable signal is invalid.

2. The high-voltage cross double-sampling circuit of claim 1, wherein, The switched capacitor module includes a switch control unit and a switched capacitor unit; The switch control unit is used to generate four control signals based on a set of non-overlapping clock signals; The switched capacitor unit is connected to the switch control unit and is used to perform cross-sampling of the high voltage signal and the low voltage signal by switching under the control of various control signals.

3. The high-voltage cross double-sampling circuit of claim 2, wherein, The switch control unit includes a first inverter, a second inverter, a third inverter, and a fourth inverter. The input terminal of the first inverter is connected to a first clock signal, and the output terminal of the first inverter is connected to the input terminal of the second inverter and outputs a fourth control signal. The output terminal of the second inverter outputs a first control signal. The input terminal of the third inverter is connected to a second clock signal, and the output terminal of the third inverter is connected to the input terminal of the fourth inverter and outputs a second control signal. The output terminal of the fourth inverter outputs a third control signal. The first clock signal and the second clock signal are a set of non-overlapping clock signals.

4. The high-voltage cross double-sampling circuit of claim 2, wherein, The switched capacitor unit includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor. The gate of the first NMOS transistor is connected to the gate of the second NMOS transistor and to the drain of the third NMOS transistor. The gate of the third NMOS transistor is connected to the gate of the fourth NMOS transistor and to the drain of the second NMOS transistor. The gate of the first PMOS transistor is connected to the gate of the second PMOS transistor and to the drain of the third PMOS transistor. The gate of the third PMOS transistor is connected to the gate of the fourth PMOS transistor and to the drain of the second PMOS transistor. The source of the first NMOS transistor, the source of the second NMOS transistor, and the source of the third NMOS transistor are all connected to the source of the second NMOS transistor. The source of the first PMOS transistor and the source of the fourth NMOS transistor are connected to each other and serve as the low-voltage input terminal of the switched capacitor module. The sources of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor are connected to each other and serve as the high-voltage input terminal of the switched capacitor module. The drain of the first NMOS transistor is connected to the drain of the first PMOS transistor and serves as the first output terminal of the switched capacitor module. The drain of the second NMOS transistor is connected to the first control signal via the first capacitor. The drain of the second PMOS transistor is connected to the second control signal via the second capacitor. The drain of the third NMOS transistor is connected to the third control signal via the third capacitor. The drain of the third PMOS transistor is connected to the fourth control signal via the fourth capacitor. The drain of the fourth NMOS transistor is connected to the drain of the fourth PMOS transistor and serves as the second output terminal of the switched capacitor module.

5. The high-voltage cross double-sampling circuit of claim 1, wherein, The enable control module includes two input enable units and / or two output enable units. The two input enable units are respectively connected to the two input terminals of the switched capacitor module, and the two output enable units are respectively connected to the two output terminals of the switched capacitor module. The module is used to pull down the two input terminals and / or two output terminals of the switched capacitor module when the enable signal is invalid, and to turn on the switched capacitor module when the enable signal is valid.

6. The high-voltage cross double-sampling circuit of claim 5, wherein, When the enable control module includes an input enable unit, the input enable unit includes a fifth NMOS transistor, wherein the gate of the fifth NMOS transistor is connected to the inverted signal of the enable signal, the drain of the fifth NMOS transistor is connected to the low-voltage input terminal or the high-voltage input terminal of the switched capacitor module, and the source of the fifth NMOS transistor is connected to a reference ground; when the enable control module includes an output enable unit, the output enable unit includes a sixth NMOS transistor, wherein the gate of the sixth NMOS transistor is connected to the inverted signal of the enable signal, the drain of the sixth NMOS transistor is connected to the first output terminal or the second output terminal of the switched capacitor module, and the source of the sixth NMOS transistor is connected to a reference ground.

7. The high-voltage cross double-sampling circuit of claim 1, wherein, The capacitor initialization module includes two N-side capacitor initialization units and two P-side capacitor initialization units. The two N-side capacitor initialization units are respectively connected to the first and third capacitors located on the NMOS side of the switched capacitor module, and the two P-side capacitor initialization units are respectively connected to the second and fourth capacitors located on the PMOS side of the switched capacitor module. When the enable signal is invalid, the module is used to set the initial state of the corresponding capacitor by discharging the first and second capacitors, and by charging the third and fourth capacitors.

8. The high-voltage cross double-sampling circuit of claim 7, wherein, The N-side capacitor initial setting unit includes a seventh NMOS transistor, wherein the gate of the seventh NMOS transistor is connected to the inverted signal of the enable signal, the drain of the seventh NMOS transistor is connected to the first capacitor or the third capacitor, and the source of the seventh NMOS transistor is connected to the reference ground.

9. The high-voltage cross double-sampling circuit of claim 7, wherein, The P-side capacitor initial setting unit includes an eighth NMOS transistor and a diode. The gate of the eighth NMOS transistor is connected to the inverted signal of the enable signal, the drain of the eighth NMOS transistor is connected to the second capacitor or the fourth capacitor, the source of the eighth NMOS transistor is connected to the anode of the diode, and the cathode of the diode is connected to the reference ground.

10. The high-voltage cross double sampling circuit according to any one of claims 1 to 9, characterized by, The high-voltage cross-dual sampling circuit also includes a clamping acceleration module connected to the switched capacitor module. This module is used to quickly increase the gate voltage of the PMOS transistor in the switched capacitor module after the switched capacitor module is turned on, and to clamp and protect the gate-source voltage of the PMOS transistor in the switched capacitor module.

11. The high-voltage cross double-sampling circuit of claim 10, wherein, When the switched capacitor module includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor, the clamping acceleration module includes a first clamping transistor and a second clamping transistor. The anode of the first clamping transistor is connected to the gate of the first PMOS transistor and the gate of the second PMOS transistor, the cathode of the first clamping transistor is connected to the source of the first PMOS transistor and the source of the second PMOS transistor, the anode of the second clamping transistor is connected to the gate of the third PMOS transistor and the gate of the fourth PMOS transistor, and the cathode of the second clamping transistor is connected to the source of the third PMOS transistor and the source of the fourth PMOS transistor.

12. An analog-to-digital converter, characterized by The analog-to-digital converter includes a high-voltage cross-dual sampling circuit as described in any one of claims 1 to 11.

13. The analog-to-digital converter of claim 12, wherein, The analog-to-digital converter includes a Σ-Δ analog-to-digital converter.

14. A battery management system, characterized by, The battery management system includes the analog-to-digital converter as described in claim 12 or 13.

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