A pre-stabilization circuit, a PCB board and a controller

Abstract

The application discloses a pre-stabilization circuit, a PCB and a controller, comprising a start bias unit, a pre-stabilization unit, an enable control unit, a high-voltage bandgap reference unit and an output buffer unit. The start bias unit can provide forced start at the moment of power-on, ensure the circuit to get rid of the degenerate point and establish stable bias, and automatically exit after the start is completed. The pre-stabilization unit generates two signals based on the bias: one is a driving signal suitable for high-voltage LDMOS, which improves the high-voltage adaptability of the circuit; the other is a control signal of the reference circuit, which is used for enable management. The enable control unit selects the control signal through an external signal, realizes work mode control, and cuts off the bias to reduce static power consumption when it is turned off. The high-voltage bandgap reference unit starts after obtaining the driving and bias, uses internal temperature compensation and closed-loop adjustment mechanism to output low-drift reference voltage. The output buffer unit enhances the load capacity of the reference voltage, and forms a global closed loop through feedback.

Description

Technical Field

[0001] This invention relates to the field of pre-regulated voltage circuit technology, and particularly to a pre-regulated voltage circuit, PCB board and controller. Background Technology

[0002] The analog circuits inside the chip (such as reference voltage sources, oscillators, PLLs, etc.) require a certain settling time after power-on before they can output stable operating signals. Before these analog modules reach a stable state, operations performed by digital logic that rely on such signals are invalid or even erroneous. Therefore, a pre-regulator circuit is needed to provide a stable power supply and reference for the internal modules in advance. Traditional pre-regulator circuits often use simple current source biasing, diode-connected MOSFET voltage divider, and source follower output structures. However, such pre-regulator circuits have poor adaptability to high voltage and cannot meet the gate drive requirements of high-voltage LDMOS power transistors.

[0003] It is evident that existing technologies still need improvement and enhancement. Summary of the Invention

[0004] In view of the shortcomings of the prior art, the purpose of this invention is to provide a pre-regulated circuit that provides a pre-established and stable operating bias for analog modules such as high-voltage bandgap references inside the chip, so that they can quickly reach a stable state after power-on, thereby ensuring the reliable operation of subsequent digital logic.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: A pre-regulator circuit includes a startup bias unit, a pre-regulator unit, an enable control unit, a high-voltage bandgap reference unit, and an output buffer unit. The input terminal of the startup bias unit is connected to an external high-voltage power supply. The input terminal of the pre-regulator unit is connected to both the output terminal of the startup bias unit and the external high-voltage power supply. The pre-regulator unit has a first output terminal and a second output terminal. The first output terminal of the pre-regulator unit is connected to the input terminal of the high-voltage bandgap reference unit via the enable control unit. The enable control unit is also connected to an external enable signal terminal. The second output terminal of the pre-regulator unit is connected to the input terminal of the high-voltage bandgap reference unit. The output terminal of the high-voltage bandgap reference unit is connected to the input terminal of the output buffer unit. The output sampling node of the unit is connected to the input terminal of the high-voltage bandgap reference unit; the start-up bias unit is used to provide bias current to the pre-regulation unit according to the high-voltage signal from the external high-voltage power supply terminal; the pre-regulation unit is used to generate a control signal for controlling the bias switching of the high-voltage bandgap reference unit and a drive signal for the LDMOS regulating transistor adapted to the high-voltage bandgap reference unit according to the bias current; the enable control unit is used to adjust the connection state between the control signal and the high-voltage bandgap reference unit according to the signal from the external enable signal terminal; the high-voltage bandgap reference unit is used to generate a reference voltage according to the control signal, the drive signal and the feedback signal from the output sampling node; the output buffer unit is used to improve the load-carrying capacity of the reference voltage output by the high-voltage bandgap reference unit.

[0006] In the aforementioned pre-regulatory circuit, the startup bias unit includes a power-on startup circuit and a reference current source circuit. The input terminals of the power-on startup circuit and the reference current source circuit are respectively connected to an external high-voltage power supply. The output terminal of the power-on startup circuit is connected to the enable terminal of the reference current source circuit, and the output terminal of the reference current source circuit is connected to the input terminal of the pre-regulatory unit. The power-on startup circuit is used to inject a forced startup current into the reference current source circuit at the moment of power-on of the external high-voltage power supply. The reference current source circuit is used to provide bias current for the pre-regulatory unit.

[0007] In the aforementioned pre-regulatory circuit, the power-on startup circuit includes a first field-effect transistor M1, a second field-effect transistor M2, a third field-effect transistor M3, and a voltage divider resistor network; the reference current source circuit includes a fourth field-effect transistor M4, a fifth field-effect transistor M5, a sixth field-effect transistor M6, a seventh field-effect transistor M7, an eighth field-effect transistor M8, a ninth field-effect transistor M9, a tenth field-effect transistor M10, an eleventh field-effect transistor M11, and a fifth resistor R5; the sources of the first field-effect transistor M1, the second field-effect transistor M2, and the third field-effect transistor M3 are connected to... An external high-voltage power supply is connected. The drain of the first field-effect transistor M1 is connected to one end of the voltage divider resistor network, and the other end of the voltage divider resistor network is grounded. The drain of the first field-effect transistor M1 is also shorted to its gate. The gate of the first field-effect transistor M1 is also connected to the drain of the second field-effect transistor M2 and the gate of the third field-effect transistor M3. The gate of the second field-effect transistor M2 is connected to the gate of the fourth field-effect transistor M4, the gate and drain of the fifth field-effect transistor M5, and the input terminal of the pre-regulator unit. The third field-effect transistor... The drain of transistor M3 is connected to the drain of the sixth field-effect transistor M6, the drain and gate of the eighth field-effect transistor M8, and the gate of the ninth field-effect transistor M9. The sources of the fourth field-effect transistor M4 and the fifth field-effect transistor M5 are connected to an external high-voltage power supply. The drain of the fourth field-effect transistor M4 is connected to the drain of the sixth field-effect transistor M6. The drain of the fifth field-effect transistor M5 is also connected to the source of the seventh field-effect transistor M7. The gate of the seventh field-effect transistor M7 is shorted to its drain. The drain of the seventh field-effect transistor M7 is also connected to the drain of the ninth field-effect transistor M9. The source of the eighth field-effect transistor M8 is connected to the drain and gate of the tenth field-effect transistor M10, the gate of the eleventh field-effect transistor M11, and the input of the pre-regulatory unit. The source of the tenth field-effect transistor M10 is grounded. The source of the eleventh field-effect transistor M11 is connected to one end of the fifth resistor R5, and the other end of the fifth resistor R5 is grounded.

[0008] In the aforementioned pre-regulatory circuit, the pre-regulatory unit includes a twelfth field-effect transistor (FET) M12, a thirteenth field-effect transistor (FET) M13, a fourteenth field-effect transistor (FET) M14, a fifteenth field-effect transistor (FET) M15, a sixteenth field-effect transistor (FET) M16, a seventeenth field-effect transistor (FET) M17, a sixth resistor R6, and a current switching section. The source of the twelfth field-effect transistor (FET) M12 is connected to an external high-voltage power supply terminal. The gate of the twelfth field-effect transistor (FET) M12 is connected to the gate of the second field-effect transistor (FET) M2. The drain of the twelfth field-effect transistor (FET) M12 is connected to the source of the thirteenth field-effect transistor (FET) M13. The gate of the thirteenth field-effect transistor (FET) M13 is connected to the gate of the seventh field-effect transistor (FET) M7. The drain of the thirteenth field-effect transistor (FET) M13 is connected to one end of the sixth resistor R6. The other end is connected to the source of the fourteenth field-effect transistor M14, the gate of the seventeenth field-effect transistor M17, and the input terminal of the high-voltage bandgap reference unit. The gate of the fourteenth field-effect transistor M14 is shorted to its drain. The drain of the fourteenth field-effect transistor M14 is also connected to the drain and gate of the fifteenth field-effect transistor M15. The source of the fifteenth field-effect transistor M15 is connected to the drain and gate of the sixteenth field-effect transistor M16. The source of the sixteenth field-effect transistor M16 is grounded. The source of the seventeenth field-effect transistor M17 is connected to an external high-voltage power supply terminal. The drain of the seventeenth field-effect transistor M17 is connected to the current switch section. The current switch section is also connected to the gate of the eleventh field-effect transistor M11 and the input terminal of the enable control unit.

[0009] In the pre-regulatory circuit, the current switching section includes an eighteenth field-effect transistor M18 and a nineteenth field-effect transistor M19. The drain of the eighteenth field-effect transistor M18 is connected to the drain of the seventeenth field-effect transistor M17, the source of the eighteenth field-effect transistor M18 is connected to the drain of the nineteenth field-effect transistor M19, the source of the nineteenth field-effect transistor M19 is grounded, and the gate of the eighteenth field-effect transistor M18 is connected to the gate of the eleventh field-effect transistor M11, the gate of the nineteenth field-effect transistor M19, and the input terminal of the enable control unit.

[0010] In the pre-regulator circuit, the enable control unit includes a twentieth field-effect transistor M20, a twenty-first field-effect transistor M21, a twenty-second field-effect transistor M22, and an inverter INV. The source of the twentieth field-effect transistor M20 is grounded, and the gate of the twentieth field-effect transistor M20 is connected to the gate of the eighteenth field-effect transistor M18. The drain of the twentieth field-effect transistor M20 is connected to the sources of the twenty-first field-effect transistor M21 and the twenty-second field-effect transistor M22. The gate of the twenty-first field-effect transistor M21 and the input terminal of the inverter INV are connected to an external enable signal terminal. The output terminal of the inverter INV is connected to the gate of the twenty-second field-effect transistor M22. The drain of the twenty-first field-effect transistor M21 is connected to the input terminal of the high-voltage bandgap reference unit, and the drain of the twenty-second field-effect transistor M22 is connected to the input terminals of the high-voltage bandgap reference unit and the output buffer unit, respectively.

[0011] In the aforementioned pre-regulatory circuit, the high-voltage bandgap reference unit includes the following transistors: the 23rd MOSFET M23, the 24th MOSFET M24, the 25th MOSFET M25, the 26th MOSFET M26, the 27th MOSFET M27, the 28th MOSFET M28, the 29th MOSFET M29, the 30th MOSFET M30, the 31st MOSFET M31, the 1st transistor NPN1, the 2nd transistor NPN2, the 3rd transistor NPN3, the 4th transistor NPN4, the 5th transistor NPN5, the 7th resistor R7, the 10th resistor R10, and the 11th resistor R11. The 23rd MOSFET M23, the 24th MOSFET M24, the 25th MOSFET M25, and the... The sources of the 26th field-effect transistor M26, the 27th field-effect transistor M27, and the 29th field-effect transistor M29 are connected to an external high-voltage power supply. The drain and gate of the 23rd field-effect transistor M23, the gate of the 24th field-effect transistor M24, the gate of the 25th field-effect transistor M25, and the drain of the 26th field-effect transistor M26 are respectively connected to the drain of the 21st field-effect transistor M21. The drain of the 24th field-effect transistor M24 is connected to the gate of the 26th field-effect transistor M26, the gate of the 27th field-effect transistor M27, the source of the 28th field-effect transistor M28, and the gate of the 29th field-effect transistor M29. The source of the 25th field-effect transistor M25... The drain, gate and drain of the 28th field-effect transistor M28, and gate of the 30th field-effect transistor M30 are connected to the drain of the 22nd field-effect transistor M22. The drain of the 29th field-effect transistor M29 is connected to the source of the 30th field-effect transistor M30. The drain of the 30th field-effect transistor M30 is connected to the collector of the 2nd transistor NPN2. The emitter of the 2nd transistor NPN2 is connected to the collector and base of the 1st transistor NPN1. The emitter of the 1st transistor NPN1 is grounded. The base of the 2nd transistor NPN2 is connected to the base of the 3rd transistor NPN3. The emitter of the 3rd transistor NPN3 is connected to the output terminal of the output buffer unit and the fourth... The base of transistor NPN4 is connected to the base of transistor NPN5. The collector of transistor NPN3 is connected to the source of field-effect transistor M31. The gate of field-effect transistor M31 is connected to the gate of field-effect transistor M17. The drain of field-effect transistor M31 is connected to one end of resistor R7. The other end of resistor R7 is connected to an external high-voltage power supply. The emitter of transistor NPN5 is connected to one end of resistor R10. The emitter of transistor NPN4 and the other end of resistor R10 are respectively connected to one end of resistor R11. The other end of resistor R11 is grounded.The collectors of the fourth transistor NPN4 and the fifth transistor NPN5 are respectively connected to the input terminals of the output buffer unit.

[0012] In the aforementioned pre-regulatory circuit, the output buffer unit includes a 32nd field-effect transistor (FET) M32, a 33rd field-effect transistor (FET) M33, a 34th field-effect transistor (FET) M34, a 35th field-effect transistor (FET) M35, a 36th field-effect transistor (FET) M36, a 37th field-effect transistor (FET) M37, an 8th resistor R8, a 9th resistor R9, a 12th resistor R12, and a 13th resistor R13. The sources of the 32nd, 33rd, and 36th FETs are connected to an external high-voltage power supply. The gate of the 32nd FET M32 is connected to its drain and the gate of the 33rd FET M33. The drain of the 32nd FET M32 is also connected to one end of the 8th resistor R8. The other end of the 8th resistor R8 is connected to the drain of the 34th FET M34. The source of the 34th FET M34 is connected to the collector of the 4th transistor NPN4. The 33rd field-effect transistor... The drain of field-effect transistor M33 is connected to one end of the ninth resistor R9 and the gate of the thirty-sixth field-effect transistor M36. The other end of the ninth resistor R9 is connected to the drain of the thirty-fifth field-effect transistor M35. The source of the thirty-fifth field-effect transistor M35 is connected to the collector of the fifth transistor NPN5. The gates of the thirty-fourth field-effect transistor M34 and the thirty-fifth field-effect transistor M35 are connected to the gate of the seventeenth field-effect transistor M17. The drain of the thirty-sixth field-effect transistor M36 is connected to the source of the thirty-seventh field-effect transistor M37. The gate of the thirty-seventh field-effect transistor M37 is connected to the drain of the twenty-second field-effect transistor M22. The drain of the thirty-seventh field-effect transistor M37 is connected to one end of the twelfth resistor R12. The other end of the twelfth resistor R12 is connected to the emitter of the third transistor NPN3 and one end of the thirteenth resistor R13. The other end of the thirteenth resistor R13 is grounded.

[0013] This application also provides a PCB board printed with the pre-regulator circuit described above.

[0014] This application also provides a controller that uses the pre-regulated circuit described above for operation control.

[0015] Beneficial effects: This invention provides a pre-regulatory circuit. The startup bias unit provides forced startup upon power-up, ensuring the circuit moves away from its degeneracy point and establishes a stable bias. It automatically exits after startup, reducing the impact on the main circuit. The pre-regulatory unit generates two signals based on this bias: one is a drive signal adapted to high-voltage LDMOS, improving the circuit's high-voltage adaptability; the other is a control signal for the reference circuit, used for subsequent enable management. The enable control unit selects this control signal via an external signal, enabling flexible control of the operating mode and cutting off the core bias during shutdown to reduce static power consumption. The high-voltage bandgap reference unit starts after receiving drive and bias, utilizing internal temperature compensation and closed-loop regulation mechanisms to output a high-precision, low-drift reference voltage. Its establishment precedes the digital logic, ensuring reliable initialization of the analog circuit. The output buffer unit enhances the reference voltage's load-carrying capacity and forms a global closed loop through feedback, further stabilizing the output voltage, suppressing load and power supply disturbances, and improving the overall robustness of the system. Attached Figure Description

[0016] Figure 1 Circuit block diagram of the pre-regulator circuit provided by the present invention Figure 2 The circuit structure diagram of the pre-stabilized voltage circuit provided by the present invention.

[0017] Explanation of key component symbols: 1-Start-up bias unit, 2-Pre-stabilization unit, 3-Enable control unit, 4-High voltage bandgap reference unit, 5-Output buffer unit. Detailed Implementation

[0018] This invention provides a pre-regulated voltage circuit, a PCB board, and a controller. To make the objectives, technical solutions, and effects of this invention clearer and more explicit, the invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only for explaining the invention and are not intended to limit the invention.

[0019] In the description of this invention, it should be understood that the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0020] Please see Figures 1 to 2This invention provides a pre-regulatory circuit, including a startup bias unit 1, a pre-regulatory unit 2, an enable control unit 3, a high-voltage bandgap reference unit 4, and an output buffer unit 5. The input terminal of the startup bias unit 1 is connected to an external high-voltage power supply terminal, used to generate a startup signal and provide a stable bias current when the system is powered on. The input terminal of the pre-regulatory unit 2 is connected to the output terminal of the startup bias unit 1 and the external high-voltage power supply terminal, and it is provided with a first output terminal and a second output terminal. The pre-regulatory unit 2 receives the bias current and generates two signals: the signal output from its first output terminal serves as a control signal for controlling the bias switching of the high-voltage bandgap reference unit 4, and this control signal is connected to the input terminal of the high-voltage bandgap reference unit 4 through the enable control unit 3; the signal output from its second output terminal serves as a drive signal for adapting to the internal LDMOS adjustment transistor of the high-voltage bandgap reference unit 4, and this drive signal is directly connected to the corresponding control terminal of the high-voltage bandgap reference unit 4. The enable control unit 3 is also connected to an external enable signal terminal to adjust the connection state between the control signal and the high-voltage bandgap reference unit 4 according to the external enable signal, thereby realizing the operating mode control of the entire reference circuit. The output terminal of the high-voltage bandgap reference unit 4 is connected to the input terminal of the output buffer unit 5, and the output sampling node of the output buffer unit 5 is connected to the feedback input terminal of the high-voltage bandgap reference unit 4, forming a closed loop to stabilize the output voltage. The high-voltage bandgap reference unit 4 generates a high-precision reference voltage with low correlation to power supply voltage and temperature changes based on the received control signal, drive signal, and feedback voltage from the output sampling node. The output buffer unit 5 is used to improve the driving capability and load-carrying capacity of the reference voltage, ensuring that it can stably power the subsequent load circuit.

[0021] In this embodiment, the startup bias unit 1 provides a forced startup mechanism at the moment the high-voltage power supply is powered on, which helps prevent the circuit from falling into the degeneracy point and ensures that the pre-regulator unit 2 can obtain the initial bias and enter the normal working state. This startup mechanism can automatically exit after power-on, thereby reducing the impact on the long-term stability of the main bias circuit. The pre-regulator unit 2 uses the stable bias provided by the startup bias unit 1 to generate two signals. The generated drive signal matches the gate drive requirements of the high-voltage LDMOS regulator, thereby improving the adaptability of the entire circuit to the high-voltage power supply. The generated control signal provides the basis for the enable control of subsequent circuits, realizing the management of the operating state of the core reference circuit. The enable control unit 3 selects the control signal path through the external enable signal, realizing flexible control of the operating mode of the entire pre-regulator circuit. In the shutdown mode, this unit can effectively cut off the core bias path of the high-voltage bandgap reference unit 4, which helps to reduce the static power consumption of the circuit in the non-operating state and meets the requirements of low-power applications. After receiving adaptive drive from pre-regulator unit 2 and effective bias from enable control unit, high-voltage bandgap reference unit 4 can start up and operate stably under high-voltage conditions. This unit utilizes the temperature characteristics of semiconductor devices to generate a temperature-compensated voltage through its internal circuit structure, and combined with an internal closed-loop regulation mechanism, ultimately outputs a reference voltage that is insensitive to changes in power supply voltage and temperature. Its operating point can be established before most of the digital logic circuits in the system, thus providing conditions for reliable initialization of the analog circuits. Output buffer unit 5 is connected after high-voltage bandgap reference unit 4. It significantly improves the current output capability of the reference voltage output node, enabling it to drive larger capacitive loads or provide a certain amount of source and sink current, while maintaining the accuracy and stability of the output voltage. Simultaneously, this unit feeds back a portion of the final output voltage to the input of high-voltage bandgap reference unit 4, forming a global negative feedback loop. This helps to further suppress output voltage fluctuations caused by load changes or power supply disturbances, enhancing the stability and robustness of the system.

[0022] The working principle of this application is as follows: During system power-up, the startup bias unit 1 operates first, providing the required bias current to the pre-regulator unit 2 based on the high-voltage signal from the external high-voltage power supply. The pre-regulator unit 2 is configured to generate two control signals based on this bias current: one is a control signal controlling the on / off state of the bias circuit inside the high-voltage bandgap reference unit 4, selected by the enable control unit 3; the other is a drive signal directly driving the high-voltage LDMOS regulating transistor inside the high-voltage bandgap reference unit 4. The enable control unit 3 adjusts the connection state between the control signal and the high-voltage bandgap reference unit 4 according to the logic level of the external enable signal terminal, thereby achieving overall control of the reference circuit's operating mode. When enabled, the high-voltage bandgap reference unit 4 generates a reference voltage with low temperature drift and high power supply rejection ratio based on the received control signal, drive signal, and feedback voltage from the output sampling node of the output buffer unit 5. The output buffer unit 5 is used to improve the driving capability and load-carrying capability of the reference voltage, and to form a closed loop to stabilize the final output voltage by feeding back the voltage of the output sampling node to the high-voltage bandgap reference unit 4.

[0023] In one specific circuit implementation, the startup bias unit 1 includes a power-on startup circuit and a reference current source circuit. The power-on startup circuit injects a forced startup current into the reference current source circuit at the initial moment of power-on at the external high-voltage power supply terminal, causing it to move away from its degeneracy point. After normal startup, the reference current source circuit provides a stable bias current to the pre-regulatory unit 2. The power-on startup circuit includes a first field-effect transistor M1, a second field-effect transistor M2, a third field-effect transistor M3, and a voltage divider resistor network. The sources of the first field-effect transistor M1, the second field-effect transistor M2, and the third field-effect transistor M3 are all connected to the external high-voltage power supply terminal. The drain of the first field-effect transistor M1 is connected to one end of the voltage divider resistor network, the other end of the voltage divider resistor network is grounded, and the drain of the first field-effect transistor M1 is shorted to its gate. This shorting point is also connected to the drain of the second field-effect transistor M2 and the gate of the third field-effect transistor M3. The voltage divider resistor network divides the high-voltage power supply, providing conditions for the conduction of the first field-effect transistor M1 and the third field-effect transistor M3. The gate of the second field-effect transistor M2 is connected to the reference current source circuit.

[0024] In this embodiment, the voltage divider resistor network includes a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4 connected in series. The other end of the first resistor R1 is connected to the drain of the first field-effect transistor M1, and the other end of the fourth resistor R4 is grounded.

[0025] The reference current source circuit includes a fourth field-effect transistor (FET) M4, a fifth FET M5, a sixth FET M6, a seventh FET M7, an eighth FET M8, a ninth FET M9, a tenth FET M10, an eleventh FET M11, and a fifth resistor R5. The sources of the fourth FET M4 and the fifth FET M5 are connected to an external high-voltage power supply. Multiple nodes, including the gates of the fourth FET M4, the gates and drains of the fifth FET M5, the gates of the seventh FET M7, the sixth FET M6, and the tenth FET M10, are interconnected to form a self-biased current mirror structure, which serves as the output node for the bias current. The drain of the fifth FET M5 is connected to the source of the seventh FET M7. The drain of the fourth FET M4 is connected to the drain of the sixth FET M6. The source of the eighth field-effect transistor M8 is connected to the drain and gate of the tenth field-effect transistor M10, the gate of the eleventh field-effect transistor M11, and the input terminal of the pre-regulation unit 2. The source of the tenth field-effect transistor M10 is grounded. The source of the eleventh field-effect transistor M11 is grounded through the fifth resistor R5. The drain of the third field-effect transistor M3 is connected to the drain of the sixth field-effect transistor M6, the drain and gate of the eighth field-effect transistor M8, and the gate of the ninth field-effect transistor M9. Upon power-up, the third field-effect transistor M3 is turned on, pulling up the gate potential of the eighth field-effect transistor M8, thereby starting the entire current source circuit. After the circuit stabilizes, the third field-effect transistor M3 is turned off due to the gate potential change, isolating the startup circuit from the main bias circuit.

[0026] The pre-regulation unit 2 includes a twelfth field-effect transistor (FET) M12, a thirteenth field-effect transistor (FET) M13, a fourteenth field-effect transistor (FET) M14, a fifteenth field-effect transistor (FET) M15, a sixteenth field-effect transistor (FET) M16, a seventeenth field-effect transistor (FET) M17, a sixth resistor R6, and a current switch. The source of the twelfth field-effect transistor (FET) M12 is connected to an external high-voltage power supply, and its gate is connected to a bias signal from the gate of the second field-effect transistor (FET) M2 in the startup bias unit 1. The drain of the twelfth field-effect transistor (FET) M12 is connected to the source of the thirteenth field-effect transistor (FET) M13. The gate of the thirteenth field-effect transistor (FET) M13 is connected to a bias signal from the gate of the seventh field-effect transistor (FET) M7 in the startup bias unit 1. The drain of the thirteenth field-effect transistor M13 is connected to an internal node (referred to as the first node) through the sixth resistor R6. This first node is simultaneously connected to the source of the fourteenth field-effect transistor M14, the gate of the seventeenth field-effect transistor M17, and the gate control terminal of the high-voltage adjustment transistor in the high-voltage bandgap reference unit 4, serving as the second output terminal of the pre-stabilization unit 2 to output the drive signal. The gate of the fourteenth field-effect transistor M14 is shorted to its drain and connected to the drain and gate of the fifteenth field-effect transistor M15. The source of the fifteenth field-effect transistor M15 is connected to the drain and gate of the sixteenth field-effect transistor M16, and the source of the sixteenth field-effect transistor M16 is grounded. The fourteenth field-effect transistor M14, the fifteenth field-effect transistor M15, and the sixteenth field-effect transistor M16 are connected in series to form a self-biased branch, used to establish a relatively stable voltage at the first node. The source of the seventeenth field-effect transistor M17 is connected to an external high-voltage power supply terminal, and its drain is connected to the current switching section.

[0027] The current switching unit includes an eighteenth field-effect transistor (FET) M18 and a nineteenth field-effect transistor (FET) M19. The drain of the eighteenth FET M18 is connected to the drain of the seventeenth FET M17, and its source is connected to the drain of the nineteenth FET M19. The source of the nineteenth FET M19 is grounded. The gate of the eighteenth FET M18 is connected to the gate of the nineteenth FET M19, the gate of the eleventh FET M11, and the input terminal of the enable control unit 3. The signal at this connection point serves as the control signal generated by the pre-regulation unit 2. The pre-regulation unit 2 utilizes the bias current provided by the start-up bias unit 1, and through the operation of components such as the twelfth FET M12, the thirteenth FET M13, and the sixth resistor R6, generates a gate voltage suitable for driving a high-voltage LDMOS device at the first node. Simultaneously, a controlled current path is formed through the seventeenth FET M17 and the current switching unit.

[0028] The enable control unit 3 includes a twentieth field-effect transistor (FET) M20, a twenty-first field-effect transistor (FET) M21, a twenty-second field-effect transistor (FET) M22, and an inverter INV. The source of the twentieth FET M20 is grounded, and its gate is connected to a control signal from the gates of the eighteenth and nineteenth FETs M18 and M19 in the pre-regulation unit 2. The drain of the twentieth FET M20 is connected to the sources of the eleventh and twenty-second FETs M21 and M22. The gate of the eleventh FET M21 and the input of the inverter INV are both connected to an external enable signal terminal. The output of the inverter INV is connected to the gate of the twenty-second FET M22. The drain of the eleventh FET M21 is connected to one bias input terminal of the high-voltage bandgap reference unit 4. The drain of the twenty-second FET M22 is connected to the other bias input terminal of the high-voltage bandgap reference unit 4 and one input terminal of the output buffer unit 5. When the external enable signal is valid, the 21st field-effect transistor M21 is turned on, and the 22nd field-effect transistor M22 is turned off, allowing the control signal to be transmitted to the high-voltage bandgap reference unit 4 and activating its main circuit. When the external enable signal is invalid, the 21st field-effect transistor M21 is turned off, and the 22nd field-effect transistor M22 is turned on, pulling down the relevant bias node potential of the high-voltage bandgap reference unit 4 and turning it off.

[0029] The high-voltage bandgap reference unit 4 includes a 23rd field-effect transistor M23, a 24th field-effect transistor M24, a 25th field-effect transistor M25, a 26th field-effect transistor M26, a 27th field-effect transistor M27, a 28th field-effect transistor M28, a 29th field-effect transistor M29, a 30th field-effect transistor M30, a 31st field-effect transistor M31, a 1st transistor NPN1, a 2nd transistor NPN2, a 3rd transistor NPN3, a 4th transistor NPN4, a 5th transistor NPN5, a 7th resistor R7, a 10th resistor R10, and an 11th resistor R11. The sources of the 23rd field-effect transistor M23, the 24th field-effect transistor M24, the 25th field-effect transistor M25, the 26th field-effect transistor M26, the 27th field-effect transistor M27, and the 29th field-effect transistor M29 are connected to an external high-voltage power supply. The drain and gate of the 23rd field-effect transistor M23, the gate of the 24th field-effect transistor M24, the gate of the 25th field-effect transistor M25, and the drain of the 26th field-effect transistor M26 are all connected to the drain of the 21st field-effect transistor M21 in the enable control unit 3. The drain of the 24th field-effect transistor M24 is connected to the gate of the 26th field-effect transistor M26, the gate of the 27th field-effect transistor M27, the source of the 28th field-effect transistor M28, and the gate of the 29th field-effect transistor M29. The drain of the 25th field-effect transistor M25, the gate and drain of the 28th field-effect transistor M28, and the gate of the 30th field-effect transistor M30 are all connected to the drain of the 22nd field-effect transistor M22 in the enable control unit 3. The 29th field-effect transistor M29 serves as a high-voltage LDMOS regulator, and its drain is connected to the source of the 30th field-effect transistor M30. The drain of the 30th field-effect transistor M30 is connected to the collector of the 2NPN2 transistor. The emitter of the second transistor NPN2 is connected to the collector and base of the first transistor NPN1, and the emitter of the first transistor NPN1 is grounded. The bases of the second transistor NPN2 and the third transistor NPN3 are connected. The emitter of the third transistor NPN3 serves as a feedback node, connected to the output terminal of the output buffer unit 5 and the bases of the fourth transistor NPN4 and the fifth transistor NPN5. The collector of the third transistor NPN3 is connected to the source of the thirty-first field-effect transistor M31. The gate of the thirty-first field-effect transistor M31 is connected to the drive signal from the first node of the pre-regulation unit 2, and its drain is connected to an external high-voltage power supply through the seventh resistor R7. The emitters of the fourth transistor NPN4 and the fifth transistor NPN5 are grounded through the network of the tenth resistor R10 and the eleventh resistor R11, and their collectors are respectively connected to the input terminal of the output buffer unit 5.Based on the temperature characteristics of semiconductor devices, this unit generates a voltage proportional to absolute temperature (PTAT) through the cooperation of the second transistor NPN2, the third transistor NPN3, the first transistor NPN1, and a resistor network. This voltage is compensated for by the negative temperature coefficient of the transistor's forward junction voltage (VBE), thereby generating a low-temperature drift reference voltage at the feedback node. The amplification loop composed of the 29th field-effect transistor M29, the 30th field-effect transistor M30, and the 23rd to 28th field-effect transistors M23 adjusts and stabilizes this reference voltage.

[0030] The output buffer unit 5 includes a 32nd field-effect transistor (FET) M32, a 33rd field-effect transistor (FET) M33, a 34th field-effect transistor (FET) M34, a 35th field-effect transistor (FET) M35, a 36th field-effect transistor (FET) M36, a 37th field-effect transistor (FET) M37, an 8th resistor R8, a 9th resistor R9, a 12th resistor R12, and a 13th resistor R13. The sources of the 32nd, 33rd, and 36th FETs are connected to an external high-voltage power supply. The gate of the 32nd FET M32 is connected to its drain, as well as the gate of the 33rd FET M33. The drain of the 32nd FET M32 is also connected to the drain of the 34th FET M34 via the 8th resistor R8. The drain of the 33rd FET M33 is connected to the drain of the 35th FET M35 via the 9th resistor R9, and this drain is also connected to the gate of the 36th FET M36. The source of the thirty-fourth field-effect transistor M34 is connected to the collector of the fourth transistor NPN4 in the high-voltage bandgap reference unit 4. The source of the thirty-fifth field-effect transistor M35 is connected to the collector of the fifth transistor NPN5 in the high-voltage bandgap reference unit 4. The gates of both the thirty-fourth and thirty-fifth field-effect transistors M34 and M35 are connected to the drive signal from the first node of the pre-regulation unit 2. The drain of the thirty-sixth field-effect transistor M36 is connected to the source of the thirty-seventh field-effect transistor M37. The gate of the thirty-seventh field-effect transistor M37 is connected to the drain of the twenty-second field-effect transistor M22 in the enable control unit 3, and its drain is connected to the final reference voltage output terminal VREF through the twelfth resistor R12 and grounded through the thirteenth resistor R13. This VREF node is also the sampling node that feeds back to the emitter of the third transistor NPN3 in the high-voltage bandgap reference unit 4. The thirty-second field-effect transistors M32 to M35 form a common-source, common-gate current mirror structure, used to accurately mirror and transmit the current signal from the high-voltage bandgap reference unit 4, driving the output stage composed of the thirty-sixth field-effect transistor M36 and the thirty-seventh field-effect transistor M37, thereby providing a larger output current capability. The voltage divider network formed by the twelfth resistor R12 and the thirteenth resistor R13 samples and feeds back the output voltage VREF, forming a closed-loop control, which helps to improve the stability and load-carrying capacity of the output voltage.

[0031] The working process of the pre-regulated voltage circuit in this application is as follows: Upon system power-up, an external high-voltage power supply is established. The starting bias unit 1 first generates a stable bias current. Based on this bias current, the pre-regulated voltage unit 2 establishes its internal operating point and generates a high-voltage drive signal and a bias control signal. When the external enable signal is valid, the enable control unit 3 guides the bias control signal to the high-voltage bandgap reference unit 4, causing its main circuit to start operating. Under the action of the high-voltage drive signal, the high-voltage bandgap reference unit 4, combined with its internal negative feedback loop, generates an initial low-temperature drift reference voltage. This voltage is amplified by the current and driven by the output buffer unit 5, outputting a stable reference voltage VREF. Simultaneously, VREF is fed back to the input terminal of the high-voltage bandgap reference unit 4 through the twelfth resistor R12 and the thirteenth resistor R13, forming a global negative feedback loop to accurately stabilize the final output voltage value. The entire circuit provides a reference voltage source for subsequent load circuits that has an early setup time, high accuracy, strong driving capability, and adaptability to high-voltage operating environments.

[0032] This application also provides a PCB board on which a pre-regulator circuit as described in any of the above embodiments is printed. This pre-regulator circuit can be soldered onto the PCB board as an independent power management integrated circuit or module to provide a stable and reliable reference voltage for other functional circuits on the PCB board, such as microcontrollers, analog-to-digital converters, and power drivers, thereby helping to improve the timing control and reliability of the entire circuit system's power-on process.

[0033] This application also provides a controller that employs a pre-regulated voltage circuit as described in any of the above embodiments for operational control. Specifically, the controller internally includes an analog circuit module requiring a reference voltage and a digital logic module. After the controller is powered on, the pre-regulated voltage circuit provides a stable bias and reference voltage to the analog circuit module before the initialization process of the digital logic module. This avoids the risk of digital logic errors due to the analog section not being ready, thus improving the controller's operational reliability in complex or high-voltage power supply environments. This controller can be applied to fields such as motor drives, power management, and communication interfaces.

[0034] It is understood that those skilled in the art can make equivalent substitutions or modifications to the technical solution and inventive concept of the present invention, and all such substitutions or modifications should fall within the protection scope of the appended claims.

Claims

1. A pre-regulated voltage circuit, characterized in that, The system includes a startup bias unit, a pre-regulation unit, an enable control unit, a high-voltage bandgap reference unit, and an output buffer unit. The input terminal of the startup bias unit is connected to an external high-voltage power supply. The input terminal of the pre-regulation unit is connected to both the output terminal of the startup bias unit and the external high-voltage power supply. The pre-regulation unit has a first output terminal and a second output terminal. The first output terminal of the pre-regulation unit is connected to the input terminal of the high-voltage bandgap reference unit via the enable control unit, which is also connected to an external enable signal terminal. The second output terminal of the pre-regulation unit is connected to the input terminal of the high-voltage bandgap reference unit. The output terminal of the high-voltage bandgap reference unit is connected to the input terminal of the output buffer unit, and the output of the output buffer unit... The sampling node is connected to the input terminal of the high-voltage bandgap reference unit; the start-up bias unit is used to provide bias current to the pre-regulation unit according to the high-voltage signal from the external high-voltage power supply terminal; the pre-regulation unit is used to generate a control signal for controlling the bias switching of the high-voltage bandgap reference unit and a drive signal for the LDMOS regulating transistor adapted to the high-voltage bandgap reference unit according to the bias current; the enable control unit is used to adjust the connection state between the control signal and the high-voltage bandgap reference unit according to the signal from the external enable signal terminal; the high-voltage bandgap reference unit is used to generate a reference voltage according to the control signal, the drive signal and the feedback signal from the output sampling node; the output buffer unit is used to improve the load-carrying capacity of the reference voltage output by the high-voltage bandgap reference unit.

2. The pre-regulator circuit according to claim 1, characterized in that, The startup bias unit includes a power-on startup circuit and a reference current source circuit. The input terminals of the power-on startup circuit and the reference current source circuit are respectively connected to an external high-voltage power supply. The output terminal of the power-on startup circuit is connected to the enable terminal of the reference current source circuit, and the output terminal of the reference current source circuit is connected to the input terminal of the pre-regulation unit. The power-on startup circuit is used to inject a forced startup current into the reference current source circuit at the moment of power-on of the external high-voltage power supply. The reference current source circuit is used to provide bias current for the pre-regulation unit.

3. The pre-regulator circuit according to claim 2, characterized in that, The power-on startup circuit includes a first field-effect transistor M1, a second field-effect transistor M2, a third field-effect transistor M3, and a voltage divider resistor network; the reference current source circuit includes a fourth field-effect transistor M4, a fifth field-effect transistor M5, a sixth field-effect transistor M6, a seventh field-effect transistor M7, an eighth field-effect transistor M8, a ninth field-effect transistor M9, a tenth field-effect transistor M10, an eleventh field-effect transistor M11, and a fifth resistor R5; the sources of the first field-effect transistor M1, the second field-effect transistor M2, and the third field-effect transistor M3 are connected to an external high-voltage power supply terminal. The drain of the first field-effect transistor M1 is connected to one end of the voltage divider resistor network, and the other end of the voltage divider resistor network is grounded. The drain of the first field-effect transistor M1 is also shorted to its gate. The gate of the first field-effect transistor M1 is also connected to the drain of the second field-effect transistor M2 and the gate of the third field-effect transistor M3. The gate of the second field-effect transistor M2 is connected to the gate of the fourth field-effect transistor M4, the gate and drain of the fifth field-effect transistor M5, and the input terminal of the pre-regulator unit. The third field-effect transistor M3... The drain of the transistor is connected to the drain of the sixth field-effect transistor M6, the drain and gate of the eighth field-effect transistor M8, and the gate of the ninth field-effect transistor M9. The sources of the fourth field-effect transistor M4 and the fifth field-effect transistor M5 are connected to an external high-voltage power supply. The drain of the fourth field-effect transistor M4 is connected to the drain of the sixth field-effect transistor M6. The drain of the fifth field-effect transistor M5 is also connected to the source of the seventh field-effect transistor M7. The gate of the seventh field-effect transistor M7 is shorted to its drain. The gate of the seventh field-effect transistor M7 is also connected to... The gate of the sixth field-effect transistor M6 is connected to the input terminal of the pre-regulation unit. The drain of the seventh field-effect transistor M7 is also connected to the drain of the ninth field-effect transistor M9. The source of the eighth field-effect transistor M8 is connected to the drain and gate of the tenth field-effect transistor M10. The gate of the eleventh field-effect transistor M11 is connected to the input terminal of the pre-regulation unit. The source of the tenth field-effect transistor M10 is grounded. The source of the eleventh field-effect transistor M11 is connected to one end of the fifth resistor R5. The other end of the fifth resistor R5 is grounded.

4. The pre-regulator circuit according to claim 3, characterized in that, The pre-regulator unit includes a twelfth field-effect transistor (FET) M12, a thirteenth field-effect transistor (FET) M13, a fourteenth field-effect transistor (FET) M14, a fifteenth field-effect transistor (FET) M15, a sixteenth field-effect transistor (FET) M16, a seventeenth field-effect transistor (FET) M17, a sixth resistor R6, and a current switch. The source of the twelfth field-effect transistor (FET) M12 is connected to an external high-voltage power supply. The gate of the twelfth field-effect transistor (FET) M12 is connected to the gate of the second field-effect transistor (FET) M2. The drain of the twelfth field-effect transistor (FET) M12 is connected to the source of the thirteenth field-effect transistor (FET) M13. The gate of the thirteenth field-effect transistor (FET) M13 is connected to the gate of the seventh field-effect transistor (FET) M7. The drain of the thirteenth field-effect transistor (FET) M13 is connected to one end of the sixth resistor R6, and the other end of the sixth resistor R6 is connected to... The source of the fourteenth field-effect transistor M14, the gate of the seventeenth field-effect transistor M17, and the input terminal of the high-voltage bandgap reference unit are connected. The gate of the fourteenth field-effect transistor M14 is shorted to its drain. The drain of the fourteenth field-effect transistor M14 is also connected to the drain and gate of the fifteenth field-effect transistor M15. The source of the fifteenth field-effect transistor M15 is connected to the drain and gate of the sixteenth field-effect transistor M16. The source of the sixteenth field-effect transistor M16 is grounded. The source of the seventeenth field-effect transistor M17 is connected to an external high-voltage power supply terminal. The drain of the seventeenth field-effect transistor M17 is connected to the current switching unit. The current switching unit is also connected to the gate of the eleventh field-effect transistor M11 and the input terminal of the enable control unit.

5. The pre-regulator circuit according to claim 4, characterized in that, The current switching unit includes an eighteenth field-effect transistor M18 and a nineteenth field-effect transistor M19. The drain of the eighteenth field-effect transistor M18 is connected to the drain of the seventeenth field-effect transistor M17, the source of the eighteenth field-effect transistor M18 is connected to the drain of the nineteenth field-effect transistor M19, the source of the nineteenth field-effect transistor M19 is grounded, and the gate of the eighteenth field-effect transistor M18 is connected to the gate of the eleventh field-effect transistor M11, the gate of the nineteenth field-effect transistor M19, and the input terminal of the enable control unit.

6. The pre-regulator circuit according to claim 5, characterized in that, The enable control unit includes a twentieth field-effect transistor (FET) M20, a twenty-first field-effect transistor (FET) M21, a twenty-second field-effect transistor (FET) M22, and an inverter INV. The source of the twentieth FET M20 is grounded, and its gate is connected to the gate of the eighteenth FET M18. The drain of the twentieth FET M20 is connected to the sources of the twenty-first and twenty-second FETs M21 and M22. The gate of the twenty-first FET M21 and the input of the inverter INV are connected to an external enable signal terminal. The output of the inverter INV is connected to the gate of the twenty-second FET M22. The drain of the twenty-first FET M21 is connected to the input of the high-voltage bandgap reference unit. The drain of the twenty-second FET M22 is connected to the inputs of both the high-voltage bandgap reference unit and the output buffer unit.

7. The pre-regulator circuit according to claim 6, characterized in that, The high-voltage bandgap reference unit includes the following transistors: M23 (23rd), M24 (24th), M25 (25th), M26 (26th), M27 (27th), M28 (28th), M29 (29th), M30 (30th), M31 (31st), NPN1 (1st), NPN2 (2nd), NPN3 (3rd), NPN4 (4th), NPN5 (5th), R7 (7th), R10 (10th), and R11 (11th). The sources of transistors M26, M27, and M29 are connected to an external high-voltage power supply. The drain and gate of M23, the gate of M24, the gate of M25, and the drain of M26 are connected to the drain of M21. The drain of M24 is connected to the gate of M26, the gate of M27, the source of M28, and the gate of M29. The drain of M25 is connected to the gate of M21. The gate and drain of the 28th field-effect transistor M28 and the gate of the 30th field-effect transistor M30 are connected to the drain of the 22nd field-effect transistor M22. The drain of the 29th field-effect transistor M29 is connected to the source of the 30th field-effect transistor M30. The drain of the 30th field-effect transistor M30 is connected to the collector of the 2nd transistor NPN2. The emitter of the 2nd transistor NPN2 is connected to the collector and base of the 1st transistor NPN1. The emitter of the 1st transistor NPN1 is grounded. The base of the 2nd transistor NPN2 is connected to the base of the 3rd transistor NPN3. The emitter of the 3rd transistor NPN3 is connected to the output terminal of the output buffer unit and the fourth transistor N. The base of PN4 is connected to the base of the fifth transistor NPN5. The collector of the third transistor NPN3 is connected to the source of the thirty-first field-effect transistor M31. The gate of the thirty-first field-effect transistor M31 is connected to the gate of the seventeenth field-effect transistor M17. The drain of the thirty-first field-effect transistor M31 is connected to one end of the seventh resistor R7. The other end of the seventh resistor R7 is connected to an external high-voltage power supply. The emitter of the fifth transistor NPN5 is connected to one end of the tenth resistor R10. The emitter of the fourth transistor NPN4 and the other end of the tenth resistor R10 are respectively connected to one end of the eleventh resistor R11. The other end of the eleventh resistor R11 is grounded.The collectors of the fourth transistor NPN4 and the fifth transistor NPN5 are respectively connected to the input terminals of the output buffer unit.

8. The pre-regulator circuit according to claim 7, characterized in that, The output buffer unit includes a 32nd field-effect transistor (FET), a 33rd field-effect transistor (FET), a 34th field-effect transistor (FET), a 35th field-effect transistor (FET), a 36th field-effect transistor (FET), a 37th field-effect transistor (FET), an 8th resistor (R8), a 9th resistor (R9), a 12th resistor (R12), and a 13th resistor (R13). The sources of the 32nd, 33rd, and 36th FETs are connected to an external high-voltage power supply. The gate of the 32nd FET, its drain, and the gate of the 33rd FET are connected. The drain of the 32nd FET is also connected to one end of the 8th resistor (R8). The other end of the 8th resistor (R8) is connected to the drain of the 34th FET (FET). The source of the 34th FET (FET) is connected to the collector of the 4th transistor (NPN4). The 33rd FET M3... The drain of transistor 3 is connected to one end of the ninth resistor R9 and the gate of the thirty-sixth field-effect transistor M36. The other end of the ninth resistor R9 is connected to the drain of the thirty-fifth field-effect transistor M35. The source of the thirty-fifth field-effect transistor M35 is connected to the collector of the fifth transistor NPN5. The gates of the thirty-fourth field-effect transistor M34 and the thirty-fifth field-effect transistor M35 are connected to the gate of the seventeenth field-effect transistor M17. The drain of the thirty-sixth field-effect transistor M36 is connected to the source of the thirty-seventh field-effect transistor M37. The gate of the thirty-seventh field-effect transistor M37 is connected to the drain of the twenty-second field-effect transistor M22. The drain of the thirty-seventh field-effect transistor M37 is connected to one end of the twelfth resistor R12. The other end of the twelfth resistor R12 is connected to the emitter of the third transistor NPN3 and one end of the thirteenth resistor R13. The other end of the thirteenth resistor R13 is grounded.

9. A PCB board, characterized in that, The PCB board is printed with a pre-regulatory circuit as described in any one of claims 1-8.

10. A controller, characterized in that, The controller employs a pre-regulated circuit as described in any one of claims 1-8.

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