A semiconductor package-on-board structure and packaging process

Abstract

This invention discloses a semiconductor board-level packaging structure and packaging process. The packaging process includes the following steps: providing a molding substrate, bonding multiple wafers face-down onto the molding substrate; performing board-level molding to form a molding compound; removing the molding substrate to expose the front side of the wafers; forming a passivation layer and a redistribution structure on the exposed wafers; pre-cutting along the wafer dicing lines to form grooves; applying a solid insulating material film to the side with the passivation layer and redistribution structure using a vacuum lamination process, and filling the grooves with the solid insulating material film; thinning the back side of the molding compound; and finally cutting the structure filled with the solid insulating material film, so that the sides of each chip retain the solid insulating material film, forming a single product with six sides packaged. This invention achieves efficient six-sided chip packaging, effectively reducing thermal stress and warpage while ensuring high-precision circuit fabrication, minimizing the impact on the chip body, and significantly improving product reliability.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and more specifically to a semiconductor board-level packaging structure and packaging process. Background Technology

[0002] As semiconductor devices evolve towards higher performance, smaller size, and higher integration, chip packaging technology not only needs to protect chips from damage caused by external environments (such as moisture, contaminants, and mechanical stress), but also needs to provide reliable electrical interconnections. To achieve comprehensive chip protection, the six-sided packaging concept was proposed, which involves covering the top, bottom, and four sides of the chip.

[0003] In the evolution of packaging technology, wafer-level processes have become an important means of achieving chip-level packaging due to their high precision and suitability for mass production. Meanwhile, board-level packaging technology, which can process multiple wafers in parallel on large-size substrates, has gradually attracted industry attention due to its significant advantages in production efficiency and cost.

[0004] To meet the requirements of six-sided packaging, those skilled in the art have attempted to apply wafer-level processing techniques to the protection of chip sides, for example, by forming grooves on the wafer and filling them with insulating material to provide a protective layer for the chip sides. However, six-sided packaging methods based solely on wafer-level processes still have the following prominent problems: Process platform limitations: Wafer-level processes handle only one wafer at a time, and production efficiency is limited by wafer size, making it difficult to meet the needs of large-scale, low-cost manufacturing.

[0005] Inappropriate process timing: The grooving and filling steps for forming side protection usually need to be performed before the fine lines are formed on the wafer surface. This results in the subsequent line fabrication having to be carried out on uneven or already filled surfaces, affecting the accuracy of the lines and the process window.

[0006] The trade-off between structural reliability and processing precision: Existing grooving methods often employ wide dicing channels to provide space for filler material. Excessively wide dicing channels directly encroach on the effective structural area of ​​the chip, effectively "thinning" and weakening the chip itself, potentially compromising its mechanical strength and long-term reliability. Simultaneously, excessively wide dicing channels occupy more wafer area, leading to a reduction in the number of chips produced per wafer, which is detrimental to cost control.

[0007] Reliability and manufacturing bottlenecks caused by materials and processes: Specifically, existing processes typically involve filling the dicing channels with a large amount of liquid encapsulant in a vacuum environment after wafer pre-dicing to achieve side coating. This approach has inherent drawbacks: First, the coefficient of thermal expansion of the selected liquid encapsulant material is usually much higher than that of the silicon chip, generating huge thermal mismatch stress during curing and subsequent thermal processes. This leads to severe warping of the wafer or package, causing misalignment in subsequent fine operations such as photolithography and bonding, resulting in a significant drop in product yield or even the scrapping of the entire batch. Second, this filling process (especially vacuum filling and warpage correction) is highly dependent on manual or semi-automated operations, which are complex, inefficient, and inconsistent, significantly increasing manufacturing costs and process difficulty, and cannot meet the needs of large-scale mass production.

[0008] On the other hand, if board-level packaging technology is directly applied to six-sided packaging, new process challenges such as warpage control, large-size uniformity, and multi-wafer alignment will be faced, and existing wafer-level six-sided packaging methods do not provide corresponding solutions.

[0009] Therefore, how to organically combine the processing precision of wafer-level processes, the production efficiency of board-level packaging, and the structural requirements of six-sided packaging to develop a highly efficient and reliable packaging method that can effectively protect the six sides of the chip, minimize the impact on the chip body through optimized slot design, and solve the warpage and manufacturing bottlenecks caused by high CTE material filling, thus adapting to large-scale board-level manufacturing, has become a key technical challenge that urgently needs to be overcome in this field. Summary of the Invention

[0010] To address the aforementioned technical problems, the present invention aims to provide a semiconductor board-level packaging structure and packaging process. This invention combines wafer-level process precision with board-level packaging efficiency, achieving highly efficient six-sided chip packaging. While ensuring high-precision circuit fabrication, it effectively reduces thermal stress and warpage, minimizes the impact on the chip itself, and significantly improves product reliability and scalability.

[0011] To achieve the above-mentioned technical objectives and effects, the present invention is implemented through the following technical solution: This invention provides a semiconductor board-level packaging process, comprising the following steps: A molding substrate is provided, on which multiple wafers to be diced into chips are temporarily bonded, face down. Board-level molding is performed to form a molding compound that covers all wafers; Remove the plastic-encapsulated substrate to expose the front side of the wafer; A passivation layer and redistribution structure are formed on the exposed wafer; Pre-cut along the wafer dicing path to form a groove with a depth greater than the chip thickness; A solid insulating material film is pressed onto the side having the passivation layer and redistribution structure using a vacuum pressing process, and the solid insulating material film is pressed and flowed in a vacuum environment to fill the groove. The back side of the encapsulation opposite to the side where the passivation layer and redistribution structure are formed is thinned until the solid insulating material film in the groove is exposed; The structure filled with the solid insulating material film is then cut to ensure that the solid insulating material film remains on the sides of each obtained single chip, forming a single product that is packaged on all six sides.

[0012] Furthermore, after removing the molding substrate and before thinning the back side of the molding body, the method further includes: providing a support structure on the back side of the molding body, the support structure being a support substrate bonded by temporary bonding technology or a structure bonded back-to-back with another molding body; and before performing the back side thinning process, releasing the temporary bonding relationship between the support structure and the molding body.

[0013] Furthermore, the step of forming a passivation layer and redistribution structure on the exposed wafer includes: An insulating material is laminated onto the front side of the wafer and then baked to form a passivation layer. Laser ablation technology is used to form openings on the passivation layer at the locations corresponding to the chip pads. A rewiring structure electrically connected to the pads is formed through physical vapor deposition, photolithography, electroplating, and etching processes.

[0014] Furthermore, after forming the solid insulating material film, the process further includes a step of constructing a multilayer redistribution structure and / or forming an external connection structure through a patterned electroplating process.

[0015] Furthermore, by controlling the difference between the pre-cut width and the final cut width, the thickness of the solid insulating material film covering the final chip side is adjusted.

[0016] Furthermore, the groove formed by the pre-cutting is located within the molding compound or within the wafer, depending on the location of the cut track. Specifically, in the cut track region between adjacent wafers, the groove is formed within the molding compound; in the cut track region inside the wafer, the groove is formed within the wafer.

[0017] Furthermore, the coefficient of thermal expansion of the solid insulating material film is lower than that of the material forming the encapsulation.

[0018] Furthermore, the molding substrate has a releasable temporary bonding layer, which is released from bonding by thermal release, photorelease, or mechanical peeling when the molding substrate is removed.

[0019] Furthermore, when thinning the back side of the encapsulant, the thinning is performed until the solid insulating material film in the groove is flush with or slightly lower than the back side of the encapsulant.

[0020] Another aspect of the present invention provides a semiconductor board-level packaging structure, comprising: The chip has a front and a back side, as well as four sides connecting the front and the back side; A molding compound that covers the back side of the chip; A passivation layer and a redistribution structure are disposed on the front side of the chip; A solid insulating material film is applied to the passivation layer and the redistribution structure, and extends to the side region of the chip, forming a side protective layer on the side of the chip. The chip's front, back, and four sides are covered by solid insulating material films located on the passivation layer and redistribution structure, a molding compound on the back, and solid insulating material films on the sides, forming a six-sided encapsulation structure.

[0021] The beneficial effects of this invention are as follows: (1) The present invention adopts a board-level packaging platform to process multiple wafers in parallel. Multiple wafers can be processed in a single production run. The production efficiency is much higher than that of traditional wafer-level packaging methods, significantly reducing the unit manufacturing cost and meeting the needs of large-scale mass production.

[0022] (2) The present invention performs pre-cutting after the passivation layer and redistribution structure are completed, ensuring that fine lines are fabricated on a complete and flat wafer surface, avoiding the precision loss and process window limitations caused by photolithography on a surface with filled grooves in the traditional solution.

[0023] (3) The present invention uses a vacuum pressing process to press a solid insulating material film onto the wafer surface and fill the groove. The material flows under pressure in a vacuum environment, which can achieve a bubble-free and highly dense filling effect. The thermal expansion coefficient of the solid insulating material film can be selected independently, which can effectively reduce thermal stress, reduce product warping, improve yield and long-term reliability, and is suitable for automated operation to significantly improve efficiency.

[0024] (4) In this invention, the pre-cutting is carried out along the original cutting line of the wafer to make narrow grooves. The grooves are only opened in the necessary cutting area, which avoids the problem of wide grooves or the groove position encroaching on the effective area of ​​the chip in the traditional solution. This minimizes the "thinning" effect on the chip body and preserves the mechanical strength of the chip.

[0025] (5) The present invention achieves complete and controllable encapsulation of the six surfaces of the chip by using a process sequence of “pre-cutting + solid film vacuum filling + back side thinning + final cutting”, so that the top surface of the chip is covered by a passivation layer and a solid insulating material film on the redistribution structure, the bottom surface is covered by a molding compound, and the four sides are covered by a solid insulating material film extending to the side areas. This significantly improves the reliability indicators of the device, such as moisture resistance and mechanical stress resistance.

[0026] (6) The present invention is compatible with subsequent processes such as multi-layer rewiring structure and external connection structure, and meets the diverse needs of different products. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the structure obtained in step one of the semiconductor board-level packaging process of the present invention.

[0028] Figure 2 This is a schematic diagram of the structure obtained in step two of the semiconductor board-level packaging process of the present invention.

[0029] Figure 3 This is a schematic diagram of the structure obtained in step three of the semiconductor board-level packaging process of the present invention.

[0030] Figure 4 This is a schematic diagram of the structure obtained in step four of the semiconductor board-level packaging process of the present invention.

[0031] Figure 5 This is a schematic diagram of the structure obtained in step five of the semiconductor board-level packaging process of the present invention.

[0032] Figure 6 This is a schematic diagram of the structure obtained in step six of the semiconductor board-level packaging process of the present invention.

[0033] Figure 7 This is a schematic diagram of the structure obtained in step seven of the semiconductor board-level packaging process of the present invention.

[0034] Figure 8 This is a schematic diagram of the structure obtained in step eight of the semiconductor board-level packaging process of the present invention.

[0035] In the figure, 10: wafer; 20: molding substrate; 30: temporary bonding layer; 40: molding body; 50: passivation layer; 60: redistribution structure; 70: groove; 80: solid insulating material film; 90: external connection structure; 100: chip. Detailed Implementation

[0036] The technical solutions of the present invention will be clearly and completely described below with reference to specific embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0037] This invention provides a semiconductor board-level packaging process and a packaging structure fabricated by the process. This process combines the processing precision of wafer-level processes with the high efficiency of board-level packaging. Through optimized process timing and innovative material filling methods, it achieves complete coverage of all six sides of the chip, while simultaneously achieving multiple objectives such as high-precision circuit fabrication, low-stress filling, and chip body protection.

[0038] like Figures 1 to 8 As shown, the semiconductor board-level packaging process provided by this invention includes the following steps: Step 1: A molding substrate 20 with a releasable temporary bonding layer 30 is provided. Multiple wafers 10 (with completed front-end processes) to be diced into chips 100 are bonded to the molding substrate 20 with their front sides facing down through the temporary bonding layer 30. The temporary bonding layer 30 is preferably released by thermal release, optical release, or mechanical peeling to facilitate subsequent removal of the molding substrate. The front side of the wafer 10 has chip pads.

[0039] Step 2: Perform board-level molding by forming a molding compound 40 that covers all wafers 10 using molding compound material such as epoxy molding compound. The molding compound 40 covers the back and side areas of wafers 10.

[0040] Step 3: Remove the temporary bonding layer 30 by heat, light or mechanical means, remove the plastic encapsulation substrate 20, and expose the front side of the wafer 10.

[0041] Step four involves forming a passivation layer 50 and a redistribution structure 60 on the exposed front side of wafer 10. Specifically: first, an insulating material is laminated onto the front side of wafer 10 and baked to form the passivation layer 50. Then, laser ablation technology is used to create openings on the passivation layer 50 corresponding to the chip pad positions. Next, a seed layer is deposited on the passivation layer 50 using physical vapor deposition (PVD) or similar methods. Subsequently, a dry film is etched using photolithography, and after exposure, development, and other patterning processes, the required circuit pattern is formed. Then, electroplating is performed to form a metal (such as copper) circuit pattern. Afterward, the dry film is removed, and excess seed layer is etched away, thus completing the fabrication of the first redistribution structure 60 (RDL). The RDL enables electrical connections and fan-out between the chip pads and subsequent external interconnect structures. This step is performed with the wafer 10 surface completely flat, ensuring the fabrication precision of the fine circuitry.

[0042] Step 5: Pre-cut along the dicing lines of wafer 10 to form a groove 70 with a depth greater than the final chip thickness. This pre-cutting step is performed after the passivation layer 50 and redistribution structure 60 are formed, avoiding the process risks of fabricating circuits on the already filled surface. The groove 70 formed by pre-cutting is located either within the molding compound 40 or within the wafer 10, depending on the location of the dicing lines: in the dicing line region between adjacent wafers 10, the groove 70 is formed within the molding compound 40; in the dicing line region inside the wafer 10, the groove 70 is formed within the wafer 10. Furthermore, the side of the groove 70 formed by cutting connects to the side of the diced chip 100, that is, the side of the chip 100 is exposed to the groove 70. Regarding the pre-cut width, this invention employs a narrow slot design, ensuring that the difference between the pre-cut width and the final cut width is approximately equal to twice the thickness of the predetermined side protection layer (a solid insulating material film located on the side of the chip). In other words, the pre-cut width only needs to be slightly larger than the sum of the final cut width and twice the target side protection layer thickness. The target side protection layer thickness can be set according to reliability requirements, exemplarily ranging from 5μm to 15μm. It should be noted that the "final cut width" mentioned in this application refers to the actual material removal width generated during the final cut, i.e., the cutting loss width. This width depends on the parameters of the cutting tool and the process conditions, and is typically slightly larger than the physical width of the cutting tool itself.

[0043] Step six involves applying a solid insulating material film 80 to the side with the passivation layer 50 and redistribution structure 60 using a vacuum pressing process. The solid insulating material film 80 is then pressurized and flowed under vacuum to fill the pre-cut groove 70. This process uses a solid insulating material film 80 (such as a dry film) instead of traditional liquid adhesive, and allows it to flow and fill under pressure in a vacuum environment, achieving a bubble-free and highly dense filling effect. The coefficient of thermal expansion of the solid insulating material film 80 can be independently selected, preferably lower than that of the molding compound material, thereby effectively reducing thermal stress and product warping. Simultaneously, the solid insulating material film has a uniform thickness, making it suitable for automated operations.

[0044] After forming the solid insulating material film 80, a multi-layer redistribution structure 60 can be constructed and / or an external connection structure 90, such as solder balls and pads, can be formed through patterned electroplating processes (including repeated drilling (such as laser drilling), photolithography, electroplating, etc.) according to product requirements. These subsequent processes are well compatible with the basic process of this invention and meet the diverse needs of different products.

[0045] Step 7: Thin the back side of the encapsulant 40 opposite to the side where the passivation layer 50 and the redistribution structure 60 are formed until the solid insulating material film 80 in the groove 70 is exposed. Preferably, the solid insulating material film 80 is thinned to be flush with or slightly lower than the back side of the encapsulant 40 to provide a flat base for subsequent segmentation.

[0046] Step eight involves a final cut of the structure filled with the solid insulating material film 80, ensuring that the sides of each obtained individual chip 100 retain the solid insulating material film 80, forming a single-chip packaged product with six sides encapsulated. By controlling the difference between the pre-cut width and the final cut width, the thickness of the solid insulating material film 80 covering the sides of the chip 100 can be precisely adjusted. The final cut is performed within the width of the groove 70, with the cutting path essentially overlapping the pre-cut path, ensuring that the cutting loss is located inside the groove 70, thereby retaining a predetermined thickness of solid insulating material film 80 on both sides of the chip 100 as a side protective layer.

[0047] In a preferred embodiment, after removing the molding substrate 20 and before thinning the back side of the molding compound 40, a step of providing a support structure on the back side of the molding compound 40 is included. This support structure can be a support substrate bonded using temporary bonding technology, or a structure back-to-back bonded to another molding compound 40. Its function is to enhance the mechanical strength of the molding compound 40 and prevent warping deformation. For back-to-back bonded structures, parallel processing on both sides can also be achieved. Before performing the back side thinning process, the temporary bond between the support structure and the molding compound 40 must be released, separating them from each other.

[0048] like Figure 8 As shown, the present invention also provides a semiconductor board-level package structure prepared using the above-described process, comprising: a chip 100 having a front side and a back side opposite to each other, and four sides connecting the front side and the back side; a molding compound 40 covering the back side of the chip 100; a passivation layer 50, a redistribution structure 60, and an external connection structure 90 disposed on the front side of the chip 100; and a solid insulating material film 80 covering the passivation layer 50 and the redistribution structure 60 and extending to the side regions of the chip 100, forming a side protection layer at the side positions of the chip 100. The front side, back side, and four sides of the chip 100 are respectively covered by the solid insulating material film 80 located on the passivation layer 50 and the redistribution structure 60, the molding compound 40 located on the back side, and the solid insulating material film 80 located on the sides, forming a six-sided package structure.

[0049] To make the present invention clearer, the following are some preferred ranges of process parameters, which are for illustrative purposes only and do not constitute limitations: the wafer thickness can be 200μm-800μm; the depth of the groove 70 formed by pre-cutting can exceed the final chip thickness by 10μm-50μm; the pre-cutting width can be determined according to the thickness of the target side protective layer, and is exemplarily 20μm-60μm; the final cutting width depends on the cutting tool, and is exemplarily 15μm-30μm; the target side protective layer thickness can be set to 5μm-20μm according to reliability requirements; the vacuum degree of the vacuum pressing process is preferably lower than 100Pa, the pressing pressure is preferably 0.1MPa-0.5MPa, and the pressing temperature is preferably 40℃-80℃.

[0050] In summary, the present invention achieves the following comprehensive technical effects through the above technical solutions: The use of a board-level packaging platform allows for parallel processing of multiple wafers, resulting in significantly higher production efficiency than traditional wafer-level packaging and a substantial reduction in unit manufacturing costs; pre-dicing after the passivation layer and redistribution structure are completed ensures that fine lines are fabricated on a complete and flat surface, avoiding precision loss; vacuum lamination fills the grooves with a solid insulating material film, achieving bubble-free, highly dense filling, and the thermal expansion coefficient of the solid insulating material film can be independently selected to reduce thermal stress and warping; pre-dicing involves narrow groove processing along the original wafer dicing lines, and through differentiated grooving and precise width control, it minimizes the impact on the chip body and improves wafer area utilization; the process sequence of "pre-dicing + solid film vacuum filling + backside thinning + final dicing" achieves complete coverage of all six surfaces of the chip, significantly improving device reliability; simultaneously, this process is highly compatible with subsequent processes such as multi-layer redistribution structures and external connection structures, meeting diverse product requirements.

[0051] The present invention will be further described below through specific embodiments.

[0052] Example like Figures 1 to 8 As shown, this embodiment provides a semiconductor board-level packaging process that does not employ a support structure, specifically including the following steps: Step 1: Temporarily bonding wafer 10 to the carrier substrate: A molding substrate 20 with a temporary bonding layer 30 is provided. Multiple wafers 10, which have completed front-end processes and are to be diced into chips 100, are bonded face down to the molding substrate 20 through the temporary bonding layer 30. The front side of the wafer 10 has chip pads. The temporary bonding layer 30 can be released by thermal release to facilitate the subsequent removal of the molding substrate 20.

[0053] Step 2, board-level molding: Board-level molding is performed by using epoxy molding compound to form a molding compound 40 that covers all wafers 10, including the back and side areas of wafers 10.

[0054] Step 3, Remove the molding substrate 20: Remove the temporary bonding layer 30 by heating, remove the molding substrate 20, and expose the front side of the wafer 10.

[0055] Step 4: Forming the passivation layer 50 and the redistribution structure 60: The passivation layer 50 and the redistribution structure 60 are formed on the exposed front side of the wafer 10. Specifically: First, an insulating material is laminated onto the front side of the wafer 10 and baked to form the passivation layer 50; then, an opening is formed on the passivation layer 50 corresponding to the chip pad position using laser ablation technology; then, a seed layer is deposited on the passivation layer 50 by physical vapor deposition (PVD); subsequently, a dry film is etched, and the required circuit pattern is formed through patterning processes such as exposure and development; then, electroplating is performed to form a copper circuit pattern; finally, the dry film is removed, and excess seed layer is etched away, thereby completing the fabrication of the redistribution structure 60.

[0056] Step 5, Pre-cutting to form a groove 70: Pre-cutting is performed along the dicing lines of wafer 10 to form a groove 70 with a depth greater than the final chip 100 thickness. The groove 70 formed by the pre-cutting is located either within the molding compound 40 or within the wafer 10, depending on the location of the dicing lines: in the dicing line region between adjacent wafers 10, the groove 70 is formed within the molding compound 40; in the dicing line region inside the wafer 10, the groove 70 is formed within the wafer 10. Furthermore, the sidewalls of the groove 70 formed by the cutting connect to the sidewalls of the diced chip 100, meaning the sidewalls of the chip 100 are exposed to the groove 70. The pre-cutting width is designed to be 35 μm, the target sidewall protection layer thickness is 10 μm, and the final cutting width is 15 μm. The difference between the pre-cutting width and the final cutting width is 20 μm, which is equal to twice the target sidewall protection layer thickness.

[0057] Step Six: Vacuum Lamination and Filling of Solid Insulating Material Film 80: A solid insulating material film 80 (dry film) is laminated onto the side with the passivation layer 50 and redistribution structure 60 using a vacuum lamination process. The solid insulating material film 80 is then pressurized and flows under vacuum to fill the pre-cut groove 70. The vacuum degree of the vacuum lamination process is 80 Pa, the lamination pressure is 0.3 MPa, and the lamination temperature is 60°C. The coefficient of thermal expansion of the solid insulating material film 80 is 25 ppm / °C, which is lower than the coefficient of thermal expansion of the molding compound material (approximately 40 ppm / °C). Then, through processes such as drilling, photolithography, electroplating, and resist removal etching, an external connection structure 90 is formed on the redistribution structure 60.

[0058] Step 7, back side thinning and final cutting: The back side of the molding compound 40 opposite to the side with the passivation layer 50 and the redistribution structure 60 is thinned until the solid insulating material film 80 in the groove 70 is flush with the back side of the molding compound 40, exposing the solid insulating material film 80 in the groove 70.

[0059] Step eight involves a final cut of the structure filled with the solid insulating material film 80. The final cut is performed along the width of the groove 70, with the cutting path essentially overlapping the pre-cutting path. This ensures that the solid insulating material film 80 remains on the sides of each obtained individual chip 100, forming a single-chip packaged product with six sides encapsulated. The final cut width is 15 μm. By using the difference between the pre-cut width and the final cut width, the thickness of the solid insulating material film 80 (side protective layer) covering the sides of the chip 100 is precisely controlled to be 10 μm.

[0060] like Figure 8 As shown, the semiconductor board-level package structure prepared by the packaging process of this embodiment includes: a chip 100 having a front and a back side facing each other and four sides connecting the front and back sides; a molding compound 40 covering the back side of the chip 100; a passivation layer 50 and a redistribution structure 60 disposed on the front side of the chip 100; and a solid insulating material film 80 covering the passivation layer 50 and the redistribution structure 60 and extending to the side areas of the chip 100, forming a side protection layer at the side positions of the chip 100. The front, back, and four sides of the chip 100 are respectively covered by the solid insulating material film 80 located on the passivation layer 50 and the redistribution structure 60, the molding compound 40 located on the back side, and the solid insulating material film 80 located on the sides, forming a six-sided package structure.

[0061] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, it is intended that all variations falling within the meaning and scope of equivalents of the claims be included within the present invention.

[0062] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A semiconductor board-level packaging process, characterized in that, Includes the following steps: A molding substrate is provided, on which multiple wafers to be diced into chips are temporarily bonded, face down. Board-level molding is performed to form a molding compound that covers all wafers; Remove the plastic-encapsulated substrate to expose the front side of the wafer; A passivation layer and redistribution structure are formed on the exposed wafer; Pre-cut along the wafer dicing path to form a groove with a depth greater than the chip thickness; A solid insulating material film is pressed onto the side having the passivation layer and redistribution structure using a vacuum pressing process, and the solid insulating material film is pressed and flowed in a vacuum environment to fill the groove. The back side of the encapsulation opposite to the side where the passivation layer and redistribution structure are formed is thinned until the solid insulating material film in the groove is exposed; The structure filled with the solid insulating material film is then cut to ensure that the solid insulating material film remains on the sides of each obtained single chip, forming a single product that is packaged on all six sides.

2. The semiconductor board-level packaging process according to claim 1, characterized in that, After removing the molding substrate and before thinning the back side of the molding compound, the method further includes: providing a support structure on the back side of the molding compound, the support structure being a support substrate bonded by temporary bonding technology or a structure bonded back-to-back with another molding compound; and before performing the back side thinning process, releasing the temporary bonding relationship between the support structure and the molding compound.

3. The semiconductor board-level packaging process according to claim 1, characterized in that, The step of forming a passivation layer and redistribution structure on the exposed wafer includes: An insulating material is laminated onto the front side of the wafer and then baked to form a passivation layer. Laser ablation technology is used to form openings on the passivation layer at the locations corresponding to the chip pads. A rewiring structure electrically connected to the pads is formed through physical vapor deposition, photolithography, electroplating, and etching processes.

4. The semiconductor board-level packaging process according to claim 1, characterized in that, After forming the solid insulating material film, the process further includes a step of constructing a multilayer redistribution structure and / or forming an external connection structure through a patterned electroplating process.

5. The semiconductor board-level packaging process according to claim 1, characterized in that, The thickness of the solid insulating material film covering the final chip side is adjusted by controlling the difference between the pre-cut width and the final cut width.

6. The semiconductor board-level packaging process according to claim 1, characterized in that, The groove formed by the pre-cutting is located either inside the molding compound or inside the wafer, depending on the location of the cut track. Specifically, in the cut track region between adjacent wafers, the groove is formed inside the molding compound; in the cut track region inside the wafer, the groove is formed inside the wafer.

7. The semiconductor board-level packaging process according to claim 1, characterized in that, The coefficient of thermal expansion of the solid insulating material film is lower than that of the material forming the encapsulation.

8. The semiconductor board-level packaging process according to claim 1, characterized in that, The encapsulated substrate has a releasable temporary bonding layer, which is released from the bond by thermal release, photorelease, or mechanical peeling when the encapsulated substrate is removed.

9. The semiconductor board-level packaging process according to claim 1, characterized in that, When thinning the back side of the encapsulant, the thinning is performed until the solid insulating material film in the groove is flush with or slightly lower than the back side of the encapsulant.

10. A semiconductor board-level packaging structure, characterized in that, include: The chip has a front and a back side, as well as four sides connecting the front and the back side; A molding compound that covers the back side of the chip; A passivation layer and a redistribution structure are disposed on the front side of the chip; A solid insulating material film is applied to the passivation layer and the redistribution structure, and extends to the side region of the chip, forming a side protective layer on the side of the chip. The chip's front, back, and four sides are covered by solid insulating material films located on the passivation layer and redistribution structure, a molding compound on the back, and solid insulating material films on the sides, forming a six-sided encapsulation structure.

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