Method of manufacture and MEMS corner reflector array

Abstract

The application discloses a manufacturing method and a MEMS corner reflector array. The application adopts ICP etching method to etch the front and back surfaces of a silicon wafer, realizes a deep cavity with high inner wall perpendicularity, and can form a high-perpendicularity reflecting surface. The application bonds a light-transmitting cover plate to protect the light-transmitting window. Based on the light-transmitting cover plate, self-mask photolithography and stripping can be realized, the composite metal layer is uniformly sputtered to the inner wall of the deep cavity, and the uniform metallization of the perpendicular reflecting surface is ensured. The application has simple process, wafer-level integrated process in the whole flow, and is compatible with CMOS process, and is suitable for mass production.

Description

Technical Field

[0001] This invention relates to a manufacturing method and a MEMS corner reflector array, belonging to the field of microelectromechanical systems (MEMS) manufacturing technology. Background Technology

[0002] Corner reflectors, as typical retroreflective optical devices, rely on three mutually perpendicular reflective surfaces to reflect light incident at any angle back along its original path. They possess core advantages such as passive operation, strong anti-interference capability, and stable retroreflection direction, and are widely used in fields such as lidar ranging, satellite laser communication, radar and microwave, transportation and security, aircraft attitude sensing, precision optical inspection, and high-end anti-counterfeiting. Traditional macroscopic corner reflectors are mostly made of materials such as glass and metal, which have drawbacks such as large size, heavy weight, high integration difficulty, and high mass production cost, making them unsuitable for the application requirements of miniaturized, integrated, and lightweight optoelectronic systems.

[0003] With the rapid development of Micro Electro-Mechanical Systems (MEMS) technology, MEMS corner reflector arrays based on semiconductor micro-nano fabrication processes have achieved miniaturization, lightweighting, electrically controllable modulation, arraying, and wafer-level mass production, becoming a core solution to overcome the application limitations of traditional devices. However, current mainstream MEMS corner reflector fabrication technologies still face many technical bottlenecks. For example, the KOH wet anisotropic etching process is limited by the silicon crystal orientation, resulting in poor perpendicularity of the reflecting surface; and the conventional DRIE (Deep Reactive Ion Etching) dry etching process is prone to sidewall tilting. Therefore, a new manufacturing method is urgently needed. Summary of the Invention

[0004] This invention provides a manufacturing method and a MEMS corner reflector array, which solves the problems disclosed in the background art.

[0005] According to one aspect of this application, a manufacturing method is provided for fabricating a MEMS corner reflector array, the method comprising: Using the protective mechanism of photoresist, the oxide layer in the unprotected front window of the silicon wafer is removed, and a shallow cavity is etched on the front side of the silicon wafer with the oxide layer removed using the ICP etching method. Using the protective mechanism of photoresist, the remaining oxide layer on the front side of the silicon wafer is removed, the oxide-free front side of the silicon wafer is bonded to the light-transmitting cover plate, and a mask layer is sputtered on the back side of the silicon wafer. Using the protection mechanism of photoresist, the mask layer and oxide layer in the unprotected back window on the back of the silicon wafer are removed, and the ICP etching method is used to etch the back of the silicon wafer after removing the mask layer and oxide layer until it connects with the shallow cavity to form a deep cavity. Remove the remaining mask layer and oxide layer on the back of the silicon wafer, apply photoresist to the back of the silicon wafer, expose the photoresist from the bottom of the deep cavity on the side of the light-transmitting cover plate, and leave a photoresist layer at the bottom of the deep cavity after development. A composite metal layer is sputtered onto the back of a silicon wafer, and the photoresist layer with the sputtered composite metal layer is peeled off to form a MEMS vertical mirror structure layer. The side of the MEMS vertical mirror structure layer away from the light-transmitting cover is bonded to the MEMS planar mirror chip.

[0006] Furthermore, the etching conditions for the ICP etching method are as follows: RF power 550W~650W; during the etching process, SF6 flow rate 125sccm~135sccm, pressure 20mTorr~35mTorr, time 5s~7s; during the passivation process, C4F8 flow rate 80sccm~90sccm, pressure 12mTorr~20mTorr, time 2s~4s.

[0007] Furthermore, before applying photoresist to the back of the silicon wafer, the inner wall of the deep cavity of the silicon wafer, from which the mask layer and oxide layer have been removed, is sequentially subjected to plasma cleaning and chemical polishing.

[0008] Furthermore, the process parameters for plasma cleaning are: RF power 380W, oxygen flow rate 380sccm, and cleaning time 1h.

[0009] Furthermore, the light-transmitting cover is a glass cover; the front side of the silicon wafer with the oxide layer removed is bonded to the glass cover with silicon-glass bonding.

[0010] Furthermore, the silicon-glass bonding conditions are: temperature 350℃; pressure 5.0 × 10⁻⁶. -5 mbar, voltage 800V, bonding time 25min.

[0011] Furthermore, the sputtered composite metal layer includes a chromium layer and a gold layer sputtered sequentially, with the chromium layer serving as an adhesion layer for the gold layer; the side of the MEMS vertical mirror structure layer away from the light-transmitting cover plate is bonded to the MEMS planar mirror chip with gold-silicon bonding.

[0012] Furthermore, the gold-silicon bonding conditions are: temperature 420℃; bonding pressure 3000 Torr; vacuum degree 10 m Torr; time 60 minutes.

[0013] Furthermore, the mask layer is an aluminum layer.

[0014] According to another aspect of this application, a MEMS corner reflector array is provided, which is fabricated using the method described above.

[0015] The beneficial effects achieved by this invention are as follows: 1. This invention uses ICP etching to etch the front and back sides of the silicon wafer, achieving a deep cavity with high verticality of the inner wall, thereby forming a high-verticality reflective surface. Furthermore, this invention uses a bonding light-transmitting cover plate to protect the light-transmitting window. Based on the light-transmitting cover plate, self-mask lithography and stripping can be achieved, uniformly sputtering the composite metal layer onto the inner wall of the deep cavity, ensuring uniform metallization of the vertical reflective mirror surface; 2. This invention has a simple process, a fully integrated wafer-level process, is compatible with CMOS processes, and is suitable for mass production. Attached Figure Description

[0016] Figure 1 A flowchart of the manufacturing process; Figure 2 A schematic diagram of a silicon wafer with surface oxidation; Figure 3 A schematic diagram showing the front side of a silicon wafer after photoresist has been applied. Figure 4 This is a schematic diagram showing the oxide layer removed from the front window. Figure 5 This is a schematic diagram after etching the shallow cavity; Figure 6 A schematic diagram showing the silicon wafer after removing photoresist from the front side and applying photoresist to the back side; Figure 7 This is a schematic diagram showing the silicon wafer after the oxide layer on the front side has been removed. Figure 8 This is a schematic diagram after the light-transmitting cover plate has been bonded; Figure 9 This is a schematic diagram showing the back of a silicon wafer after a sputtering mask layer has been applied. Figure 10 A schematic diagram showing the photoresist coating on the mask layer; Figure 11 This is a schematic diagram showing the mask layer and oxide layer after removal from the rear window. Figure 12 This is a schematic diagram showing the formation of the deep cavity; Figure 13 This is a schematic diagram showing the silicon wafer after the mask layer and oxide layer on the back side have been removed. Figure 14 A schematic diagram showing the back of a silicon wafer after photoresist has been applied. Figure 15 This is a schematic diagram after exposure and development; Figure 16 This is a schematic diagram after sputtering the composite metal layer; Figure 17 This is a schematic diagram after the photoresist layer has been peeled off. Figure 18 This is a schematic diagram of the MEMS vertical mirror structure layer before bonding to the MEMS planar mirror chip. Figure 19This is a schematic diagram of the bonding between the MEMS vertical mirror structure layer and the MEMS planar mirror chip. Figure 20 This is a schematic diagram of a single unit structure in a MEMS corner reflector array. Detailed Implementation

[0017] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this application or its application or use. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0018] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps described in these embodiments do not limit the scope of this application.

[0019] At the same time, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn according to actual scale.

[0020] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0021] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0022] It should be noted that similar symbols and letters in the accompanying drawings represent similar items; therefore, once an item is defined in one accompanying drawing, it does not need to be discussed further in subsequent accompanying drawings.

[0023] See Figure 1 , Figure 1 This is a flowchart of a manufacturing method provided in an embodiment of this application. This method can be used to fabricate a MEMS corner reflector array, and the steps of the method may include at least: Step 1: Using the protection mechanism of photoresist 3, the oxide layer 2 in the unprotected front window of the silicon wafer 1 is removed, and a shallow cavity 4 is etched on the front side of the silicon wafer 1 after removing the oxide layer 2 using the ICP etching method.

[0024] It should be noted that the protection mechanism of photoresist 3 is to use photoresist 3 as a selective mask to protect the underlying structure from being etched.

[0025] The specific process of step 1 can be as follows: 11) Prepare double-sided polished silicon wafers, such as N(100) silicon wafers, and perform surface inspection, cleaning and other treatments.

[0026] 12) A dense layer of silicon dioxide of approximately 1200 Å is formed on the surface of silicon wafer 1 through dry oxidation. For details, please refer to [link to relevant documentation]. Figure 2 .

[0027] 13) The oxidized silicon wafer 1 surface is cleaned, bonded, coated with photoresist 3, pre-baked, exposed, developed, and post-baked to form an unprotected front window on the front side of the silicon wafer 1; see [reference needed]. Figure 3 Except for the front window portion, the remaining portion of the front side of the silicon wafer 1 is uniformly coated with photoresist 3; the position and size of the front window are determined according to the actual situation.

[0028] 14) The oxide layer 2 inside the front window is etched using a plasma etching machine or a hydrofluoric acid wet etching process; the structure after removing the oxide layer 2 inside the front window can be found in [reference needed]. Figure 4 .

[0029] 15) Using ICP (Inductively Coupled Plasma) etching, a shallow cavity 4 is etched on the front side of the silicon wafer 1 after removing the oxide layer 2. Specifically, approximately 2μm of silicon can be etched to form a cavity 4. Figure 5 The shallow cavity 4 shown is used in the ICP etching method. The etching conditions are as follows: RF power 550W~650W; during etching, SF6 flow rate 125sccm~135sccm, pressure 20mTorr~35mTorr, time 5s~7s; during passivation, C4F8 flow rate 80sccm~90sccm, pressure 12mTorr~20mTorr, time 2s~4s. The preferred conditions are: RF power 600W; during etching, SF6 flow rate 130sccm, pressure 28mTorr, time 6s; during passivation, C4F8 flow rate 85sccm, pressure 17mTorr, time 3s.

[0030] By optimizing the ICP etching method, the loading effect can be effectively reduced, the etching accuracy can be improved, the etching rate can be kept uniform, and the microstructure processing of ultra-smooth, highly perpendicular reflective surfaces can be achieved.

[0031] Step 2: Using the protective mechanism of photoresist 3, remove the remaining oxide layer 2 on the front side of silicon wafer 1, bond the front side of silicon wafer 1 with oxide layer 2 removed to the light-transmitting cover plate 5, and sputter a mask layer 6 on the back side of silicon wafer 1.

[0032] Step 2 can be described as follows: 21) Remove the photoresist 3 from the front side of silicon wafer 1 and apply photoresist 3 to the back side of silicon wafer 1, thus forming a protective layer of photoresist 3 on the back side. For details, please refer to [link to documentation]. Figure 6 .

[0033] 22) See Figure 7 Hydrofluoric acid wet etching can be used to etch the oxide layer 2 that is not protected by photoresist 3, that is, to remove the remaining oxide layer 2 on the front side of silicon wafer 1.

[0034] 23) See also Figure 8 A glass cover plate (such as a Pyrex 7740 glass cover plate) is used as the light-transmitting cover plate 5. The silicon wafer 1 and the glass cover plate are surface cleaned and pretreated, and then silicon-glass bonding is performed. Specifically, the two are placed in a bonding machine for silicon-glass bonding. The silicon-glass bonding conditions are: temperature 350℃; pressure 5.0×10⁻⁶. -5 mbar, voltage 800V, bonding time 25min.

[0035] 24) The silicon-glass bonded structure is cleaned, and a mask layer 6 is sputtered onto the back side of silicon wafer 1; wherein, the mask layer 6 can be an aluminum layer, see [reference needed]. Figure 9 It can sputter an aluminum layer approximately 1.2 μm thick.

[0036] Step 3: Using the protection mechanism of photoresist 3, the mask layer 6 and oxide layer 2 in the unprotected back window of the back side of silicon wafer 1 are removed, and ICP etching is used to etch the back side of silicon wafer 1 after removing the mask layer 6 and oxide layer 2 until it connects with the shallow cavity 4 to form a deep cavity 7.

[0037] The specific process of step 3 can be as follows: 31) Similar to 13), the surface of the structure obtained in 24) is cleaned, bonded, coated with photoresist 3, pre-baked, exposed, developed, and post-baked to form an unprotected back window in the mask layer 6; see also Figure 10 Except for the back window portion, the rest of the mask layer 6 is uniformly coated with photoresist 3; the back window faces the front window, and the two are the same size.

[0038] 32) The aluminum layer inside the back window was etched using a wet etching process with a mixture of phosphoric acid, nitric acid, and acetic acid, and the oxide layer 2 inside the window was etched using a wet etching process with hydrofluoric acid; the structure after etching can be found in [reference needed]. Figure 11 .

[0039] 33) Using ICP (Inductively Coupled Plasma) etching, etching is performed on the back side of the silicon wafer 1 after the aluminum layer and oxide layer 2 have been removed, etching to form a deep cavity 7 that communicates with the shallow cavity 4, as detailed below. Figure 12 As shown; wherein, the etching conditions of the ICP etching method are the same as those in step 15).

[0040] Step 4: Remove the remaining mask layer 6 and oxide layer 2 on the back of silicon wafer 1. Apply photoresist 3 to the back of silicon wafer 1. Expose the photoresist 3 (specifically negative photoresist) at the bottom of deep cavity 7 from the side of the light-transmitting cover plate 5. Due to the short exposure time and the vertical morphology of the inner wall of deep cavity 7, the photoresist on the side wall is not exposed. After development, a layer of photoresist 3 remains at the bottom of deep cavity 7.

[0041] See Figure 13 To remove the photoresist 3, aluminum layer, and oxide layer 2 from the back of silicon wafer 1, and to reduce the roughness of the inner wall of deep cavity 7, a plasma cleaner is used to sequentially perform plasma cleaning and chemical polishing on the inner wall of deep cavity 7. The plasma cleaning is used to remove the polymer from the inner wall of deep cavity 7, and the process parameters can be: RF power 380W, oxygen flow rate 380sccm, and cleaning time 1h. The chemical polishing can use potassium oxide-isopropanol solution to further reduce the roughness.

[0042] See Figure 14 A photoresist 3 with a thickness of approximately 2 μm can be coated on the back side of silicon wafer 1. Exposure is performed from the glass cover side. Because the glass cover is transparent, the photoresist 3 in the transparent area is exposed, while the photoresist 3 in other areas is not exposed due to the blocking effect of silicon. After development, a photoresist 3 layer is formed at the bottom of the deep cavity 7. (See [reference needed]). Figure 15 .

[0043] Step 5: Sputter a composite metal layer on the back side of silicon wafer 1, and peel off the photoresist layer 3 with the sputtered composite metal layer to form a MEMS vertical mirror structure layer.

[0044] The structure after sputtering the composite metal layer can be seen in Figure 16 The sputtered composite metal layer includes a chromium layer 8 and a gold layer 9 sputtered sequentially. The chromium layer 8 serves as an adhesion layer for the gold layer 9, and the thickness of the chromium layer 8 is approximately 0.1 to 0.3 micrometers. The gold layer 9 serves as a reflective surface, and the thickness is approximately 0.3 to 0.7 micrometers.

[0045] See Figure 17 The chromium layer 8, gold layer 9 and photoresist 3 are stripped off. Specifically, the photoresist 3 is directly removed, and the excess chromium layer 8 and gold layer 9 on the photoresist 3 are stripped off to form the first reflective surface A and the second reflective surface B (i.e., the vertical reflective surface) of the MEMS vertical reflective mirror structure layer.

[0046] It should be noted that all the layers in the attached figures, namely chromium layer 8, gold layer 9, and photoresist 3, are very thin layers. To clearly show the structure, each layer has been magnified in the figures. Figure 17 After the photoresist 3 is stripped away, the composite metal layer on the inner wall of the deep cavity 7 extends all the way to the bottom of the deep cavity 7.

[0047] Step 6: Bond the side of the MEMS vertical mirror structure layer away from the light-transmitting cover plate 5 to the MEMS planar mirror chip 10.

[0048] The vertical reflective surface and the MEMS planar reflective chip 10 undergo inspection, cleaning, and preprocessing. (See also...) Figure 18 and Figure 19 The side of the MEMS vertical reflector structure layer away from the light-transmitting cover plate 5 is bonded to the MEMS planar reflector chip 10 with gold-silicon. The gold-silicon bonding conditions are: temperature 420℃; bonding pressure 3000 Torr; vacuum degree 10 m Torr; time 60 minutes.

[0049] The above method employs ICP etching to perform shallow cavity 4 etching on the front side of silicon wafer 1, defining the final optical window area, and forming two perpendicular reflective surfaces during deep cavity 7 etching. After bonding the front side of silicon wafer 1 to the glass cover plate, the back side of silicon wafer 1 is patterned. ICP etching is then used to vertically etch the pattern on the back side of silicon wafer 1 to remove non-connected portions of the window area. Furthermore, to reduce scattering loss, a plasma cleaner is first used to perform plasma cleaning on the surface of the perpendicular reflector to remove the deep reactive ion etching residues on the sidewall surfaces. The polymer is then used; then, the two vertical mirrors are anisotropically etched and polished using a potassium hydroxide-isopropanol (KOH-IPA) solution to further reduce the sidewall roughness; photoresist 3 is sprayed onto the remaining vertical structure, and the silicon structure is used as a self-mask for exposure from the glass cover side; after metal sputtering and stripping processes, the top and sidewalls of the mirrors are metallized, while the uncoated transparent windows are retained. These integrated vertical reflective surfaces are then bonded to the glass cover to the MEMS planar reflector chip 10 to complete the MEMS corner reflector array packaging.

[0050] The above method uses ICP etching to etch both sides of the silicon wafer 1, achieving a deep cavity 7 with high inner wall verticality, thereby forming a highly vertical reflective surface. Furthermore, a light-transmitting cover plate 5 is bonded to protect the light-transmitting window. Based on the light-transmitting cover plate 5, self-mask lithography and stripping can be achieved to uniformly sputter the composite metal layer onto the inner wall of the deep cavity 7, ensuring uniform metallization of the vertical reflective mirror surface. The above method is simple, a fully integrated wafer-level process, compatible with CMOS processes, and suitable for mass production.

[0051] Based on the above method, this application also discloses a MEMS corner reflector array, specifically fabricated using the above method. The structure of a single unit in the MEMS corner reflector array can be found in [reference needed]. Figure 20The structure consists of three layers. The top layer is a glass cover, which serves as the light-transmitting window for the MEMS corner reflector array, allowing light to enter while protecting and sealing it. The middle layer is a hollow structure containing two vertically aligned reflective surfaces in the MEMS corner reflector array, mainly composed of a first reflective surface A and a second reflective surface B in the vertical direction, both made up of composite metal layers. The bottom layer is the MEMS planar reflector chip 10 of the MEMS corner reflector array, including a planar reflector C, adjustable circuitry, interconnect leads, etc. The planar reflector C is the third reflective surface in the horizontal direction, composed of composite metal layers.

[0052] The above description is only a preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A manufacturing method, characterized in that, The method for fabricating a MEMS corner reflector array includes: Using the protective mechanism of photoresist, the oxide layer in the unprotected front window of the silicon wafer is removed, and a shallow cavity is etched on the front side of the silicon wafer with the oxide layer removed using the ICP etching method. Using the protective mechanism of photoresist, the remaining oxide layer on the front side of the silicon wafer is removed, the oxide-free front side of the silicon wafer is bonded to the light-transmitting cover plate, and a mask layer is sputtered on the back side of the silicon wafer. Using the protection mechanism of photoresist, the mask layer and oxide layer in the unprotected back window on the back of the silicon wafer are removed, and the ICP etching method is used to etch the back of the silicon wafer after removing the mask layer and oxide layer until it connects with the shallow cavity to form a deep cavity. Remove the remaining mask layer and oxide layer on the back of the silicon wafer, apply photoresist to the back of the silicon wafer, expose the photoresist at the bottom of the deep cavity from the light-transmitting cover side, and after development, a photoresist layer remains at the bottom of the deep cavity. A composite metal layer is sputtered onto the back of a silicon wafer, and the photoresist layer with the sputtered composite metal layer is peeled off to form a MEMS vertical mirror structure layer. The side of the MEMS vertical mirror structure layer away from the light-transmitting cover is bonded to the MEMS planar mirror chip.

2. The method according to claim 1, characterized in that, The etching conditions for the ICP etching method are: RF power 550W~650W; During the etching process, the SF6 flow rate is 125 sccm~135 sccm, the pressure is 20 mTorr~35 mTorr, and the time is 5 s~7 s; during the passivation process, the C4F8 flow rate is 80 sccm~90 sccm, the pressure is 12 mTorr~20 mTorr, and the time is 2 s~4 s.

3. The method according to claim 1, characterized in that, Before applying photoresist to the back of the silicon wafer, the inner wall of the deep cavity of the silicon wafer, from which the mask layer and oxide layer have been removed, is sequentially subjected to plasma cleaning and chemical polishing.

4. The method according to claim 3, characterized in that, The process parameters for plasma cleaning are: RF power 380W, oxygen flow rate 380sccm, and cleaning time 1h.

5. The method according to claim 1, characterized in that, The light-transmitting cover is a glass cover; the front side of the silicon wafer with the oxide layer removed is bonded to the glass cover with silicon-glass bonding.

6. The method according to claim 5, characterized in that, The conditions for silicon-glass bonding are: temperature 350℃; pressure 5.0×10⁻⁶. -5 mbar, voltage 800V, bonding time 25min.

7. The method according to claim 1, characterized in that, The sputtered composite metal layer consists of a chromium layer and a gold layer sputtered sequentially, with the chromium layer serving as an adhesion layer for the gold layer; the side of the MEMS vertical mirror structure layer away from the light-transmitting cover plate is bonded to the MEMS planar mirror chip with gold-silicon bonding.

8. The method according to claim 7, characterized in that, The gold-silicon bonding conditions were: temperature 420℃; bonding pressure 3000 Torr; vacuum degree 10 m Torr; time 60 minutes.

9. The method according to claim 1, characterized in that, The mask layer is an aluminum layer.

10. A MEMS corner reflector array, characterized in that, Prepared by the method described in any one of claims 1 to 9.

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