Methods for the production of silicon epitaxial wafers
Patent Information
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- SUMCO CORP
- Filing Date
- 2016-04-05
- Publication Date
- 2026-07-02
AI Technical Summary
Existing methods for manufacturing silicon epitaxial wafers with low substrate resistivity struggle to sufficiently restrict the generation of stacking faults (SF) in a simple manner, particularly when using silicon wafers doped with phosphorus, which often result in surface defects.
A manufacturing method involving argon annealing followed by a pre-baking treatment in a hydrogen and hydrogen chloride gas atmosphere is employed to etch the outer layer of silicon wafers, reducing clusters and micropits, thereby minimizing the generation of SF.
This method effectively reduces the number of SF on silicon epitaxial wafers to a negligible level, ensuring high-quality production without complex temperature regulation, even with extremely low resistivity wafers.
Abstract
Description
TECHNICAL AREA
[0001] The present invention relates to a manufacturing method of a silicon epitaxial wafer. BACKGROUND ART
[0002] For example, silicon epitaxial wafers for power MOS transistors must have an extremely low substrate resistivity. In order to lower the substrate resistivity of silicon wafers sufficiently, it is known to mix molten silicon with an n-type resistivity adjustment dopant (e.g., arsenic (As) and antimony (Sb)) during a pull-up step (i.e., in a growing silicon crystal). to dope single crystal ingots for providing silicon wafers (hereinafter referred to as a single crystal ingot). Since such dopants are extremely volatile, it is difficult to sufficiently increase the dopant concentration in silicon crystals. Thus, it is difficult to manufacture silicon wafers having the desired sufficiently low resistivity.
[0003] Accordingly, silicon wafers with extremely low substrate resistivity have come into use in which phosphorus (P), an n-type dopant that is less volatile than arsenic (As) and antimony (Sb), is doped at a high concentration (see, for example, Patent Literature 1 and 2).
[0004] Patent Literature 1 and 2 disclose that when an epitaxial layer is grown on a silicon wafer that has been heavily doped with phosphorus, a number of stacking faults (hereinafter abbreviated as "SF") are generated on the epitaxial layer, with the SF on the surface of the Silicon wafers appear in a form of steps to significantly deteriorate the level of LPD (Light Point Defects) on the surface of the silicon wafer. The reasons for the generation of SF are conjectured as follows.
[0005] The silicon wafer, which has been doped with phosphorus, is first heated, resulting in the formation of clusters (microprecipitates) of oxygen and phosphorus. Then, the silicon wafer is subjected to a heat treatment (hereinafter referred to as “hydrogen baking”) in a hydrogen gas atmosphere to remove a natural oxide film present on the surface of the silicon wafer. The clusters are preferentially etched to provide micropits by an etching action of the hydrogen gas due to a difference in an etching rate between the outermost layer of the silicon wafer and the clusters. It is conjectured that when the silicon wafer provided with the micro-cavities undergoes epitaxial growth, SF are generated in the epitaxial layers originating from the micro-cavities.
[0006] Accordingly, Patent Literature 1, which focuses on a correlation between the solidification rate and thermal hysteresis of a single crystal ingot and generation of SF, discloses a manufacturing method in which generation of SF is restricted by controlling a period of time when the temperature of the single crystal ingot is in a range of 570 ± 70°C during the pull-up step.
[0007] Furthermore, Patent Literature 2 discloses a manufacturing method in which the generation of SF is restricted by subjecting a silicon wafer to a heat treatment before forming an epitaxial layer in an argon gas atmosphere (hereinafter referred to as “subjected to an argon anneal treatment”) in order to reduce the clusters on the outer layer to make into a solid solution. CITATION LIST PATENT LITERATURE(S)
[0008] Patent Literature 1: WO 2014 / 175120 Patent Literature 2: JP 2014-11293 A SUMMARY OF THE INVENTION PROBLEM(S) TO BE SOLVED BY THE INVENTION
[0009] However, the manufacturing method as disclosed in Patent Literature 1 may require complicated temperature regulation during the pulling-up step of the single crystal ingot.
[0010] Further, it has been found that the manufacturing method as disclosed in Patent Literature 2, which can be used to meet a recent growing demand for silicon wafers with a low substrate resistivity, sometimes fails to sufficiently restrict the generation of SF on the manufactured silicon epitaxial wafers.
[0011] An object of the invention is to provide a manufacturing method of a silicon epitaxial wafer, the method being capable of sufficiently restraining the generation of SF in a simple manner regardless of the use of a silicon wafer having an extremely low resistivity. MEANS TO SOLVE THE PROBLEM(S).
[0012] After intensive investigations, the inventors have found the following.
[0013] Since it was proved that there is a correlation between the solidification rate and the thermal hysteresis of a single-crystal ingot and the generation of SF as described in Patent Literature 1, the inventors first conducted experiments to examine the influence of the resistivity of the single-crystal ingot on the correlation . Experiment 1: Investigation on the correlation between resistivity / solidification rate / thermal hysteresis of single crystal ingots and generated SF number.
[0014] In a manufacturing process of an ordinary single crystal ingot, a step of forming a shoulder continuous with a seed crystal and having a gradually increasing diameter (shoulder forming step), a step of forming a straight body continuous with the shoulder, and a substantially constant diameter (straight body forming step) and a step of forming a tail continuous with a lower end of the straight body and having a diameter gradually reduced to zero (tail forming step) are performed. After the tail forming step is completed, a step of cooling the single crystal ingot (cooling step) is performed, and the single crystal ingot is taken out from a pull-up jig.
[0015] Since the single crystal ingot undergoes the above manufacturing process, it is inferred that the time elapsed after it is pulled from the dopant-added melt becomes shorter toward a lower end (bottom) of the single crystal ingot (i.e., as the solidification rate increases) . Incidentally, the solidification rate refers to a ratio of the pulled-up weight of the single crystal ingot relative to an initial charge weight of a dopant-added melt initially stored in a quartz crucible.
[0016] Initially, single crystal ingots of Experimental Examples 1 and 2 were manufactured according to the above manufacturing process, and a residence time at 570±70°C for each of the solidification rates was measured as a thermal hysteresis. To prepare the single crystal ingots of Experimental Examples 1 and 2, red phosphorus (dopant) was added to the silicon melt to provide the dopant-added melt so that the substrate resistivity of silicon wafers became such as shown in Table 1 below. Incidentally, a loading amount of the dopant-added melt was set to 100 kg as in an ordinary manufacturing process. Table 1 top floor Experimental example 1 1.1mΩ·cm 0.7mΩ·cm Experimental example 2 0.9mΩ·cm 0.6mΩ·cm
[0017] In addition, silicon wafers corresponding to the plurality of solidification rates were cut from the single crystal ingots of Experimental Examples 1 and 2 to prepare silicon epitaxial wafers, and the SF number of each of the silicon epitaxial wafers was counted. figure 1 shows the results of Experimental Example 1 and figure 2 shows the results of Experimental Example 2. Incidentally, the SF number means the counted number of LPDs (Light Spot Defects) of a size of 90 nm or more observed on a surface of each silicon epitaxial wafer when the surface was inspected with a surface inspection system (DCN mode of SP-1 manufactured by KLA-Tencor Corporation).
[0018] It should be noted that the results in figure 1 and figure 2 show the SF number counted on an epitaxial layer formed under the following conditions on the silicon wafers provided without a polysilicon film on a back side thereof, the silicon wafers having been subjected to a hydrogen baking treatment in which the silicon wafers are at a temperature of 1200°C in a hydrogen gas atmosphere for 30 seconds. epitaxial layer growth conditions Dopant gas: phosphine gas (PH 3 -Gas) Material source gas: Trichlorosilane gas (SiHCl 3 -Gas) Carrier gas: hydrogen gas Growth temperature: 1080ºC Epitaxial layer thickness: 4 μm Specific resistance (resistivity of the epitaxial layer): 0.3 Ω·cm
[0019] As in figure 1, it was found in Experimental Example 1 that the SF number substantially correlates with the residence time of the single crystal ingot at the temperature of 570±70°C and the SF number becomes zero at a portion where the solidification rate is more than 70% . In contrast, in Experimental Example 2, it was found that while the SF number substantially correlates with the residence time of the single crystal ingot at the temperature of 570±70°C at a portion where the solidification rate is 75% or less, the SF number increases toward the bottom at a portion where the solidification rate exceeds 75% regardless of the residence time. Incidentally, the substrate resistivity at a position where the solidification rate was 75% was about 0.7 mΩ·cm.
[0020] In view of the above, it was found that SF increases in proportion to an increase in the red phosphorus concentration when the red phosphorus concentration is equal to or higher than a predetermined level, or im Ratio to a reduction in substrate resistivity increases when the substrate resistivity is equal to or lower than a predetermined level. Experiment 2: Study on the effectiveness of a heat treatment in a gas atmosphere containing hydrogen and hydrogen chloride for reducing SF
[0021] It is believed that micropits generated after the hydrogen baking treatment must be reduced in order to reduce the number of SF. In order to reduce the micropits, it is believed that a cluster elimination treatment must be applied before the hydrogen baking treatment in which the clusters are generated.
[0022] Accordingly, it was examined whether or not SF can be reduced by etching a cluster-containing outer layer having a predetermined thickness of a silicon wafer with the use of a hydrogen chloride gas in addition to a hydrogen gas for a pre-bake treatment before growing an epitaxial layer.
[0023] First, a single crystal ingot was prepared under the same conditions as in Experimental Example 2. A plurality of silicon wafers were cut out from the single crystal ingot at each center portion where the number of SF in the single crystal ingot is largest and a bottom portion where the number of SF increases toward the bottom.
[0024] The substrate resistivity at the center portion was more than 0.7 mΩ·cm but not more than 0.9 mΩ·cm, and the substrate resistivity at the bottom portion was not more than 0.7 mΩ·cm. It should be noted that the middle section is, for example, a section with a solidification rate ranging from 50% to 60% in figure 2 ranges, and the bottom portion is a portion having a solidification rate of 75% or more in figure 2 is
[0025] Next, the silicon wafers cut out from the center portion and the bottom portion were subjected to treatments as shown in Tables 2 and 3 to produce silicon epitaxial wafers of Experimental Examples 3 to 8, and the number of SF was evaluated. figure 3 shows the results of Experimental Examples 3 to 5 and figure4 shows the results of Experimental Examples 6 to 8. Note that an epitaxial layer was grown under the same conditions as Experimental Examples 1 and 2. FIG. It is also noted that the argon anneal treatment and the pre-bake treatment were performed without providing a polysilicon film on the back side of the silicon wafer. Table 2 Argon anneal A: done B: not performed pre-bake Section for cutting the silicon wafer Experimental example 3 B hydrogen center Experimental example 4 A hydrogen Experimental example 5 A hydrogen + hydrogen chloride Experimental example 6 B hydrogen floor Experimental example 7 A hydrogen Experimental example 8 A hydrogen + hydrogen chloride Table 3 the atmosphere heat treatment temperature heat treatment time Argon anneal argon gas 1200°C 30 minutes pre-bake (hydrogen) Hydrogen gas (flow: 40L / min) 1200°C 30 seconds Pre-bake (hydrogen + hydrogen chloride Hydrogen gas (flow: 40 L / min) Hydrogen chloride gas (flow: 1 L / min) 1190°C 30 seconds
[0026] In the figure 3 and figure The results shown in Figure 4 prove the following.
[0027] First, it is found that when Experimental Example 3 is compared with Experimental Example 6, the center portion has more SF than the bottom portion.
[0028] It is believed that this is because the cluster density of the center portion is higher than that of the bottom portion due to the influence of thermal hysteresis during the production of the single crystal ingot.
[0029] Next, when Experimental Examples 3 and 6 are compared with Experimental Examples 4 and 7, it was found that the silicon wafers subjected to the argon anneal treatment have less SF at both the center portion and the bottom portion than the silicon wafers subjected to the argon -Have not been subjected to tempering treatment.
[0030] The following reasons are conceived. First, as described in Patent Literature 2, the clusters present on the outer layer having the predetermined thickness are made into a solid solution to be reduced by the argon anneal treatment. Accordingly, it is considered that the number of clusters present on the outer layer after a pre-baking treatment in a hydrogen gas atmosphere is performed subsequent to an argon anneal treatment is reduced compared with a case without performing the argon anneal treatment, resulting in a reduction in the number of micro-pits generated after the pre-baking treatment, and consequently leads to a reduction in SF.
[0031] Further, when Experimental Example 4 is compared with Experimental Example 7, it is found that the bottom portion has less SF than the middle portion. More specifically, when the argon anneal treatment was performed, the number of SF fell in a range from 0.1 per square centimeter to 1.0 per square centimeter at the central portion of Experimental Example 4, and the number of SF fell below 0.1 per square centimeter at the Bottom section of experimental example 7.
[0032] It is believed that this is because the center portion has a higher cluster density than the bottom portion before the argon anneal treatment, and thus the number of clusters remaining on the outer layer at the center portion after the argon anneal treatment is larger. although the clusters are made into a solid solution by the argon anneal treatment, resulting in an increase in SF derived from the clusters.
[0033] Further, when Experimental Examples 4 and 7 are compared with Experimental Examples 5 and 8, it is found that the number of SFs obtained after performing a pre-baking treatment in a gas atmosphere containing hydrogen and hydrogen chloride (referred to as “a pre-baking treatment with hydrogen and hydrogen chloride”) referred to) is smaller at both the center portion and the bottom portion than the number of SF obtained after performing a pre-baking treatment in a gas atmosphere containing only hydrogen (i.e., referred to as “a pre-baking treatment using only hydrogen”).
[0034] The following reasons are conceived. First, in the pre-bake treatment with only hydrogen, the clusters present on the outermost layer of the silicon wafer are preferentially etched to become eminently observable as surface pits. In contrast, in the pre-bake treatment with hydrogen and hydrogen chloride, not only the clusters but also the outermost cluster are etched. Accordingly, it is considered that the pre-baking treatment with hydrogen and hydrogen chloride reduces the number of micropits generated after the pre-baking treatment compared with the pre-baking treatment with hydrogen only, and consequently reduces the number of SF.
[0035] Further, when Experimental Example 5 is compared with Experimental Example 8, it is found that the pre-baking treatment with hydrogen and hydrogen chloride reduces the SF at the center portion to a level comparable to the SF at the bottom portion. More specifically, when the pre-baking treatment was performed with hydrogen and hydrogen chloride, the number of SF was 0.02 per square centimeter or less at both the center portion and the bottom portion.
[0036] It is believed that this is because the number of micropits present on the outer layer after the pre-baking treatment becomes the same as long as the outer layer where the clusters are made into a solid solution by the argon anneal treatment , have a substantially uniform thickness regardless of the cluster density, and an allowance of the outer layer to be etched by the pre-bake treatment is smaller than the thickness of the outer layer where the clusters are made into a solid solution by the argon anneal treatment will.
[0037] Incidentally, the number of SF at the center portion, which is the largest in the single crystal ingot, can be reduced to 0.02 per square centimeter or less by the pre-baking treatment with hydrogen and hydrogen chloride, so that the number of SF on a silicon wafer is different from any other portion where single crystal ingot is cut out is to be reduced to a similar level by such pre-baking treatment.
[0038] The invention has been accomplished based on the above findings.
[0039] According to one aspect of the invention, there is provided a manufacturing method of a silicon epitaxial wafer comprising a silicon wafer doped with phosphorus and an epitaxial layer provided on a surface of the silicon wafer, the method comprising: forming an oxide layer on a back side of the silicon wafer composed of a layer formed by a Czochralski process produced single crystal ingot is excised; removing the oxide film present on an outer periphery of the silicon wafer; argon annealing in which the silicon wafer is subjected to a heat treatment in an argon gas atmosphere after removing the oxide layer; and forming the epitaxial layer on the surface of the silicon wafer after the argon anneal, the forming of the epitaxial layer comprising: a pre-bake in which the silicon wafer is subjected to heat treatment in a gas atmosphere comprising hydrogen and hydrogen chloride to etch an outer layer of the silicon wafer; and growing the epitaxial layer on the surface of the silicon wafer after the pre-bake.
[0040] According to the above aspect of the invention, the generation of SF can be sufficiently restricted in such a simple manner by additionally using a hydrogen chloride gas for a typical prebaking treatment with hydrogen only, regardless of the use of a silicon wafer having an extremely low resistivity. Example 3: Investigation on the correlation between allowance of an outer layer for pre-baking treatment with hydrogen and hydrogen chloride / growth temperature of epitaxial layer and generated SF number
[0041] The allowance of an outer layer taken by the pre-baking treatment with hydrogen and hydrogen chloride can be larger than the thickness of an outer layer where clusters are made into a solid solution by the argon anneal treatment. Such a new outer layer formed after the pre-baking treatment has clusters which are not made into a solid solution by the argon anneal treatment, and such clusters can be preferentially etched to form micropits from which SF are produced.
[0042] Accordingly, an experiment was conducted to determine an optimal value of allowance of the outer layer to be taken by the prebaking treatment with hydrogen and hydrogen chloride. In addition, another experiment was also conducted to determine an optimal value of the growth temperature of the epitaxial layer.
[0043] First, silicon wafers manufactured under the same conditions as in Experimental Example 3, i.e., a plurality of silicon wafers cut out from the central portion of the single crystal ingot in the same manner as in Experimental Example 2, were subjected to the argon annealing treatment under the same Subjected to conditions as in Experimental Example 5.
[0044] Next, the heat treatment time, the heat treatment temperature, the concentration of the hydrogen chloride gas and the like were adjusted in order to obtain silicon wafers having outer layers with an allowance of 50 nm, silicon wafers having outer layers with an allowance of 100 nm, silicon wafers having outer layers with to produce silicon wafers having outer layers with a stock of 180 nm, silicon wafers having outer layers with a stock of 290 nm, and silicon wafers having outer layers with a stock of 395 nm. It is also noted that the argon anneal treatment and the pre-bake treatment were performed without providing a polysilicon film on the back side of each silicon wafer.
[0045] Then, an epitaxial layer was grown on each of the silicon wafers having the above dimensions under the same conditions as in Experimental Example 2 except that the growth temperature was set at 1060 ºC, 1080 ºC and 1100 ºC to produce a silicon epitaxial wafer, and the number of SF was counted. The results will be in figure 5 shown.
[0046] As in figure 5, it was found that when an allowance is in a range from 100 nm to 300 nm, the number of SF becomes less than 0.1 per square centimeter regardless of the growth temperature for the epitaxial layers, proving that the generation of SF is sufficient can be restricted. In particular, it was found that when an allowance is equal to 150±10 nm, the number of SF becomes less than 0.01 per square centimeter.
[0047] It is believed that this is because an allowance less than 100 nm is smaller than a dimension in a depth direction of clusters present on the outer layer, and thus all of the clusters cannot be eliminated, resulting in the generation of Micropits resulting from the remaining clusters that have not been eliminated.
[0048] In contrast, an allowance exceeding 300 nm is larger than the thickness of the outer layer where the clusters are made into a solid solution by the argon anneal treatment, and thus some of the clusters not made into a solid solution by the argon annealing treatment remain argon anneal treatment, on a new outer layer formed after the pre-bake treatment, resulting in the creation of micro-pits resulting from the remaining clusters.
[0049] Furthermore, it was found out how figure 5 shows that when an allowance is in a range of 100 nm to 300 nm, for example, the number of SF becomes less than 0.1 per square centimeter at the growth temperature for the epitaxial layer of 100°C, and 0.06 per square centimeter or less at the growth temperature of 1080°C or 1060°C.
[0050] Further, it was found that when an allowance is in a range of 100 nm to 200 nm, the number of SF becomes 0.03 per square centimeter or less at the growth temperature of the epitaxial layer of 1080°C or 1060°C.
[0051] In view of the above, in the manufacturing method of the silicon epitaxial wafer according to the above aspect of the invention, it is preferable that the outer layer to be etched has a thickness ranging from 100 nm to 300 nm in the pre-baking.
[0052] In the manufacturing method of the silicon epitaxial wafer according to the above aspect of the invention, it is preferable that the heat treatment in the argon anneal is carried out in the argon gas atmosphere at a temperature ranging from 1150°C to 1250°C, and the heat treatment in the prebake in the hydrogen and a gas atmosphere comprising hydrogen chloride at a temperature ranging from 1050°C to 1250°C.
[0053] In the manufacturing method of the silicon epitaxial wafer according to the above aspect of the invention, it is preferable that the epitaxial layer growing step comprises growing the epitaxial layer at a temperature ranging from 1050°C to 1150°C, particularly at a temperature of 1080°C or less.
[0054] In the manufacturing method of the silicon epitaxial wafer according to the above aspect of the invention, it is preferable that the pre-baking step includes adding a hydrogen chloride gas to a hydrogen gas atmosphere having a temperature ranging from 1050°C to 1250°C to make the gas atmosphere containing the hydrogen and the hydrogen chloride .
[0055] It has been experimentally found that adding a hydrogen chloride gas to a hydrogen gas atmosphere having a temperature lower than 1050°C results in fogging of the silicon epitaxial wafer. Further, adding a hydrogen chloride gas to a hydrogen gas atmosphere having a temperature higher than 1250°C causes warping of the wafer due to a large thermal stress, and thus slip dislocation is likely to occur disadvantageously.
[0056] According to the above aspect of the invention, since the hydrogen chloride gas is added to the hydrogen gas atmosphere at a temperature ranging from 1050°C to 1250°C, the fogging of the silicon epitaxial wafer and the occurrence of slip dislocation can be restricted.
[0057] In the manufacturing method of the silicon epitaxial wafer according to the above aspect of the invention, a resistivity of the silicon wafer is preferably 1.5 mΩ·cm or less, more preferably 1.1 mΩ·cm or less, and particularly preferably 0.98 mΩ·cm or less . BRIEF DESCRIPTION OF THE DRAWING(S)
[0058] figure 1 is a graph of results of Experiment 1 for deriving a manufacturing condition of a silicon epitaxial wafer according to the invention, showing a relationship between a solidification rate and a thermal hysteresis of a single crystal ingot and a generated SF number in Experimental Example 1.
[0059] figure 2 is a graph of results of Experiment 1 showing a relationship between a solidification rate and thermal hysteresis of a single crystal ingot and a generated SF number in Experimental Example 2. FIG.
[0060] figure 3 is a graph of results of Experiment 2 for deriving the manufacturing condition, showing relationships between a solidification rate of a single crystal ingot and a generated SF number in Experimental Examples 3 to 5.
[0061] figure 4 is a graph of results of Experiment 2 showing relationships between a solidification rate of a single crystal ingot and a generated SF number in Experimental Examples 6 to 8. FIG.
[0062] figure 5 is a graph of results of Experiment 3 for deriving the manufacturing condition, showing a relationship between an etching allowance for a pre-baking treatment with hydrogen and hydrogen chloride and a generated SF number at each growth temperature for an epitaxial layer.
[0063] figure6 is a flow chart showing a manufacturing method of a silicon epitaxial wafer according to an exemplary embodiment of the invention. DESCRIPTION OF EMBODIMENT(S)
[0064] (An) exemplary embodiment(s) of the invention will be described below with reference to the accompanying drawings.
[0065] As in figure As shown in FIG. 6, a single crystal ingot manufacturing step (step S1) is performed in the manufacturing process of a silicon epitaxial wafer.
[0066] In the single crystal ingot manufacturing step, a single crystal ingot having a diameter of 200 mm is manufactured from a silicon melt added with red phosphorus (n-type dopant) according to the CZ method (Czochralski process) using a pull-up device (not shown). .
[0067] In this exemplary embodiment, the single crystal ingot is manufactured according to the following conditions so that the resistivity of silicon wafers cut out from the single crystal ingot falls within a range of 0.6 mΩ·cm to 0.98 mΩ·cm.
[0068] Red phosphorus concentration: 7.54 × 10 19 atoms / cm 3 or more and 1.32 × 10 20 atoms / cm 3 Or less Oxygen concentration: 7 × 10 17 atoms / cm 3 or more and 12 × 10 17 atoms / cm 3 Or less To limit misfit dislocation, germanium can be used from a concentration in a range of 3.70 × 10 19 atoms / cm 3 to 2.93×10 20 atoms / cm 3 to be added.
[0069] Subsequently, silicon wafers are cut out from the single-crystal ingot prepared in step S1, and each silicon wafer is subjected to a back surface oxide film formation step (step S2), a back surface oxide film removal step (step S3), an argon annealing step (step S4), a pre-baking step, the in a gas atmosphere containing hydrogen and hydrogen chloride (epitaxial layer forming step: step S5), and subjected to an epitaxial layer growing step (epitaxial layer forming step: step S6).
[0070] More specifically, in the back surface oxide film forming step of step S2, a back surface of each of the silicon wafers is subjected to treatment according to the following conditions with a normal pressure continuous CVD apparatus (AMAX1200 manufactured by Amaya Co., Ltd.) to form an oxide film ( hereinafter referred to as a backside oxide layer) on the backside of the silicon wafer. Material gas: Gas mixture of silane (SiH 4 ) and oxygen (O 2 ) Thickness of the back oxide layer: 550 nm (in a range from 100 nm to 1500 nm) Film formation temperature: 430ºC (in a range of 400 to 450ºC)
[0071] The formation of the backside oxide layer limits self-doping.
[0072] In the back surface oxide film removing step (step S3), the oxide film present on the outer periphery of the back surface of each of the silicon wafers is removed with the use of various methods including polishing and etching (see, for example, JP 2003-273063 A and JP 2011 -114210A). The oxide layer is preferably removed at an area less than 5 mm from an outer edge of each of the silicon wafers.
[0073] The removal of the backside oxide layer on the outer periphery of each of the silicon wafers limits the generation of so-called nodules.
[0074] In the argon annealing step (step S4), a batch furnace capable of annealing a plurality of silicon wafers at a single time is used to apply heat treatment according to the following conditions. Atmosphere: argon gas Heat treatment temperature: 1200ºC to 1220ºC (within a range of 1150 to 1250ºC) Heat treatment time: from 30 to 120 minutes
[0075] The argon annealing step allows clusters generated on each of the silicon wafers to be made into a solid solution and reduced.
[0076] Incidentally, the out-diffusion of red phosphorus is caused in the argon annealing step to form an out-diffusion layer of a thickness in a range of 0.65 μm to 0.91 μm on the surface of each of the silicon wafers, thereby increasing a width of a junction region increase. However, since the red phosphorus moves from a high-concentration area to a low-concentration area due to heat treatment(s) in the subsequent device production process, small problems arise.
[0077] In the pre-baking step in a gas atmosphere containing hydrogen and hydrogen chloride (step S5), a heat treatment is applied to each of the silicon wafers in an epitaxial growth apparatus according to the following conditions. Atmosphere: hydrogen gas and hydrogen chloride gas Flow rate of hydrogen gas: 40 liters per minute Hydrogen chloride gas flow rate: 1 liter per minute Heat treatment temperature: 1190ºC (in a range of 1050 to 1250ºC) Heat treatment time: 30 seconds (within a range of 30 to 300 seconds)
[0078] Incidentally, in order to make the gas atmosphere containing hydrogen and hydrogen chloride in the pre-baking step, it is preferable that a temperature in an atmosphere containing only a hydrogen gas is raised first and a hydrogen chloride gas is added when the temperature ranges from 1050°C to 1250°C achieved. The addition of the hydrogen chloride gas at such a timing can prevent the fogging of the silicon epitaxial wafer and restrain the occurrence of slip dislocation.
[0079] Further, an allowance of each of the silicon wafers for the pre-baking step is preferably in a range from 100 nm to 300 nm, more preferably equal to 150±10 nm.
[0080] In the epitaxial layer growth step (step S6), an epitaxial layer is grown according to the following conditions on each of the silicon wafers that have been subjected to the pre-baking step. Dopant gas: phosphine gas (PH 3 -Gas) Material source gas: Trichlorosilane gas (SiHCl 3 -Gas) Carrier gas: hydrogen gas Growth temperature: 1060ºC (in a range of 1050 to 1150ºC) Epitaxial layer thickness: 4 μm (in a range from 1 μm to 10 μm) Resistivity (resistivity of epitaxial layer): 0.3 Ω cm (in a range of 0.01 to 10 Ω cm) Red phosphorus concentration: 1.87 × 10 16 atoms / cm 3 (in an area of 4.44 × 10 14 atoms / cm 3 to 4.53×10 18 atoms / cm 3 )
[0081] With the epitaxial layer growth step being performed, an epitaxial silicon wafer having an epitaxial layer formed on the surface of each of the silicon wafers can be manufactured.
[0082] The silicon wafers may have clusters before undergoing the backside oxide layer formation step. Even in such a case, the outer layer having the predetermined thickness as well as the clusters are etched through the argon annealing step and the pre-baking step in the gas atmosphere containing hydrogen and hydrogen chloride. The number of SF produced on the resulting silicon epitaxial wafers can thus be reduced in such a simple manner by additionally using the hydrogen chloride gas for a typical pre-bake treatment with only hydrogen compared to silicon wafers subjected to the typical pre-bake treatment in a gas atmosphere containing only hydrogen will. High quality silicon epitaxial wafers can thus be produced in such a simple manner, in addition to using the hydrogen chloride gas for the typical pre-bake treatment with only hydrogen.
[0083] In addition, since the argon annealing step is performed after performing the back surface oxidation film removing step, the out-diffusion of red phosphorus from the outer periphery uncovered by the back surface oxidation film can be promoted, thereby restraining the occurrence of self-doping. Thus, the resistivity on the surface of the epitaxial layer can be equalized. Further exemplary embodiment(s)
[0084] It should be understood that the scope of the invention is not limited to the exemplary embodiment(s) described above, but various improvements and design changes are possible as long as such improvements and changes are compatible with the invention are.
[0085] For example, the manufacturing method of a silicon epitaxial wafer according to the invention can be applied to any silicon wafer having a resistivity exceeding 0.98 mΩ·cm (e.g., a resistivity of 1.5 mΩ·cm or less) as long as the silicon wafer is made of a single crystal ingot that has been doped with phosphorus.
[0086] Further, if the generated SF number obtained after the argon anneal step and the hydrogen only pre-bake step is predictable, the silicon wafers with a generated SF number equal to or more than an acceptable value can be subjected to the hydrogen pre-bake step and hydrogen chloride after the argon annealing step, while the silicon wafers with a generated SF number less than the acceptable value may be subjected to the hydrogen pre-baking step only after the argon annealing step. It should be noted that the generated SF number can be predicted based on the thermal hysteresis of the single crystal ingot, or alternatively can be predicted based on an evaluation result obtained by a heat treatment for indentation evaluation of an evaluation silicon wafer cut out at a predetermined position, such as described in Patent Literature 2.
Claims
[1] A method for manufacturing a silicon epitaxial wafer comprising a phosphorus-doped silicon wafer and an epitaxial layer provided on a surface of the silicon wafer, the method comprising: Forming an oxide layer on the back side of the silicon wafer cut from a single crystal ingot produced by a Czochralski process; Removal of the oxide layer that is present on the outer circumference of the silicon wafer; Argon tempering, wherein the silicon wafer is subjected to heat treatment in an argon gas atmosphere after removal of the oxide layer; and Formation of the epitaxial layer on the surface of the silicon wafer after argon annealing, wherein the formation of the epitaxial layer includes: Pre-baking, in which the silicon wafer is subjected to heat treatment in a gas atmosphere containing hydrogen and hydrogen chloride to etch an outer layer of the silicon wafer; and Growth of the epitaxial layer on the surface of the silicon wafer after pre-baking. [2] Manufacturing process of the silicon epitaxial wafer according to claim 1, wherein the outer layer to be etched has a thickness ranging from 100 nm to 300 nm during pre-baking. [3] Manufacturing process of the silicon epitaxial wafer according to claim 1 or 2, wherein The heat treatment during argon tempering is carried out in an argon gas atmosphere at a temperature ranging from 1150 °C to 1250 °C, and The heat treatment during pre-baking is carried out in a gas atmosphere containing hydrogen and hydrogen chloride at a temperature ranging from 1050 °C to 1250 °C. [4] Manufacturing method of the silicon epitaxial wafer according to any one of claims 1 to 3, wherein the epitaxial layer is grown at a temperature ranging from 1050 °C to 1150 °C during the growth of the epitaxial layer. [5] Manufacturing method of the silicon epitaxial wafer according to any one of claims 1 to 4, wherein a specific resistance of the silicon wafer is equal to 1.5 mΩ·cm or less.