Semiconductor optoelectronic device and optoelectronic modulator
By setting intercalated metal deposition regions on the side of the optical waveguide, the problem of redundant pattern filling when the waveguide medium and metal electrodes are highly overlapping is solved, which improves the performance of semiconductor optoelectronic devices and electrode performance, and enhances the stability and consistency of the process.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 国科光芯金杏(北京)实验室科技有限公司
- Filing Date
- 2025-01-24
- Publication Date
- 2026-07-24
AI Technical Summary
In the semiconductor chip manufacturing process, when waveguide media and metal electrodes are highly overlapping, existing technologies cannot effectively fill redundant patterns, resulting in reduced electrode flatness and reliability, and failing to meet the requirement of filling dummy areas in large regions.
By setting a metal deposition region on the side of the optical waveguide, which is interlocked with the waveguide redundancy pattern, the metal deposition region extends into the gap of the waveguide redundancy pattern and forms a connected structure, avoiding the restriction of the previous pattern structure and realizing flexible metal filling.
This improved the performance of semiconductor optoelectronic devices and electrodes, ensured the filling of redundant patterns in both waveguides and metals, enhanced the stability and consistency of the process, and enabled the fabrication of large-area electrodes.
Smart Images
Figure CN122449787A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor optoelectronic device and an optoelectronic modulator. Background Technology
[0002] In semiconductor chip manufacturing, patterning is one of the core processes. It includes photolithography and etching, which replicate and transfer patterns from a photomask to thin film materials on a wafer to form circuits, optical paths, or micromechanical structures. In this process, filling with redundant structures (dummy patterns) plays a crucial role. It not only relieves thin film stress and enhances the physical strength of the structure, but also reduces the load effect caused by uneven pattern density during processing, thereby effectively controlling process consistency and stability.
[0003] In existing processes, the materials in each layer are at different heights. Therefore, dummy elements are added to the areas of each layer that do not contain graphics, such as... Figure 1 and Figure 2 As shown. However, if different layers of materials overlap in height, competition will occur, making it impossible to meet the dummy filling requirements of each layer of materials.
[0004] In order to obtain good microwave characteristics, such as characteristic impedance and microwave loss, the electrodes are generally made wider when fabricating traveling wave electrodes for optoelectronic devices. However, this will lead to a reduction in electrode flatness and reliability, and will also prevent the dummy from being filled in a large area, including the waveguide. Summary of the Invention
[0005] In view of this, embodiments of this application provide a semiconductor optoelectronic device and an optoelectronic modulator, which at least partially solves the dummy filling problem of waveguide medium and metal electrode when they are highly overlapping in the prior art.
[0006] In a first aspect, embodiments of this application provide a semiconductor optoelectronic device, the semiconductor optoelectronic device comprising:
[0007] Substrate;
[0008] The substrate is provided with a cladding layer;
[0009] The cladding contains optical waveguides and corresponding waveguide redundancy patterns.
[0010] The cladding also includes at least one metal deposition region, which is located on one or both sides of the optical waveguide. The metal deposition region is located within any gap of the redundant pattern of adjacent waveguides, and the metals within the same metal deposition region are interconnected.
[0011] According to a specific implementation of an embodiment of this application, the optical waveguide is specifically configured as a multi-layer waveguide, with corresponding multi-layer waveguide redundancy patterns, and the bottom of the metal deposition region extends to at least one layer of waveguide redundancy patterns located below the top layer of waveguide redundancy patterns.
[0012] According to one specific implementation of the embodiments of this application, the metal deposition region does not overlap or interlock with any of the optical waveguides.
[0013] According to one specific implementation of the embodiments of this application, the metals in the same metal deposition region are interconnected and form a circuit path.
[0014] According to a specific implementation of an embodiment of this application, the projections of the multiple waveguide redundancy patterns overlap on a horizontal projection.
[0015] According to a specific implementation of an embodiment of this application, the distance between the inner wall of the metal deposition region and the sidewall of the waveguide redundancy pattern is greater than or equal to 1 μm.
[0016] According to a specific implementation of an embodiment of this application, the metal deposition depth of the metal deposition region is set to 500 nm to 3 μm.
[0017] According to a specific implementation of an embodiment of this application, the substrate is a silicon substrate, the cladding is a silicon dioxide cladding, the material of the waveguide redundancy pattern is silicon or silicon nitride, the optical waveguide is a silicon nitride waveguide or a composite waveguide, and the deposited metal is copper.
[0018] Secondly, embodiments of this application also provide a semiconductor optoelectronic device, the semiconductor optoelectronic device comprising:
[0019] Substrate;
[0020] The substrate is provided with a cladding layer;
[0021] The cladding contains optical waveguides and corresponding waveguide redundancy patterns.
[0022] The cladding also includes at least one metal deposition region, which is located on one or both sides of the optical waveguide. The metal deposition region is located within the gap of any adjacent waveguide redundancy pattern, and the metals within the same metal deposition region are interconnected. After any one or more of the metal deposition regions are energized, the optical signal transmitted in the optical waveguide is modulated.
[0023] Thirdly, embodiments of this application also provide an optoelectronic modulator, which includes a semiconductor optoelectronic device as described in any of the embodiments of the first aspect above or a semiconductor optoelectronic device as described in the embodiments of the second aspect.
[0024] Beneficial effects:
[0025] The semiconductor optoelectronic device and optoelectronic modulator in this application, by forming a structure in which the metal deposition region and the waveguide redundancy pattern are interlocked, do not need to avoid the metal position when designing the waveguide redundancy pattern. The metal filling can extend into the gaps of the waveguide redundancy pattern and form a connected structure, reducing the constraint relationship between the metal inlay process and the previous layer pattern structure. This makes the addition of the previous layer redundancy pattern more flexible, makes it easier to meet the redundancy pattern density requirements, and makes its patterning process more stable and controllable. It satisfies the dummy filling of both the waveguide and the metal, while also realizing the need for large-area electrode fabrication. Therefore, the structure of the waveguide redundancy pattern and the metal deposition region interlocked in this application improves the performance of the semiconductor optoelectronic device and effectively improves the electrode performance. Attached Figure Description
[0026] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0027] Figure 1 A cross-sectional view of a prior art semiconductor optoelectronic device;
[0028] Figure 2 A top view of a prior art semiconductor optoelectronic device;
[0029] Figure 3 This is a top view of a semiconductor optoelectronic device according to an embodiment of the present invention;
[0030] Figure 4 for Figure 3 Cross-sectional view at point A (middle dashed line);
[0031] Figure 5 for Figure 3 Cross-sectional view at point B (dash line);
[0032] Figure 6 This is a top view of another semiconductor optoelectronic device according to an embodiment of the present invention;
[0033] Figure 7 for Figure 6 Cross-sectional view at point C (dash line).
[0034] In the figure: 1. Substrate; 2. Cladding; 3. First optical waveguide; 4. Redundancy pattern of the first waveguide; 5. Second optical waveguide; 6. Redundancy pattern of the second waveguide; 7. Metal deposition region; 8. Metal modulation region; 9. Metal redundancy pattern. Detailed Implementation
[0035] The embodiments of this application will now be described in detail with reference to the accompanying drawings.
[0036] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0037] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this application, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using other structures and / or functionalities besides one or more of the aspects set forth herein.
[0038] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. The illustrations only show the components related to this application and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0039] Furthermore, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the described aspects can be practiced without these specific details.
[0040] In the existing process, the materials in each layer are at different heights, therefore redundant graphics are added to areas where no graphics exist in their respective layers. (Refer to...) Figure 1 and Figure 2As shown, each layer of the optical waveguide has its own corresponding redundant pattern. If the materials of different layers overlap in height, a competition will occur, making it impossible to meet the requirements of each layer to fill the redundant pattern.
[0041] Firstly, to solve the aforementioned technical problems, embodiments of this application provide a semiconductor optoelectronic device that solves the problem of redundant pattern filling when waveguide dielectric and metal electrodes are highly overlapping. The following refers to... Figures 3 to 5 Provide a detailed description.
[0042] In one embodiment, a semiconductor optoelectronic device is provided, the semiconductor optoelectronic device comprising:
[0043] Substrate 1;
[0044] The substrate 1 is provided with a cladding layer 2;
[0045] The cladding 2 contains an optical waveguide and a corresponding waveguide redundancy pattern 6;
[0046] The cladding 2 also includes at least one metal deposition region 7, which is located on one or both sides of the optical waveguide. The metal deposition region 7 is located within any gap of the redundant pattern of adjacent waveguides, and the metals in the same metal deposition region 7 are interconnected.
[0047] In this embodiment, by forming a structure in which the metal deposition region 7 is interlocked with the waveguide redundancy pattern, it is not necessary to avoid the metal location when designing the waveguide redundancy pattern. The metal filling can extend into the gaps of the waveguide redundancy pattern and form a connected structure, reducing the constraints between the metal inlay process and the previous layer pattern structure. This makes the addition of the previous layer redundancy pattern more flexible, making it easier to meet the redundancy pattern density requirements, and making its patterning process more stable and controllable. It satisfies the redundancy pattern filling of both the waveguide and the metal, while also achieving the need for large-area electrode fabrication. Therefore, the structure of the waveguide redundancy pattern and the metal deposition region 7 interlocked in this application improves the performance of semiconductor optoelectronic devices and effectively enhances electrode performance.
[0048] In specific implementation, the metal deposition region 7 is not located on a different layer from the optical waveguide and the waveguide redundancy pattern. Instead, the metal deposition region 7 and the waveguide redundancy pattern form a nested structure, meaning that the metal deposition region 7 is located within the gaps between any adjacent waveguide redundancy patterns, and the metals within the same metal deposition region 7 are interconnected. In this embodiment, during the fabrication process, when fabricating the preceding waveguide structure and waveguide redundancy pattern, there is no need to consider the positional relationship of the subsequent metal deposition region 7, and the metal can be fabricated over a large area. Therefore, this embodiment solves the problem of redundancy pattern filling when the waveguide medium and metal electrodes highly overlap, satisfying both the redundancy pattern filling requirements of the waveguide and the metal, and enabling large-area electrode fabrication. This ensures the performance of the optical waveguide device and effectively improves electrode performance.
[0049] In practical implementation, the waveguide redundancy pattern plays a role in pattern balancing, which can release thin film stress, enhance the strength of the physical structure, and reduce the load effect caused by uneven pattern density during processing, thereby effectively controlling the consistency and stability of the process. For the fabrication of the metal deposition region 7, the waveguide redundancy pattern can be divided into regions. Based on actual needs, several regions of the required waveguide redundancy pattern are set as metal deposition regions 7. When dividing the regions, the waveguide redundancy patterns on both sides of the optical waveguide can be divided into different regions according to the position of the optical waveguide. If the number of waveguide redundancy patterns on one side of the optical waveguide is large, or if different arrangements are required according to actual application needs, this side of the waveguide redundancy pattern can be further divided into multiple regions. That is, the region division of the waveguide redundancy pattern can be specifically set according to the actual application situation, and this embodiment does not impose any special limitations. Generally, the metal deposition region 7 overlaps and is inlaid with the waveguide redundancy pattern close to the optical waveguide, that is, the waveguide redundancy patterns located on the left and right sides of the optical waveguide overlap and are inlaid with the metal deposition region 7.
[0050] In one embodiment, refer to Figure 5 The optical waveguide is specifically configured as a multi-layer waveguide, with corresponding multi-layer waveguide redundancy patterns. The bottom of the metal deposition region 7 extends to at least one layer of the waveguide redundancy pattern located below the top layer waveguide redundancy pattern.
[0051] In practical implementation, each layer of optical waveguide has a waveguide redundancy pattern corresponding to that layer's optical waveguide, which can be used to balance the pattern structure of each layer and release thin film stress. For example... Figure 4As shown in the figure, an example with two layers of optical waveguides and waveguide redundancy patterns is illustrated. The first layer contains a first optical waveguide 3 and a first waveguide redundancy pattern 4, while the second layer contains a second optical waveguide 5 and a second waveguide redundancy pattern 6. It should be noted that the number of dielectric layers (the layers containing the optical waveguides and waveguide redundancy patterns) can be increased according to actual needs. The bottom of the metal deposition region 7 can extend to multiple layers of waveguide redundancy patterns, meaning that the metal deposition region 7 and the multiple layers of waveguide redundancy patterns are interlocked. When the required depth of the metal deposition region 7 is relatively deep, if existing fabrication methods are used when preparing the waveguide redundancy pattern, the position of the subsequent metal deposition region 7 must be considered and avoided, resulting in insufficient filling density and uniformity of the prepared waveguide redundancy pattern, thus affecting device performance. In this embodiment, the metal deposition region 7 and the waveguide redundancy pattern are directly interlocked. When preparing the waveguide redundancy pattern, the position of the metal deposition region 7 does not need to be considered, and the depth of the metal deposition region 7 can be directly adjusted according to needs, thus solving the problem of redundancy pattern filling when the waveguide dielectric and metal electrodes are highly overlapping. Therefore, in this embodiment, the redundancy pattern filling of both the waveguide and the metal is satisfied, and the requirement for large-area electrode fabrication is achieved.
[0052] In practice, an etching process is first used to etch the cladding 2, avoiding the optical waveguide and waveguide redundancy pattern areas to create grooves, forming metal deposition trenches. Metal is then deposited within these trenches using a deposition process to form the metal deposition region 7. For example, the metal filling can be achieved using a damascus process to form a metal SLOOT circuit. To avoid process deviations causing etching of the waveguide and redundancy patterns, the metal deposition region 7 needs to avoid the optical waveguide and waveguide redundancy patterns. The structure after metal deposition is shown in the figure. Figure 4 and Figure 5 As shown, the deposited metal is divided into different regions by the optical waveguide. Specifically, the metal deposition region 7 does not overlap or nest with the optical waveguide; the metal only overlaps and nests with the waveguide redundancy pattern. That is, metals within the same region are interconnected, and also interconnected within the gaps of the waveguide redundancy patterns within the same region. Therefore, the previous layer (prepared in the previous process) waveguide redundancy pattern is interlocked with the metal. The metal regions, due to their interconnection, form a unified whole, not divided by the previous layer waveguide redundancy pattern, and can still serve as electrodes.
[0053] In one embodiment, the metal deposition region 7 does not overlap or interlock with any of the optical waveguides.
[0054] Specifically, the metal deposition region 7 overlaps and interlocks with the waveguide redundancy pattern, and the metal deposition region 7 is located on both sides of the optical waveguide.
[0055] In one embodiment, the metals within the same metal deposition region 7 are interconnected and form a circuit path.
[0056] In one embodiment, refer to Figure 4 In a horizontal projection, the projections of the multiple waveguide redundancy patterns overlap.
[0057] Specifically, such as Figure 4 As shown, the positions of the multiple waveguide redundancy patterns are arranged one-to-one in the vertical direction. This can be understood as follows: during the fabrication process, the positions of the subsequent waveguide redundancy patterns overlap with those of the preceding layer. However, the size of the subsequent waveguide redundancy pattern is larger than that of the preceding waveguide redundancy pattern. This is mainly to avoid the influence of etching deviations. The size of the redundant patterns in the preceding process is generally smaller, while the size of the redundant patterns in the subsequent process gradually increases. This can be understood as the width of the second waveguide redundancy pattern 6 in the subsequent layer being greater than the width of the first waveguide redundancy pattern 4 in the preceding layer. This size arrangement can avoid the influence of etching deviations and further improve the performance of the optical waveguide device.
[0058] In one embodiment, the distance between the inner wall of the metal deposition region 7 and the sidewall of the waveguide redundancy pattern is greater than or equal to 1 μm.
[0059] In practice, to avoid affecting the waveguide redundancy pattern during the etching of the metal deposition trench when preparing the metal deposition region 7, the distance between the inner sidewall of the metal deposition region 7 and the sidewall of the waveguide redundancy pattern is greater than or equal to 1 μm.
[0060] In one example, the optical waveguide is strip-shaped.
[0061] In one example, the waveguide redundancy pattern is square in shape.
[0062] It should be noted that, Figures 3 to 5 The optical waveguides shown are arranged in two within the same layer. In practical applications, not only the two optical waveguides shown in the figure are included, but other numbers of optical waveguides can also be used. Therefore, the arrangement of metal deposition region 7 includes not only the metal deposition region 7 shown in the figure, but also the metal deposition region 7 arranged between these two optical waveguides and other optical waveguides.
[0063] Furthermore, the thickness of the metal deposition region 7 is 500 nm to 3 μm.
[0064] Furthermore, the thickness of the optical waveguide is 200nm to 800nm, and the width of the optical waveguide is 300nm to 5um.
[0065] Furthermore, the width of the waveguide redundancy pattern is 1µm to 100µm. The function of the waveguide redundancy pattern is to address process deviations and uniformity issues.
[0066] In practice, the structural dimensions of the metal deposition region 7, the optical waveguide, and the waveguide redundancy pattern are adjusted according to the actual application. When the optical waveguide has a multi-layer structure, the dimensions of each structure in each layer are adjusted according to the actual situation.
[0067] In one embodiment, the substrate 1 is a silicon substrate 1, the cladding 2 is a silicon dioxide cladding 2, the waveguide redundancy pattern is made of silicon or silicon nitride, the optical waveguide is a silicon nitride waveguide or a composite waveguide, and the deposited metal is copper.
[0068] Secondly, embodiments of this application also provide a semiconductor optoelectronic device, the semiconductor optoelectronic device comprising:
[0069] Substrate 1;
[0070] The substrate 1 is provided with a cladding layer 2;
[0071] The cladding 2 contains an optical waveguide and a corresponding waveguide redundancy pattern;
[0072] The cladding 2 also includes at least one metal deposition region 7, which is located on one or both sides of the optical waveguide. The metal deposition region 7 is located within any gap of the redundant pattern of adjacent waveguides, and the metals within the same metal deposition region 7 are interconnected. After any one or more of the metal deposition regions 7 are energized, the optical signal transmitted in the optical waveguide is modulated.
[0073] In specific implementation, the metal deposition region 7 may include a metal modulation region 8 and a metal redundancy pattern 9. The metal deposition region 7, which can modulate the optical signal transmitted in the optical waveguide after being powered on, can be set as the metal modulation region 8, and the remaining metal deposition region 7 can be set as the metal redundancy pattern 9, as shown in the reference. Figure 6 and Figure 7 As shown, the metal modulation region 8 is used to modulate the optical signal transmitted in the optical waveguide after power is applied, and the metal redundant pattern 9 serves as a redundant pattern. For example, the metal modulation region 8 can serve as a metal electrode, and its structural shape and size can be set according to the actual application scenario. The metal modulation region 8 is located near the optical waveguide and needs to be tightly coupled to the optical waveguide so that the generated electric field can affect the optical mode in the optical waveguide, thereby effectively modulating the light propagating through the optical waveguide. Therefore, the metal modulation region 8 needs to be nested with the waveguide redundant pattern close to the optical waveguide. The metal redundant pattern 9, as a redundant pattern, can be nested with other remaining waveguide redundant patterns, mainly playing a role in pattern balancing. It can release thin film stress, enhance the strength of the physical structure, and reduce the load effect caused by uneven pattern density during processing, thereby effectively controlling process consistency and stability.
[0074] In practical implementation, the number of optical waveguides can be set to multiple, as shown in the reference. Figure 6 and Figure 7 As shown in the figure, taking an example with two optical waveguides, the waveguide redundancy pattern between these two optical waveguides is divided into a region and nested with the metal modulation region 8. For the remaining waveguide redundancy patterns, since they are located on the opposite outer sides of the two optical waveguides, the waveguide redundancy pattern located on the outer side of each optical waveguide is divided into a region, and the metal redundancy pattern 9 is nested with the waveguide redundancy patterns in these two regions respectively. The figure only shows an exemplary arrangement of the metal modulation region 8 and the metal redundancy pattern 9; it can be adjusted according to actual needs, such as setting two metal modulation regions 8, etc.
[0075] For the fabrication of the semiconductor optoelectronic device of this application, taking the optical waveguide and waveguide redundancy pattern as two layers as an example, the specific process flow includes the following steps:
[0076] A first dielectric layer is grown on silicon dioxide by low-pressure chemical vapor deposition (LPCVD) to realize a low-loss optical transmission channel.
[0077] The first optical waveguide 3 and the corresponding first waveguide redundancy pattern 4 are formed by etching the first dielectric layer, wherein the filling of the first waveguide redundancy pattern 4 also needs to meet the rule requirements of metal slot;
[0078] Then a filling dielectric material, such as silica, is deposited and chemically-mechanically polished (CMP).
[0079] After CMP, a second dielectric layer is deposited, and a second optical waveguide 5 and a corresponding second waveguide redundancy pattern 6 are formed by etching the second dielectric layer. The filling positions of the second waveguide redundancy pattern 6 and the filling positions of the first waveguide redundancy pattern 4 are set one-to-one, and the rules of metal slot are also required.
[0080] Then, a filling dielectric material, such as silica, is deposited and chemically-mechanically polished (CMP) to form cladding layer 2; if more dielectric layers are required, they are added sequentially.
[0081] Metal deposition trenches are fabricated, and the trenches are cut in a way that avoids the optical waveguide and waveguide redundancy pattern regions. The metal deposition trenches are interconnected in the gaps of waveguide redundancy patterns in the same region.
[0082] Metal is deposited, and the metal deposition tank is completely filled with metal to form metal deposition area 7. For metal filling, the Damascus process can be used to form metal SLO OT circuit.
[0083] Thirdly, embodiments of this application also provide an optoelectronic modulator, which includes a semiconductor optoelectronic device as described in any of the embodiments of the first aspect above or a semiconductor optoelectronic device as described in the embodiments of the second aspect.
[0084] The embodiments provided by this invention, by forming a structure in which the metal deposition region and the waveguide redundant pattern are interlocked, allow the metal filling to extend into the gaps of the waveguide redundant pattern and form a connected structure. This reduces the constraints between the metal embedding process and the previous layer pattern structure, making the addition of the previous layer redundant pattern more flexible and easier to meet the target pattern density requirements, thus making the patterning process more stable and controllable. It satisfies the filling of redundant patterns in both the waveguide and the metal, while also enabling the fabrication of large-area electrodes. Therefore, the structure of the waveguide redundant pattern and the metal deposition region interlocked in this application improves the performance of semiconductor optoelectronic devices and effectively enhances electrode performance.
[0085] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A semiconductor optoelectronic device, characterized in that, The semiconductor optoelectronic device includes: Substrate; The substrate is provided with a cladding layer; The cladding contains optical waveguides and corresponding waveguide redundancy patterns. The cladding also includes at least one metal deposition region, which is located on one or both sides of the optical waveguide. The metal deposition region is located within any gap of the redundant pattern of adjacent waveguides, and the metals within the same metal deposition region are interconnected.
2. The semiconductor optoelectronic device according to claim 1, characterized in that, The optical waveguide is specifically configured as a multi-layer waveguide, with corresponding multi-layer waveguide redundancy patterns. The bottom of the metal deposition region extends to at least one layer of the waveguide redundancy pattern located below the top layer of the waveguide redundancy pattern.
3. The semiconductor optoelectronic device according to claim 1, characterized in that, The metal deposition region does not overlap or interlock with any of the optical waveguides.
4. The semiconductor optoelectronic device according to claim 1, characterized in that, The metals within the same metal deposition region are interconnected and form a circuit path.
5. The semiconductor optoelectronic device according to claim 2, characterized in that, In a horizontal projection, the projections of the multiple waveguide redundancy patterns overlap.
6. The semiconductor optoelectronic device according to claim 1, characterized in that, The distance between the inner wall of the metal deposition region and the sidewall of the waveguide redundancy pattern is greater than or equal to 1 μm.
7. The semiconductor optoelectronic device according to any one of claims 1 to 6, characterized in that, The metal deposition depth in the metal deposition region is set to 500 nm to 3 μm.
8. The semiconductor optoelectronic device according to any one of claims 1 to 6, characterized in that, The substrate is a silicon substrate, the cladding is a silicon dioxide cladding, the waveguide redundancy pattern is made of silicon or silicon nitride, the optical waveguide is a silicon nitride waveguide or a composite waveguide, and the deposited metal is copper.
9. A semiconductor optoelectronic device, characterized in that, The semiconductor optoelectronic device includes: Substrate; The substrate is provided with a cladding layer; The cladding contains optical waveguides and corresponding waveguide redundancy patterns. The cladding also includes at least one metal deposition region, which is located on one or both sides of the optical waveguide. The metal deposition region is located within the gap of any adjacent waveguide redundancy pattern, and the metals within the same metal deposition region are interconnected. After any one or more of the metal deposition regions are energized, the optical signal transmitted in the optical waveguide is modulated.
10. A photoelectric modulator, characterized in that, The optoelectronic modulator includes a semiconductor optoelectronic device as described in any one of claims 1 to 8 or a semiconductor optoelectronic device as described in claim 9.