A power supply ripple self-detection system and method based on MCU built-in resources

Abstract

This invention discloses a power supply ripple self-detection system and method based on MCU built-in resources, belonging to the field of embedded system power supply monitoring technology. It addresses the shortcomings of traditional digital oscilloscopes, such as high offline measurement costs and inability to achieve full lifecycle self-diagnosis in embedded systems; insufficient sampling rate of MCU built-in ADCs and susceptibility to DC component saturation; and the reliance of existing comparator solutions on external active components. This invention adopts a core architecture of "AC DC blocking + high-gain amplification + dual threshold scanning + digital counting." All active modules in the system are built into the MCU. Specifically, the AC component of the power supply ripple is separated by a DC blocking capacitor, amplified by a programmable gain amplifier, and then an adjustable threshold is generated using a dual digital-to-analog converter. This threshold controls dual high-speed comparators to scan and obtain peak and trough values ​​to calculate the peak-to-peak value, and the period is measured by an internal counter. This invention also supports zero-point calibration, gain adaptation, and online early warning, making it suitable for real-time power health monitoring in industrial control and other fields.

Description

Technical Field

[0001] This invention relates to the field of embedded system power monitoring technology, and in particular to a power ripple self-detection system and method based on MCU built-in resources. Background Technology

[0002] As embedded systems evolve towards higher integration and precision, DC-DC switching power supplies have become the mainstream power supply solution for MCUs and peripheral analog devices due to their advantages such as high efficiency, small size, and wide input voltage range. However, during the switching process of the DC-DC converter, combined with the charging and discharging characteristics of the output capacitor, periodic AC ripple is inevitably superimposed on the output voltage. The peak-to-peak value and period of this ripple are core indicators for measuring power supply quality. Excessive ripple can lead to MCU logic level misjudgments, decreased signal-to-noise ratio of analog circuits, deterioration of ADC sampling accuracy, sensor signal distortion, and even system crashes or hardware damage, seriously affecting the reliability and stability of embedded devices.

[0003] Traditional ripple measurement relies on digital oscilloscopes, requires setting up AC coupling, bandwidth limitations, and near-end grounding using grounding springs. While accurate, this method is expensive, cumbersome, and lacks embedded self-diagnosis capabilities during system operation. Some existing solutions attempt to measure ripple using MCU-built-in ADC sampling, but limitations in ADC sampling rate (typically much lower than the ripple frequency, such as hundreds of kHz to several MHz) and quantization accuracy make it difficult to accurately capture the peak-to-peak value and period of high-frequency ripple.

[0004] Therefore, there is an urgent need for a low-cost, highly integrated, high-precision, and embedded power supply ripple self-detection solution that can make full use of the existing built-in resources of the MCU without adding external active devices, and at the same time achieve accurate measurement of the peak-to-peak value and period of the power supply ripple. Summary of the Invention

[0005] In view of this, this application provides a power ripple self-detection system and method based on MCU built-in resources to overcome the shortcomings of the prior art.

[0006] The first aspect of this application provides a power ripple self-detection system based on MCU built-in resources, wherein all active modules of the system are built into the MCU, including: A DC blocking capacitor, whose input is connected to the power rail of the MCU to be tested and whose output is connected to the input of the programmable gain amplifier (PGA), is used to block the DC component of the MCU power rail and couple only the AC component of the power ripple to the signal path. A programmable gain amplifier (PGA) is used to linearly amplify the AC component of the coupled power supply ripple in a programmable manner. The first digital-to-analog converter DAC1 generates an independently adjustable upper threshold voltage; The second digital-to-analog converter DAC2 generates an independently adjustable lower threshold voltage; The first high-speed comparator CMP1 has its non-inverting input connected to the output of the programmable gain amplifier PGA and its inverting input connected to the output of the first digital-to-analog converter DAC1, and is used to compare the amplified ripple signal with the upper threshold voltage. The second high-speed comparator CMP2 has its non-inverting input connected to the output of the second digital-to-analog converter DAC2 and its inverting input connected to the output of the programmable gain amplifier PGA. It is used to compare the lower threshold voltage with the amplified ripple signal. The low dropout linear regulator (LDO) has its input connected to the power rail of the MCU, and its output independently supplies power to the programmable gain amplifier (PGA), the first digital-to-analog converter (DAC1), the second digital-to-analog converter (DAC2), the first high-speed comparator (CMP1), the second high-speed comparator (CMP2), and the digital computing unit, thereby achieving power isolation between the measurement circuit and the power rail of the MCU under test. A digital computing unit, connected to the output terminals of the first high-speed comparator CMP1 and the second high-speed comparator CMP2, and the control terminals of the first digital-to-analog converter DAC1 and the second digital-to-analog converter DAC2, is used to perform the following operations: The first digital-to-analog converter DAC1 is controlled to increment upwards to perform threshold scanning, and the second digital-to-analog converter DAC2 is controlled to decrement downwards to perform threshold scanning. The threshold voltages corresponding to the output flips of the first high-speed comparator CMP1 and the second high-speed comparator CMP2 are recorded. The peak-to-peak value of the original ripple of the MCU power rail is calculated and deduced. At the same time, the period of the original ripple is measured using an internal counter.

[0007] In one possible implementation of the first aspect, the digital computing unit is configured to dynamically configure the gain value of the programmable gain amplifier according to the expected ripple amplitude range of the MCU power rail, such that the peak-to-peak value of the amplified AC ripple signal does not exceed the input dynamic range of the first high-speed comparator CMP1 and the second high-speed comparator CMP2.

[0008] In one possible implementation of the first aspect, the DC blocking capacitor is a programmable capacitor array integrated inside the MCU, or an external discrete ceramic capacitor connected between the MCU power rail and the input terminal of the programmable gain amplifier PGA.

[0009] In one possible implementation of the first aspect, the digital computing unit is further configured to perform system zero-point calibration: When the MCU power rail is in a known low ripple state during the initial power-on phase of the system and all non-essential peripherals are not started, a complete threshold scan measurement is performed. The measurement result is stored as the inherent offset error of the system, and all subsequent measurement results are automatically compensated by subtracting the inherent offset error.

[0010] In one possible implementation of the first aspect, the first high-speed comparator CMP1 and the second high-speed comparator CMP2 are combined into a single high-speed comparator built into the MCU. The system also includes an analog switch built into the MCU, whose input terminals are respectively connected to the output terminals of the programmable gain amplifier PGA, the output terminals of the first digital-to-analog converter DAC1 and the second digital-to-analog converter DAC2, and whose output terminals are respectively connected to the non-inverting input terminal and the inverting input terminal of the high-speed comparator. The digital computing unit controls the analog switch to switch the input polarity of the high-speed comparator in a time-division manner, and performs peak detection and trough detection in sequence.

[0011] The second aspect of this application provides a power ripple self-detection method based on MCU built-in resources, comprising the following steps: S1. By blocking the DC component of the MCU power rail with a DC blocking capacitor, the AC component of the power ripple is coupled to a programmable gain amplifier, and the gain value of the programmable gain amplifier is configured by the digital computing unit to linearly amplify the AC ripple; S2. The digital computing unit controls the first digital-to-analog converter to scan upwards from the common-mode bias voltage of the programmable gain amplifier, and records the upper limit threshold voltage corresponding to the first high-speed comparator output flipping from high level to low level; at the same time, it controls the second digital-to-analog converter to scan downwards from the common-mode bias voltage of the programmable gain amplifier, and records the lower limit threshold voltage corresponding to the second high-speed comparator output flipping from high level to low level. S3. Calculate the peak-to-peak value of the amplified ripple based on the difference between the upper threshold voltage and the lower threshold voltage, and then divide it by the gain value of the programmable gain amplifier to obtain the original peak-to-peak value of the MCU power rail. S4. Fix the output of the first digital-to-analog converter or the second digital-to-analog converter to the common-mode bias voltage, and use the internal counter of the digital computing unit to capture the periodic edge signal of the corresponding high-speed comparator output to calculate the period of the original ripple.

[0012] In one possible implementation of the second aspect, in step S2, the threshold scanning adopts a successive approximation scanning method or a segmented approximation scanning method. The scanning step size is dynamically adjusted according to the resolution and measurement accuracy requirements of the first digital-to-analog converter and the second digital-to-analog converter. Each threshold point is scanned at least 3 times and the average value is taken as the final recorded value.

[0013] In one possible implementation of the second aspect, in step S4, the internal counter is configured in input capture mode, using two adjacent rising edges or two adjacent falling edges of the output of the first high-speed comparator or the second high-speed comparator as trigger signals, continuously capturing count values ​​for at least 10 cycles, and taking the arithmetic mean after removing the maximum and minimum values ​​as the cycle of the final raw ripple.

[0014] In one possible implementation of the second aspect, online monitoring and anomaly early warning steps are also included: The digital computing unit periodically executes the measurement process of steps S1 to S4, comparing the original ripple peak value obtained from each measurement with a preset health threshold. When the measurement results exceed the health threshold for three consecutive times, a hardware alarm signal is generated or a preset power management action is executed.

[0015] In one possible implementation of the second aspect, a gain adaptive adjustment step is also included: After the amplified peak-to-peak value of the ripple is obtained by the first threshold scan, if the peak-to-peak value exceeds the preset upper limit threshold or is lower than the preset lower limit threshold of the input dynamic range of the first high-speed comparator and the second high-speed comparator, the digital computing unit automatically adjusts the gain value of the programmable gain amplifier and re-executes the measurement process of steps S1 to S3 until the amplified peak-to-peak value of the ripple is between the preset upper limit threshold and the preset lower limit threshold.

[0016] Its beneficial effects are as follows: This invention discloses a power supply ripple self-detection system and method based on MCU built-in resources, which has at least the following beneficial effects: 1) Extremely simple circuit design: All active modules are built into the MCU, requiring only one external passive DC blocking capacitor (or built-in programmable capacitor array), with no additional active BOM cost and minimal PCB area occupation; 2) No risk of DC saturation: The DC blocking capacitor completely blocks the DC component, and the programmable gain amplifier (PGA) can safely amplify weak ripples with high gain without worrying about the DC component causing output saturation, thus achieving high measurement sensitivity. 3) High-precision measurement: Dual high-speed comparators independently detect peaks and troughs, and combined with successive approximation scanning and multi-cycle averaging algorithms, greatly improve the measurement accuracy of ripple peak-to-peak value and period; 4) Online self-diagnostic capability: It can perform measurements automatically and periodically, monitor the power supply ripple change trend in real time, and automatically alarm when the threshold is exceeded continuously, realizing full life cycle management of power supply health status; 5) Strong adaptability: By adjusting the programmable gain amplifier (PGA), digital-to-analog converter (DAC) step size, and DC blocking capacitor configuration through software, it can adapt to ripple signals of different voltage levels and amplitudes. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a power ripple self-detection system circuit based on MCU built-in resources provided in an embodiment of this application; Figure 2 This is a schematic diagram of a power ripple self-detection method based on MCU built-in resources provided in an embodiment of this application. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] In this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0021] To better understand this application, the technical names involved in this application are explained below: MCU power rail: refers to the common power supply line that provides the same nominal voltage to the microcontroller (MCU) and its internal peripherals and external functional modules. It is the core path for power transmission in the MCU system. Depending on the power supply object, MCU power rails typically include the main digital power rail (VDD / VCC), analog power rail (VDDA), I / O port power rail (VDDIO), and core-specific power rail (VDDCORE), etc. The technical solution of this invention can be applied to any power rail of the MCU. For ease of consistent description, in this embodiment, "MCU power rail" specifically refers to the MCU's main digital power rail VDD, i.e., the attached... Figure 1 The VDD power rail is shown in the diagram.

[0022] Example 1 The core logic of this invention is "AC DC blocking + high-gain amplification + dual threshold scanning + digital counting". Through the collaborative work of the built-in modules of the MCU, the weak high-frequency ripple that is difficult to measure directly is converted into a digital signal that can be accurately quantified. The working principle of each module is explained in detail below, and then the complete implementation process is illustrated with specific embodiments.

[0023] Core working principle: 1. AC coupling and DC blocking of DC blocking capacitors Its core function is to separate the DC component and AC ripple component on the MCU power rail, allowing only the ripple signal to enter the subsequent measurement circuit.

[0024] The power rail signal composition: the actual voltage on the MCU power rail is the superposition of the nominal DC value and the AC ripple, i.e. For example, when a 5V power rail is superimposed with a 30mV peak-to-peak ripple, the actual voltage fluctuates periodically between 4.985V and 5.015V.

[0025] DC blocking capacitors have the characteristic of "passing AC and blocking DC". For DC signals, the capacitive reactance approaches infinity, and the DC component cannot pass through at all. For AC ripple signals, as long as the capacitor value is appropriate, the capacitive reactance is much smaller than the input impedance of the subsequent PGA (usually 1000 ohms). (Level 1), the ripple signal passes through with almost no attenuation.

[0026] For parameter selection, this invention recommends that the DC blocking capacitor value be [value missing]. With typical Taking a capacitor and a 100kHz ripple as an example, its capacitive reactance Much smaller than the PGA With a high input impedance, the ripple attenuation is less than 0.0016%, which is negligible.

[0027] The output signal characteristics are such that the signal at the output terminal of the DC blocking capacitor only contains AC ripple components, and its DC level is determined by the common-mode bias voltage of the subsequent PGA, rather than the DC voltage of the power rail.

[0028] 2. Linear amplification of a programmable gain amplifier (PGA) Its core function is to amplify weak millivolt-level ripple signals to near the full scale of the comparator, thereby significantly improving measurement resolution.

[0029] Common-mode bias: The MCU's built-in PGA typically has a fixed common-mode output bias voltage, generally half of the reference voltage. In a typical embodiment, the reference voltage is 3.3V, therefore the DC bias of the PGA output is 1.65V, and the amplified ripple signal will fluctuate around 1.65V. , where G is the gain value of the PGA (programmable from 10 to 200 times).

[0030] Gain selection requires dynamic configuration based on the expected ripple amplitude to ensure that the peak-to-peak value of the amplified ripple does not exceed the comparator's input dynamic range (0~3.3V). For example, with a 30mV ripple, a gain of 100 will result in a peak-to-peak value of 3V, which is within the comparator's linear operating range. If the ripple is 200mV, a gain of 10 should be selected to avoid signal saturation distortion.

[0031] Achieving high resolution, the 12-bit DAC has a minimum step size of approximately 0.8mV at a 3.3V reference voltage. Combined with a 100x PGA gain, the minimum resolvable original ripple amplitude is... It has a measurement accuracy far exceeding that of the built-in ADC of ordinary MCUs.

[0032] 3. Built-in LDO power supply isolation Its core function is to provide an independent and clean power supply for the measurement circuit, avoiding interference from the ripple of the power rail of the MCU under test with the measurement results.

[0033] The interference is generated because if the measurement circuits (PGA, DAC, CMP) are directly powered by the power rail under test, the power supply voltage of these modules inherently contains ripple. This causes the following: the threshold voltage output by the DAC will be superimposed with ripple, resulting in jitter; the amplification factor of the PGA will fluctuate with the power supply voltage; and the switching threshold of the CMP will be unstable. Ultimately, this leads to extremely large measurement errors.

[0034] The isolation principle is that the MCU's built-in LDO converts the rippled voltage of the measured power rail into a stable 3.3V DC voltage, providing independent power to all measurement modules.

[0035] Only the input terminal of the DC blocking capacitor is directly connected to the power rail under test, while the power supply of all other active modules comes from the LDO output, completely cutting off the interference path of the ripple under test to the measurement circuit.

[0036] 4. Threshold scanning peak-to-peak value measurement using dual digital-to-analog converters and dual high-speed comparators. Its core function is to find the peaks and troughs of the amplified ripple by successively adjusting the DAC output threshold, and then calculate the peak-to-peak value of the ripple.

[0037] Basic logic of a comparator: The first high-speed comparator CMP1: its non-inverting input is connected to the output of the programmable gain amplifier PGA, and its inverting input is connected to the output of the first digital-to-analog converter DAC1; when... When the signal is high, CMP1 outputs a high level; otherwise, it outputs a low level. The second high-speed comparator CMP2: its non-inverting input is connected to the output of the second digital-to-analog converter DAC2, and its inverting input is connected to the output of the programmable gain amplifier PGA; when... When the signal is high, CMP2 outputs a high level; otherwise, it outputs a low level.

[0038] Peak detection principle: The initial value of DAC1 is set to the PGA common-mode bias voltage of 1.65V. At this time, the ripple of the PGA output will periodically be higher than 1.65V, so CMP1 will periodically output a high level. The digital computing unit controls DAC1 to increment in 1 LSB steps, waiting for 2 seconds after each update. (Greater than the comparator response time) to ensure stable output; When the DAC1 voltage exceeds the maximum value (peak) of the ripple, the PGA output will be lower than the DAC1 voltage at any time, and CMP1 will change from "periodic high-low switching" to "continuous low level". Record the DAC1 voltage value corresponding to the last high-level output of CMP1, as the estimated peak voltage value of the amplified ripple, denoted as . .

[0039] Valley detection principle: The initial value of DAC2 is set to 1.65V. At this time, the ripple output of PGA will periodically drop below 1.65V, so CMP2 will periodically output a high level. The digital computing unit controls DAC2 to decrease downwards in 1 LSB steps; When the DAC2 voltage is lower than the minimum value (trough) of the ripple, the PGA output will be higher than the DAC2 voltage at any time, and CMP2 will change from "periodic high-low switching" to "continuous low level". Record the DAC2 voltage value corresponding to the last high level output of CMP2, as the estimated value of the trough voltage of the amplified ripple, denoted as . .

[0040] Peak-to-peak value calculation principle: Magnified ripple peak value: ; Original MCU power rail ripple peak-to-peak value: .

[0041] 5. Ripple period measurement of the internal counter Its core function is to accurately measure the period and frequency of ripple using the periodic output of the comparator.

[0042] In input capture mode, the input capture channel of the MCU's internal timer can automatically record the timer count value when the comparator output edge appears. When configured for rising edge capture mode, the timer will latch the current count value into the capture register the instant the comparator output changes from low to high.

[0043] The ripple period is calculated by multiplying the difference between the count values ​​captured on two consecutive rising edges by the timer clock period. For example, if the timer clock is 100MHz (period 10ns) and the difference between two captured count values ​​is 1000, then the ripple period is... Corresponding frequency .

[0044] With improved accuracy, the system continuously captures count values ​​for 10 cycles, removes the maximum and minimum values, and takes the arithmetic mean, which effectively eliminates the effects of random noise and timer jitter, thus improving the accuracy of cycle measurement.

[0045] 6. System zero-point calibration Its core function is to eliminate inherent offset errors in hardware and improve absolute measurement accuracy.

[0046] The sources of error, primarily inherent offset errors in the system, include: leakage current of the DC blocking capacitor, input offset voltage of the PGA, input offset voltage of the comparator, and output error of the DAC. These errors can cause a fixed offset value in the measurement result even if the MCU power rail ripple is zero.

[0047] The calibration timing should be chosen at the initial stage of system power-on, when all non-essential peripherals are not yet started. At this time, the DC-DC converter is in a light-load stable operating state, and the power rail ripple is minimal (usually less than 1mV), which is much smaller than the inherent offset error of the system. It can be approximately assumed that the measurement results at this time are entirely composed of system errors.

[0048] Calibration and compensation are performed by executing a complete threshold scan measurement, and the resulting ripple value is stored as a system offset error in non-volatile memory. All subsequent formal measurements will automatically subtract this offset error from the ripple value to obtain the true power rail ripple value.

[0049] 7. Adaptive gain adjustment Its core function is to automatically match the optimal gain to avoid signal saturation or insufficient gain.

[0050] After adjusting the trigger conditions and performing the threshold scan for the first time, if the peak-to-peak value of the amplified ripple exceeds 90% of the comparator input dynamic range (e.g., 2.97V), it indicates that the gain is too large and the signal is close to saturation; if it is less than 10% of the comparator input dynamic range (e.g., 0.33V), it indicates that the gain is too small and the measurement resolution is insufficient.

[0051] The adjustment process involves the digital computing unit automatically adjusting the PGA gain based on the amplitude of the amplified ripple. For example, if the peak-to-peak value after amplification is 3.2V (saturation) when the current gain is 100 times, the gain will be automatically adjusted to 50 times, and the measurement process will be re-executed until the peak-to-peak value of the amplified ripple is in the optimal range of 0.33V to 2.97V.

[0052] After explaining the working principle of this system in detail, this embodiment measures the ripple on the VDD (5V) power rail based on a general-purpose MCU that integrates a programmable capacitor array, PGA, two 12-bit DACs (DAC1 and DAC2), two high-speed comparators (CMP1 and CMP2) and a 3.3V LDO. The expected peak-to-peak ripple is 30mV and the frequency is 100kHz.

[0053] 1. Hardware connection like Figure 1 As shown, the VDD power rail (5V) is connected to the input terminal of the DC blocking capacitor, which is a 0.1V 0805 packaged capacitor. An external ceramic capacitor connects to the input of the MCU's built-in PGA. The LDO's input is connected to the VDD power rail, and its output provides independent 3.3V power to the PGA, DAC1, DAC2, CMP1, CMP2, and the digital computing unit.

[0054] The output of the PGA is connected to both the non-inverting input of CMP1 and the inverting input of CMP2. The output of DAC1 is connected to the inverting input of CMP1 as the upper threshold. The output of DAC2 is connected to the non-inverting input of CMP2 as the lower threshold. The outputs of CMP1 and CMP2 are connected to the interrupt input interface of the digital computing unit. The digital computing unit controls the outputs of DAC1 and DAC2 through the internal bus.

[0055] 2. System Initialization After the system is powered on, the MCU first configures the system clock to 100MHz, enables the LDO and sets the output voltage to 3.3V; it also enables the PGA, DAC1, DAC2, CMP1, CMP2 and the 16-bit timer / counter module.

[0056] Initialize the PGA to single-ended input mode and set the gain to 100 times according to the expected ripple amplitude; initialize the reference voltage of DAC1 and DAC2 to 3.3V, and the initial output value is the common-mode bias voltage of the PGA to 1.65V; configure the input polarity of CMP1 and CMP2 and enable level change interrupt.

[0057] 3. Ripple peak-to-peak value measurement The digital computing unit controls DAC1 to scan upwards in 1 LSB (approximately 0.8 mV) steps, starting from 1.65 V. After each update of DAC1, it waits for 2 seconds. (Greater than the comparator response time), read the output state of CMP1. When the CMP1 output toggles from high to low, stop scanning and record the output voltage of DAC1 at this time as the upper limit threshold. (Measured voltage 3.10V, slightly lower than the actual peak voltage).

[0058] Simultaneously, DAC2 is controlled to scan downwards in 1 LSB steps, starting from 1.65V, to read the output state of CMP2. When the CMP2 output toggles from high to low, the scan stops, and the output voltage of DAC2 at this moment is recorded as the lower threshold. (Measured voltage: 0.20V, slightly higher than the actual trough).

[0059] Calculate the peak-to-peak value of the ripple after amplification: ; Original VDD power rail ripple peak-to-peak value: .

[0060] To improve accuracy, each threshold point was scanned three times and the average value was taken.

[0061] 4. Ripple Period Measurement The output of DAC1 is fixed at 1.65V. The output of CMP1 is connected to the input capture channel of the 16-bit timer inside the digital computing unit, configured for rising edge capture mode. The count values ​​for 10 consecutive cycles are captured. After discarding the maximum and minimum values, the arithmetic mean is taken. The difference in count values ​​is 1000 (timer clock 100MHz). The ripple period is then determined. Corresponding frequency .

[0062] 5. System zero-point calibration During the initial power-up phase, all non-essential peripherals are not started, and the VDD power rail ripple is at its lowest level (less than 1mV). A complete threshold scan measurement is performed, and the measured equivalent value of the original ripple (e.g., 0.5mV) is stored in non-volatile memory as the system's inherent offset error. All subsequent measurement results are automatically subtracted from this offset error to eliminate inherent hardware errors.

[0063] 6. Online monitoring and early warning of anomalies The measurement function is encapsulated and called every 500 milliseconds in the system's main loop. The measured ripple peak-to-peak value and period value are printed to the host computer via UART serial port and simultaneously stored in the internal RAM log buffer. The preset health threshold is 50mV. When three consecutive measurement results exceed 50mV, the MCU outputs a high-level alarm signal through the GPIO pin and reports the abnormal event to the cloud platform via the WiFi module.

[0064] Example 2 For a low-cost MCU integrating only one high-speed comparator, an additional built-in analog switch is added. The inputs of the analog switch are connected to the outputs of the PGA, DAC1, and DAC2, respectively, and the outputs are connected to the non-inverting and inverting inputs of the high-speed comparator, respectively. The digital computing unit controls the analog switch to switch the input polarity of the comparator in a time-division multiplexing manner. Phase 1: Switch to "PGA output connected to non-inverting input, DAC1 output connected to inverting input", and perform peak detection; Second stage: Switch to "DAC2 output connected to non-inverting input, PGA output connected to inverting input", and perform valley detection.

[0065] This solution doubles the measurement time but saves one comparator resource, making it suitable for low-cost applications where measurement speed is not critical.

[0066] Optionally, the DC blocking capacitor can be a programmable capacitor array integrated within the MCU, achieving a single-chip solution with no external components.

[0067] Optionally, the threshold scan can be performed using a segmented approximation scan method, first using a large step size of 10 LSB to quickly locate the peak range, and then using a small step size of 1 LSB to accurately measure, which can shorten the measurement time by more than 70%.

[0068] Optionally, the period measurement can adopt a gated counting mode, using the high level output of the comparator as the gate signal of the counter to measure the duration of the high level, which is suitable for duty cycle measurement requirements.

[0069] Optionally, if the PGA supports differential input, a DC blocking capacitor can be connected to the differential input terminal, which can improve the common-mode rejection ratio by more than 40dB, further enhancing the anti-interference capability.

[0070] Example 3 Based on the power ripple self-detection system based on MCU built-in resources provided in Embodiment 1 of this application, correspondingly, Embodiment 3 of this application also provides a power ripple self-detection method based on MCU built-in resources, such as... Figure 2 As shown, it includes: S1. By blocking the DC component of the MCU power rail with a DC blocking capacitor, the AC component of the power ripple is coupled to a programmable gain amplifier, and the gain value of the programmable gain amplifier is configured by the digital computing unit to linearly amplify the AC ripple; S2. The digital computing unit controls the first digital-to-analog converter to scan upwards from the common-mode bias voltage of the programmable gain amplifier, and records the upper limit threshold voltage corresponding to the first high-speed comparator output flipping from high level to low level; at the same time, it controls the second digital-to-analog converter to scan downwards from the common-mode bias voltage of the programmable gain amplifier, and records the lower limit threshold voltage corresponding to the second high-speed comparator output flipping from high level to low level. S3. Calculate the peak-to-peak value of the amplified ripple based on the difference between the upper threshold voltage and the lower threshold voltage, and then divide it by the gain value of the programmable gain amplifier to obtain the original peak-to-peak value of the MCU power rail. S4. Fix the output of the first digital-to-analog converter or the second digital-to-analog converter to the common-mode bias voltage, and use the internal counter of the digital computing unit to capture the periodic edge signal of the corresponding high-speed comparator output to calculate the period of the original ripple.

[0071] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computing software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0072] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0073] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A power ripple self-detection system based on MCU built-in resources, characterized in that, All active modules of the system are built into the MCU, including: A DC blocking capacitor, whose input is connected to the power rail of the MCU to be tested and whose output is connected to the input of the programmable gain amplifier (PGA), is used to block the DC component of the MCU power rail and couple only the AC component of the power ripple to the signal path. A programmable gain amplifier (PGA) is used to linearly amplify the AC component of the coupled power supply ripple in a programmable manner. The first digital-to-analog converter DAC1 generates an independently adjustable upper threshold voltage; The second digital-to-analog converter DAC2 generates an independently adjustable lower threshold voltage; The first high-speed comparator CMP1 has its non-inverting input connected to the output of the programmable gain amplifier PGA and its inverting input connected to the output of the first digital-to-analog converter DAC1, and is used to compare the amplified ripple signal with the upper threshold voltage. The second high-speed comparator CMP2 has its non-inverting input connected to the output of the second digital-to-analog converter DAC2 and its inverting input connected to the output of the programmable gain amplifier PGA. It is used to compare the lower threshold voltage with the amplified ripple signal. The low dropout linear regulator (LDO) has its input connected to the power rail of the MCU, and its output independently supplies power to the programmable gain amplifier (PGA), the first digital-to-analog converter (DAC1), the second digital-to-analog converter (DAC2), the first high-speed comparator (CMP1), the second high-speed comparator (CMP2), and the digital computing unit, thereby achieving power isolation between the measurement circuit and the power rail of the MCU under test. A digital computing unit, connected to the output terminals of the first high-speed comparator CMP1 and the second high-speed comparator CMP2, and the control terminals of the first digital-to-analog converter DAC1 and the second digital-to-analog converter DAC2, is used to perform the following operations: The first digital-to-analog converter DAC1 is controlled to increment upwards to perform threshold scanning, and the second digital-to-analog converter DAC2 is controlled to decrement downwards to perform threshold scanning. The threshold voltages corresponding to the output flips of the first high-speed comparator CMP1 and the second high-speed comparator CMP2 are recorded. The peak-to-peak value of the original ripple of the MCU power rail is calculated and deduced. At the same time, the period of the original ripple is measured using an internal counter.

2. The power supply ripple self-detection system of claim 1, wherein, The digital computing unit is configured to dynamically configure the gain value of the programmable gain amplifier according to the expected ripple amplitude range of the MCU power rail, such that the peak-to-peak value of the amplified AC ripple signal does not exceed the input dynamic range of the first high-speed comparator CMP1 and the second high-speed comparator CMP2.

3. The power supply ripple self-detection system of claim 1, wherein, The DC blocking capacitor is either a programmable capacitor array integrated inside the MCU, or an external discrete ceramic capacitor connected between the MCU power rail and the input terminal of the programmable gain amplifier (PGA).

4. The power supply ripple self-detection system of claim 1, wherein, The digital computing unit is also used to perform system zero-point calibration: When the MCU power rail is in a known low ripple state during the initial power-on phase of the system and all non-essential peripherals are not started, a complete threshold scan measurement is performed. The measurement result is stored as the inherent offset error of the system, and all subsequent measurement results are automatically compensated by subtracting the inherent offset error.

5. The power supply ripple self-detection system of claim 1, wherein, The first high-speed comparator CMP1 and the second high-speed comparator CMP2 are combined into a single MCU-built-in high-speed comparator. The system also includes an analog switch built into the MCU, whose input terminals are respectively connected to the output terminals of the programmable gain amplifier PGA, the output terminals of the first digital-to-analog converter DAC1 and the second digital-to-analog converter DAC2, and whose output terminals are respectively connected to the non-inverting input terminal and the inverting input terminal of the high-speed comparator. The digital computing unit controls the analog switch to switch the input polarity of the high-speed comparator in a time-division manner, and performs peak detection and trough detection in sequence.

6. A power ripple self-detection method based on MCU built-in resources, implemented by the power ripple self-detection system as described in any one of claims 1-5, characterized in that, Includes the following steps: S1. By blocking the DC component of the MCU power rail with a DC blocking capacitor, the AC component of the power ripple is coupled to a programmable gain amplifier, and the gain value of the programmable gain amplifier is configured by the digital computing unit to linearly amplify the AC ripple; S2. The digital computing unit controls the first digital-to-analog converter to scan upwards from the common-mode bias voltage of the programmable gain amplifier, and records the upper limit threshold voltage corresponding to the first high-speed comparator output flipping from high level to low level; at the same time, it controls the second digital-to-analog converter to scan downwards from the common-mode bias voltage of the programmable gain amplifier, and records the lower limit threshold voltage corresponding to the second high-speed comparator output flipping from high level to low level. S3. Calculate the peak-to-peak value of the amplified ripple based on the difference between the upper threshold voltage and the lower threshold voltage, and then divide it by the gain value of the programmable gain amplifier to obtain the original peak-to-peak value of the MCU power rail. S4. Fix the output of the first digital-to-analog converter or the second digital-to-analog converter to the common-mode bias voltage, and use the internal counter of the digital computing unit to capture the periodic edge signal of the corresponding high-speed comparator output to calculate the period of the original ripple.

7. The power supply ripple self-detection method of claim 6, wherein, In step S2, the threshold scanning adopts a successive approximation scanning method or a segmented approximation scanning method. The scanning step size is dynamically adjusted according to the resolution and measurement accuracy requirements of the first digital-to-analog converter and the second digital-to-analog converter. Each threshold point is scanned at least 3 times and the average value is taken as the final recorded value.

8. The power supply ripple self-detection method of claim 6, wherein, In step S4, the internal counter is configured to input capture mode, using two adjacent rising edges or two adjacent falling edges of the output of the first high-speed comparator or the second high-speed comparator as trigger signals to continuously capture at least 10 cycles of count values, and after removing the maximum and minimum values, the arithmetic mean is taken as the period of the final raw ripple.

9. The power supply ripple self-detection method of claim 6, wherein, It also includes online monitoring and anomaly early warning steps: The digital computing unit periodically executes the measurement process of steps S1 to S4, comparing the original ripple peak value obtained from each measurement with a preset health threshold. When the measurement results exceed the health threshold for three consecutive times, a hardware alarm signal is generated or a preset power management action is executed.

10. The power supply ripple self-detection method of claim 6, wherein, It also includes a gain adaptive adjustment step: After the amplified peak-to-peak value of the ripple is obtained by the first threshold scan, if the peak-to-peak value exceeds the preset upper limit threshold or is lower than the preset lower limit threshold of the input dynamic range of the first high-speed comparator and the second high-speed comparator, the digital computing unit automatically adjusts the gain value of the programmable gain amplifier and re-executes the measurement process of steps S1 to S3 until the amplified peak-to-peak value of the ripple is between the preset upper limit threshold and the preset lower limit threshold.

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