An arithmetic logic circuit suitable for balanced ternary systems

Abstract

This invention discloses an arithmetic logic circuit suitable for balanced ternary systems, comprising a unary balanced ternary operation circuit, a balanced ternary half-adder circuit, a balanced ternary full-adder circuit, and a balanced ternary multiplier circuit. Single-input logic conversion is achieved through the combination of polarized ternary inverters and transistors. The half-adder consists of a basic unit and a transmission gate, realizing two-bit summation and carry output. The full-adder employs two cascaded half-adders and optimizes the carry path, significantly shortening the critical path and reducing the number of transistors. The multiplier uses the basic unit as the control core and combines it with a standard ternary inverter to achieve accurate multiplication. This invention overcomes the interconnection bottleneck of traditional binary logic, avoids the high hardware overhead of unbalanced ternary logic circuits in signed number calculations, and avoids the accuracy loss of approximate calculations in existing balanced ternary logic circuits. It has advantages such as simplified structure, low latency, low power consumption, and accurate operation, and is suitable for high-performance computing scenarios such as artificial intelligence, big data, and very large-scale integrated circuits.

Description

Technical Field

[0001] This invention relates to the field of digital integrated circuit technology, specifically to an arithmetic logic circuit suitable for balanced ternary systems, and is particularly suitable for basic arithmetic operation units in very large-scale integrated circuits, artificial intelligence chips, big data processing chips, and high-speed digital signal processing systems. Background Technology

[0002] Currently, artificial intelligence, big data processing, and 5G / 6G communication technologies have become important drivers of innovation and transformation across various fields. The application scenarios of these cutting-edge technologies typically involve real-time interaction of massive amounts of data and complex low-level calculations, placing extremely high demands on the data throughput and computing performance of hardware chips. At present, the vast majority of very large-scale integrated circuits (VLSI) are still designed based on traditional binary logic, utilizing only the high and low voltage states of the device to achieve logic switching and information representation.

[0003] As chip manufacturing processes continue to evolve and system integration levels increase, the limitations of traditional binary logic in information carrying capacity are becoming increasingly prominent, posing a key bottleneck to further improvements in chip performance. In modern very large-scale integrated circuits (VLSI), over 70% of the chip's physical area is used for metal wiring. With the number of interconnects growing exponentially, the massive interconnect network not only occupies valuable chip space but also induces parasitic capacitance and resistance effects, leading to severe gate delay and signal crosstalk problems. Practice has shown that simply reducing device size is no longer sufficient to effectively overcome the power consumption and speed bottlenecks caused by interconnects; the industry urgently needs to explore entirely new design solutions at the logic architecture level.

[0004] Against this backdrop, multi-valued logic is widely recognized as an ideal alternative technology for improving the data processing capabilities and transmission efficiency of circuit systems. Compared to binary logic, multi-valued logic can carry more logic states on a single node, significantly increasing the information storage and transmission density of a single signal line, thereby greatly reducing the number of interconnects in the circuit, lowering wiring complexity, and improving chip space utilization. According to information theory and circuit design theory, the circuit synthesis complexity C is closely related to the logic radix R and its value range N. Mathematical models show that the circuit hardware complexity is lowest when the logic radix R equals the natural constant e (approximately 2.718). Since practical circuits cannot use non-integer radixes, the integer closest to e, "3," i.e., ternary logic, becomes the optimal and most suitable radix choice for engineering implementation in the multi-valued logic system. Furthermore, ternary logic can represent the same value with a shorter bit width, giving it unique application advantages in digital signal processing fields such as convolution operations and Fast Fourier Transform (FFT).

[0005] Although ternary logic holds immense theoretical potential, and basic arithmetic units such as adders and multipliers are core components of digital circuits, current research on ternary combinational logic circuits (including half-adders, full adders, and multipliers) largely focuses on unbalanced ternary logic, whose logic states are typically represented as 0, 1, and 2. When processing signed numbers (positive and negative), unbalanced ternary logic requires the introduction of an extra sign bit and the configuration of complex logic conversion circuits, which not only disrupts the symmetry of the circuit structure but also leads to significant hardware overhead and increased power consumption. In contrast, balanced ternary logic employs a symmetrical logic state distribution (i.e., -1, 0, +1), exhibiting excellent structural consistency in numerical operations and hardware implementation. This inherent symmetry allows for the direct and efficient representation and processing of signed numbers, completely eliminating the need for an extra sign bit, significantly simplifying the internal architecture of arithmetic logic units, and improving signal integrity and noise robustness. However, existing balanced ternary logic still suffers from significant technical shortcomings at the underlying circuit implementation level. Current balanced ternary arithmetic circuits generally suffer from an excessive number of transistors required for individual logic gates and high overall circuit power consumption. Particularly in core units such as full adders, the excessively long carry generation critical path directly leads to high computational latency. These underlying hardware implementation defects severely limit the large-scale application of balanced ternary logic in high-efficiency, low-power computing systems.

[0006] For example, the existing patent document CN119652311A, entitled "Ternary Logic Gate Circuit, Computing Circuit, Chip, and Electronic Device," employs unbalanced ternary logic (logic states represented as 0, 1, 2) and balanced ternary logic (logic states represented as -1, 0, +1). It proposes a balanced ternary full adder, an unbalanced ternary half adder, a full adder, and a multi-bit multiplier. To simplify the structure of ternary logic circuits and reduce the number of transistors, existing technologies design basic ternary logic gate circuits capable of "adding 1 (incrementing)" or "subtracting 1 (decreasing)" of the input logic value. These gates are then cascaded and applied to complex computational circuits such as ternary summation and multiplication, combining the single-variable functions of ternary logic. However, patent document CN119652311A mainly proposes an unbalanced ternary design. When performing signed number arithmetic operations, unbalanced ternary logic inevitably requires additional sign bits and complex logic conversion circuits, disrupting the symmetry of the circuit structure and significantly increasing the hardware overhead of the arithmetic logic unit. This design faces multiple performance bottlenecks in its underlying hardware implementation. The complex cascading of basic logic gates leads to a surge in the number of transistors used and the total number of stacked transistors. The lengthy gate-level interconnect structure weakens the driving capability of signals when transmitting between multiple transistor levels, resulting in low signal propagation efficiency and increased power consumption. Furthermore, the excessive cascading levels introduce a certain transmission delay, lengthening the response time of the critical path.

[0007] For example, in existing patent document CN117850737A, a balanced ternary approximation calculation method, apparatus, computer device, and storage medium are described. This technical solution employs a balanced ternary system with symmetrical logic states. Because the traditional balanced ternary multiplication calculation process involves the sequential cascading of sub-modules such as multipliers, half-adders, and full adders, each step of the operation requires waiting for a carry signal, resulting in a long critical path and low computational efficiency. To solve the carry delay problem, this solution proposes an "approximate calculation" architecture. By introducing "approximate addition logic gates" to replace part of the precise addition logic, it directly outputs an approximate value under specific input conditions (such as when all inputs are 1 or all are -1), thus bypassing the long carry path for approximate multiplication operations. However, in order to alleviate the lengthy carry delay in the arithmetic circuit, the approximate calculation in patent document CN117850737A inevitably uses approximate addition logic gates to replace precise logic. This still sacrifices the computational accuracy of the circuit, introducing inherent computational errors during the operation, making the solution unsuitable for precise arithmetic logic units or high-fidelity systems that have stringent requirements for data accuracy.

[0008] In summary, existing technologies cannot simultaneously meet the comprehensive requirements of balanced ternary, accurate calculation, low transistor count, low latency, and low power consumption. They are also unable to balance high-precision computing with hardware efficiency, which severely restricts the practical application and promotion of balanced ternary logic in high-performance computing chips. Summary of the Invention

[0009] The purpose of this invention is to overcome the bottlenecks of traditional binary logic interconnection, the large hardware overhead of unbalanced ternary logic, and the high power consumption, long delay, and insufficient accuracy of existing balanced ternary arithmetic circuits. It provides an arithmetic logic circuit that is simple in structure, has fewer transistors, more accurate operation, lower delay, and better power consumption, suitable for balanced ternary systems.

[0010] To achieve the above objectives, the present invention is implemented through the following technical solution: The present invention provides a unary balanced ternary arithmetic circuit suitable for balanced ternary systems, including a single-input single-output dedicated arithmetic circuit that can adapt to the balanced ternary logic system, wherein the logic states of the balanced ternary logic system are -1, 0, and +1. The dedicated operational circuit includes AM circuit, A - Circuit, A + Circuit, A - Circuit, A + The circuits, including the Az circuit, each include a polarity ternary inverter, a P-type transistor, and an N-type transistor; each circuit is functionally matched with corresponding pull-up and pull-down level combinations, which are one of VDD and Gnd, VDD and VDD / 2, and VDD / 2 and Gnd, respectively corresponding to the +1 and -1, +1 and 0, and 0 and -1 levels of balanced ternary logic; among them, the AM circuit and A...- Circuit, A + The circuit is connected to a positive polarity ternary inverter PTI, A - Circuit, A + The circuit and Az circuit are connected to the negative polarity ternary inverter NTI; the input balanced ternary logic signal is processed by the corresponding polarity ternary inverter into a transistor on / off control signal. The on and off states of the P-type transistor and N-type transistor in the circuit are controlled by the control signal to achieve a precise mapping from the input signal to the preset balanced ternary logic output signal. Each core circuit achieves its own input and output logic relationship by using the on and off states of the transistor in conjunction with the corresponding pull-up and pull-down levels.

[0011] Preferably, the pull-up and pull-down levels of the AM circuit are VDD and Gnd, corresponding to balanced ternary logic levels +1 and -1, respectively. The input-output logic relationship of the AM circuit is as follows: when the input balanced ternary logic signal A is 0, the output logic level is +1; when the input signal A is -1 or +1, the output logic level is -1. The input signal A is processed into the AP signal by the positive polarity ternary inverter PTI. The AP signal serves as the on / off control signal for transistors N1, N2 and P0, P1. When the input signal A is 0, the AP signal outputs a logic level of +1, and transistors N1 and N2 are simultaneously in the on state, pulling the AM signal at the output terminal down to the logic level of -1. When the input signal A is -1 or +1, transistors P0 and P1 are both in the on state, and transistors N1 and N2 are not simultaneously in the on state, so that the AM signal at the output terminal remains at the logic level of +1.

[0012] Preferably, the A - The circuit's pull-up and pull-down levels are VDD / 2 and Gnd, corresponding to balanced ternary logic levels 0 and -1, respectively. Its input-output logic relationship is as follows: when input signal A is -1, the output logic level is -1; when input signal A is 0 or +1, the output logic level is 0. Input signal A is processed into the AN signal by a negative polarity ternary inverter NTI. The AN signal controls the on / off state of the P-type and N-type transistors in the circuit. When input signal A is -1, the AN signal outputs a logic level of -1, the P-type transistor is turned on, and the circuit outputs a logic level of -1; when input signal A is 0 or +1, the AN signal outputs a logic level of +1, the N-type transistor is turned on, and the circuit outputs a logic level of 0. -The pull-up and pull-down levels of the circuit are also VDD / 2 and Gnd, respectively. Its input-output logic relationship is as follows: when the input signal A is +1, the output logic level is 0; when the input signal A is -1 or 0, the output logic level is -1. The input signal A is processed into the AP signal by the positive polarity ternary inverter PTI. The AP signal controls the on / off state of the P-type and N-type transistors in the circuit. When the input signal A is +1, the AP signal controls the P-type transistor to conduct, and the circuit outputs a logic level of 0; when the input signal A is -1 or 0, the AP signal controls the N-type transistor to conduct, and the circuit outputs a logic level of -1.

[0013] Preferably, the A + The circuit's pull-up and pull-down levels are VDD and VDD / 2, corresponding to balanced ternary logic levels +1 and 0, respectively. Its input-output logic relationship is as follows: when input signal A is +1, the output logic level is +1; when input signal A is -1 or 0, the output logic level is 0. Input signal A is processed into an AP signal by a positive polarity ternary inverter PTI. The AP signal controls the on / off state of the P-type and N-type transistors in the circuit. When input signal A is +1, the AP signal controls the P-type transistor to conduct, and the circuit outputs a logic level of +1; when input signal A is -1 or 0, the AP signal controls the N-type transistor to conduct, and the circuit outputs a logic level of 0. + The pull-up and pull-down levels of the circuit are VDD / 2 and Gnd, respectively, corresponding to balanced ternary logic levels 0 and -1. Its input-output logic relationship is as follows: when input signal A is -1, the output logic level is 0; when input signal A is 0 or +1, the output logic level is +1. Input signal A is processed into the AN signal by the negative polarity ternary inverter NTI. The AN signal controls the on / off state of the P-type and N-type transistors in the circuit. When input signal A is -1, the AN signal controls the N-type transistor to conduct, and the circuit outputs a logic level of 0; when input signal A is 0 or +1, the AN signal controls the P-type transistor to conduct, and the circuit outputs a logic level of +1.

[0014] Preferably, the pull-up and pull-down levels of the Az circuit are VDD and Gnd, corresponding to balanced ternary logic levels +1 and -1, respectively. Its input-output logic relationship is as follows: when the input signal A is -1, the output logic level is -1; when the input signal A is 0 or +1, the output logic level is +1. The input signal A is processed into the AN signal by the negative polarity ternary inverter NTI. The AN signal serves as the on / off control signal for the P-type and N-type transistors in the circuit. When the input signal A is -1, the AN signal outputs a logic level of -1, the N-type transistor is turned on, and the output signal is pulled low to logic level -1. When the input signal A is 0 or +1, the AN signal outputs a logic level of +1, the P-type transistor is turned on, and the output signal is pulled up to logic level +1.

[0015] This invention discloses a ternary half-adder circuit suitable for balanced ternary systems. It employs the aforementioned unary balanced ternary arithmetic circuit, combined with three transmission gates TG0, TG1, and TG2. The half-adder has two balanced ternary logic input ports, with input signals A and B, and two output ports, outputting a sum signal Sum and a carry signal Carry, respectively. Input signal A is processed by the corresponding unary balanced ternary arithmetic circuit to generate control signals AN, AM, and AP. These three control signals independently regulate transmission gates TG0, TG1, and TG2. The on and off states of TG1 and TG2 are controlled. B2, B, and B1 are used as input signals to transmission gates TG0, TG1, and TG2, respectively. The logical mapping relationship between B2 and input signal B is as follows: when B is -1, 0, or +1, B2 is +1, -1, or +1. The logical mapping relationship between B1 and input signal B is as follows: when B is -1, 0, or +1, B1 is 0, +1, or -1. The logical mapping between input signals A and B and the sum signal Sum and carry signal Carry is achieved by switching the transmission gates on and off.

[0016] Preferably, the on / off linkage switching of the transmission gate and carry branch is realized based on different values ​​of the input signal A: When the input signal A is -1, the AN signal processed by the negative polarity ternary inverter NTI is +1, controlling the transmission gate TG0 to turn on and the transmission gates TG1 and TG2 to turn off, and the Sum signal output equals B2. At the same time, the CN1 of the carry branch is turned on, and the Carry signal output equals B⁻. When the input signal A is 0, the AM signal processed by the AM circuit is -1, controlling the transmission gate TG1 to turn on and the transmission gates TG0 and TG2 to turn off, and the Sum signal output equals B. At the same time, the CP0 of the carry branch is turned on, and the Carry signal output is a balanced ternary logic level 0. When the input signal A is +1, the AP signal processed by the positive polarity ternary inverter PTI is -1, controlling the transmission gate TG2 to turn on and the transmission gates TG0 and TG1 to turn off, and the Sum signal output equals B1. At the same time, the CP1 of the carry branch is turned on, and the Carry signal output equals B⁻. + .

[0017] This invention discloses a ternary full adder circuit suitable for balanced ternary systems. It employs a ternary half adder circuit as its core operational unit. The full adder has three balanced ternary logic input ports with input signals A, B, and C, and two output ports that output a sum signal Sum. ABC With carry signal Carry ABC It includes at least a first topology full adder, which is composed of two cascaded ternary half adders and a balanced ternary ANY logic gate. The first ternary half adder is connected to input signals A and B and outputs an intermediate sum signal SUM. ABThe first carry signal CARRY1 is connected to the second ternary half-adder, which is connected to the input signal C and the intermediate sum signal SUM. AB The final output signal Sum ABC The balanced ternary ANY logic gate has two input ports and one output port. The two input ports are respectively connected to the first carry signal CARRY1 and the second carry signal CARRY2, and the output port outputs the final carry signal Carry of the full adder. ABC .

[0018] Preferably, it also includes a second topology carry-optimized full adder, which comprises the unary balanced ternary arithmetic circuit and the ternary half-adder; the summing circuit of the two-stage ternary half-adder sequentially processes the input signals A, B and the intermediate sum signal to achieve the final sum signal Sum. ABC The system performs precise calculations; it extracts the output signal of the first-stage half-adder summing circuit and the control signal after the input signal C is processed by the unary balanced three-value operation circuit, and designs a dedicated carry circuit based on the level transmission characteristics of the transistor. This dedicated carry circuit directly outputs the final carry signal CarryABC of the full adder. The dedicated carry circuit eliminates the traditional multi-stage cascaded structure and directly generates the carry through the operation signal of the first-stage half-adder output and the input signal C, thus shortening the critical carry path.

[0019] This invention discloses a ternary multiplier circuit suitable for balanced ternary systems. Based on this circuit as the basic hardware unit, it incorporates a standard ternary inverter (STI) and a transmission gate. The multiplier has two balanced ternary logic input ports, with input signals A and B, and a product output port. The transmission gate is controlled by three signals: BSTI, VDD / 2, and B. BSTI is the signal obtained by processing input signal B through the STI, and VDD / 2 corresponds to a balanced ternary logic level of 0. Different values ​​of input signal A control the transmission gate to select different branches, thus achieving balanced ternary multiplication: when input signal A is -1, the transmission gate selects the BSTI branch, and the multiplier outputs the value of B processed by the STI; when input signal A is 0, the transmission gate selects the VDD / 2 branch, and the multiplier directly outputs a balanced ternary logic level of 0; when input signal A is +1, the transmission gate selects the B branch, and the multiplier directly outputs the original value of input signal B.

[0020] Compared with the prior art, the present invention has the following beneficial effects: High information density and low interconnect overhead: The balanced ternary logic is used, with a single node carrying three states, reducing bit width and number of interconnects, reducing parasitic effects and gate delay, and improving chip area utilization.

[0021] Accurate calculation and low latency: Zero-error accurate calculation throughout the process, eliminating approximate calculation; full adder carry path optimization, eliminating multi-level cascade waiting, and significantly reducing latency.

[0022] Simplified hardware and low power consumption: By combining unary arithmetic circuits with transmission gates, the number of transistors is greatly reduced, and power consumption, delay product (PDP), and energy delay product (EDP) are optimized.

[0023] Symmetrical structure, adaptable to signed numbers: No sign bit and conversion circuit required, simple hardware architecture, strong noise resistance and robustness, suitable for high-precision digital computing systems. Attached Figure Description

[0024] Figure 1 Schematic diagram of AM circuit structure.

[0025] Figure 2 A⁻ Circuit structure diagram.

[0026] Figure 3 A + Circuit structure diagram.

[0027] Figure 4 A - Circuit structure diagram.

[0028] Figure 5 A + Circuit structure diagram.

[0029] Figure 6 A z Circuit structure diagram.

[0030] Figure 7 Schematic diagram of a balanced triple half-adder circuit.

[0031] Figure 8 Input-output logic diagram of a balanced ternary half-adder.

[0032] Figure 9 Schematic diagram of the first topology balanced ternary full adder circuit.

[0033] Figure 10 Input-output logic diagram of a balanced ternary full adder.

[0034] Figure 11 Schematic diagram of the second topology carry-optimized balanced ternary full adder circuit.

[0035] Figure 12 A schematic diagram comparing the critical path of the full adder of this invention with that of existing full adders.

[0036] Figure 13 Schematic diagram of a balanced ternary multiplier circuit.

[0037] Figure 14 A schematic diagram of the input-output logic relationship of a balanced ternary multiplier.

[0038] Figure 7 (a) Sum output section, (b) Carry output section Detailed Implementation

[0039] The following will refer to the accompanying drawings in the embodiments of the present invention. Figures 1-14 The technical solutions in the embodiments of the present invention are clearly and completely described herein. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0040] The technical problems to be solved by this invention are: 1) Overcoming the interconnection bottlenecks of large wiring area, strong parasitic effects, and high gate delay in traditional binary logic; 2) Solving the problems of unbalanced ternary logic requiring a sign bit, complex conversion circuits, hardware asymmetry, and high overhead; 3) Improving the shortcomings of existing balanced ternary arithmetic circuits, such as a large number of transistors, high power consumption, long carry critical path of full adder, and high delay, while avoiding the accuracy loss caused by approximate calculation. Technical solution / principle of the invention: This invention provides an arithmetic logic circuit suitable for balanced ternary systems, which adopts a balanced ternary logic system of -1, 0, and +1. The core technologies include: a unary balanced ternary operation circuit, a balanced ternary half-adder circuit, a balanced ternary full-adder circuit, and a balanced ternary multiplier circuit.

[0041] Technical Content 1: Univariate Balanced Ternary Operation Circuit It is a single-input single-output structure, including AM circuit, A⁻ circuit, A⁺ circuit, and A... - Circuit, A + The circuit, Az circuit, uses positive polarity ternary inverter (PTI), negative polarity ternary inverter (NTI) and P-type / N-type transistors to match the pull-up / pull-down levels composed of VDD, VDD / 2 and Gnd according to their functions to achieve fixed input / output logic mapping.

[0042] Technical Content 2: Balanced Triple Half-Adder Circuit Based on a univariate balanced ternary arithmetic circuit and transmission gate, with two inputs A and B, and outputs Sum and Carry, the transmission gate is selected by controlling the logic state of input A to achieve accurate output of Sum and Carry.

[0043] Technical Content 3: Balanced Triple Full Adder Circuit Includes two topologies: First topology: Two cascaded half-adders are used in conjunction with balanced three-valued ANY gates to generate carry; Second topology: Carry-optimized structure, eliminating multi-stage cascading, directly generating carry by using the unary operation signal of the first-stage half-adder output and input C, significantly shortening the critical path and reducing the number of transistors.

[0044] Technical Content 4: Balanced Triple Multiplier Circuit Based on a standard ternary inverter (STI) and a transmission gate, with two inputs A and B, the branch is selected according to different states of A to achieve accurate multiplication.

[0045] like Figure 1 The diagram shows the AM circuit, which outputs a logic level of +1 when the balanced ternary logic signal is 0, and a logic level of -1 otherwise. In the specific circuit, AP indicates that signal A passes through a positive ternary inverter (PTI). Specifically, when the input signal is 0, AP outputs a logic level of +1, so transistors N1 and N2 are both on, pulling the output signal AM low to logic level -1. When A is not equal to logic level 0, transistors P0 and P1 are both on, and N1 and N2 are not simultaneously on, thus maintaining the output signal AM at logic level +1.

[0046] like Figure 2 The image shows A. - The circuit uses VDD / 2 and Gnd as pull-up and pull-down levels, respectively, corresponding to logic levels 0 and -1. This circuit ensures that when the input balanced ternary logic signal is -1, the output is logic level -1; otherwise, it outputs logic level 0. AN indicates that signal A passes through a negative ternary inverter (NTI). When input signal A is not logic level -1, AN outputs logic level +1; otherwise, it outputs logic level -1. In the specific circuit, the output signal of AN controls the final output signal. When input signal A is not logic level -1, the N-type transistor controlled by signal AN will conduct, while the P-type transistor will be cut off. Ultimately, the circuit achieves an output of logic level 0 only when the input signal A is -1, with the P-type transistor controlled by signal AN conducting.

[0047] like Figure 3 The image shows A. +The circuit has pull-up and pull-down levels of VDD and VDD / 2, respectively, which correspond to logic levels +1 and 0. This circuit ensures that when the input balanced three-valued logic signal is +1, the output is logic level +1; otherwise, it outputs logic level 0. In the specific circuit, the input signal A is controlled by the output signal of PTI. When the input signal A is not logic level +1, AP outputs a high level. At this time, the N-type transistor controlled by signal AP will conduct, while the P-type transistor will be cut off, resulting in an output logic level of 0. Ultimately, the circuit achieves an output logic level +1 only when the input signal A is +1, with the P-type transistor controlled by signal AN conducting.

[0048] like Figure 4 The image shows A. - The circuit has pull-up and pull-down levels of VDD / 2 and Gnd, respectively, which correspond to logic levels 0 and -1. This circuit ensures that when the input balanced three-valued logic signal is +1, the output is logic level 0; otherwise, it outputs logic level -1. In the specific circuit, the input signal A is controlled by the output signal of PTI. When the input signal A is not logic level +1, AP outputs a high level. At this time, the N-type transistor controlled by signal AP will conduct, while the P-type transistor will be cut off, resulting in an output logic level -1. Ultimately, the circuit achieves an output logic level 0 only when the input signal A is +1, and the P-type transistor controlled by signal AN conducts.

[0049] like Figure 5 The image shows A. + The circuit uses VDD / 2 and Gnd as pull-up and pull-down levels, respectively, which correspond to logic levels 0 and -1. This circuit ensures that when the input balanced three-valued logic signal is -1, the output is logic level 0; otherwise, it outputs logic level +1. In the specific circuit, the input signal A is controlled by the output signal of NTI. When the input signal A is not logic level -1, AN outputs a low level. At this time, the P-type transistor controlled by signal AN will conduct, while the N-type transistor will be cut off, resulting in an output logic level +1. Ultimately, the circuit achieves an output logic level 0 only when the input signal A is -1, with the N-type transistor controlled by signal AN conducting.

[0050] like Figure 6 The image shows A. zThe circuit uses VDD and Gnd as pull-up and pull-down levels, respectively, which correspond to logic levels +1 and -1. This circuit ensures that when the input balanced three-valued logic signal is -1, the output is logic level -1; otherwise, it outputs logic level +1. In the specific circuit, the input signal A is controlled by the output signal of NTI. When the input signal A is not logic level -1, AN outputs a low level. At this time, the P-type transistor controlled by signal AN will conduct, while the N-type transistor will be cut off, resulting in an output logic level +1. Ultimately, the circuit achieves an output logic level -1 only when the input signal A is -1, with the N-type transistor controlled by signal AN conducting.

[0051] like Figure 7 The diagram shows a balanced ternary half-adder circuit, where A and B are the two input signals of the half-adder, and Sum and Carry are the sum and carry outputs of the half-adder, respectively. In a balanced ternary logic half-adder, the relationship between the inputs and outputs is as follows: Figure 8 The circuit demonstrates how a half-adder is designed by combining various unary balanced ternary arithmetic circuits and transmission gates. Figure 7 (a) shows the SUM output section of a half-adder, which uses three transmission gates, TG0, TG1, and TG2, controlled by one of the input signals A and its output through a unary arithmetic circuit. B 2 B, B 1 These are used as input signals for transmission gates TG0, TG1, and TG2, respectively. 2 The relationship between B and the input signal B is as follows: when B is -1, 0, and +1 respectively, B 2 The values ​​are +1, -1, and +1, respectively. B 1 The relationship between B and the input signal B is as follows: when B is -1, 0, and +1 respectively, B 2 The values ​​are 0, +1, and -1 respectively. When A=-1 (AN=+1): TG0 is on, SUM output equals B2, and CN1 is on, Carry output equals B⁻. When A=0 (AM=-1): TG1 is on, SUM output equals B; and CP0 is on, Carry output is logic level 0. When A=+1 (AP=-1): TG2 is on, SUM output equals B1, and CP1 is on, Carry output equals B⁺.

[0052] like Figure 9 The diagram shows the first proposed balanced ternary full adder circuit, where A, B, and C are the input signals of the full adder, Sum ABC With Carry ABC These represent the sum and carry output of the final full adder. In a balanced ternary logic full adder, the logical relationship between the input and output is as follows: Figure 10The circuit demonstrates this. It incorporates the proposed half-adder design and implements the final carry function through a balanced ternary ANY logic gate. ABC Output. In the circuit section of SUM, two proposed half-adder structures are used. The first half-adder has inputs A and B and output SUM. AB And CARRY1; the input signals of the second half-adder are C and SUM. AB The output signal is the final Sum. ABC Using the carry outputs CARRY1 and CARRY2 of the two half-adders as inputs to a balanced ternary ANY logic gate, the final Carry is obtained. ABC .

[0053] like Figure 11 The diagram shows another carry-optimized balanced ternary full adder circuit, where A, B, and C are the input signals of this full adder, Sum ABC With Carry ABC These represent the sum and carry output of the final full adder. In a balanced ternary logic full adder, the logical relationship between the input and output is as follows: Figure 10 The circuit demonstrates this. It combines the proposed unary ternary arithmetic logic circuit with a half-adder design. The final sum is achieved through the summing circuit in the two-stage half-adder. ABC Signal calculation. By combining the output of the first-stage summing circuit with the output of the unary balanced ternary arithmetic circuit of the input signal C, and the transmission characteristics of the transistor, the final carry-in circuit design was realized.

[0054] like Figure 12 Compared to existing full adders, the proposed full adder 1 can directly utilize a half adder structure and achieve the final carry output through any logic gates. Existing full adders require inverting the carry output from the half adders, then passing the inverted carry signal from two half adders through any logic gates to obtain the final carry. Therefore, the carry signal in a full adder has a relatively long critical path. In contrast, the proposed full adder 2 only requires the signal from a complete half adder, which, along with the input signal C, passes through the proposed TCCM circuit module to obtain the final carry output, significantly reducing the critical path length and the number of transistors.

[0055] like Figure 13 The diagram shows a balanced ternary multiplier circuit, where A and B are input signals. The logical relationship between the input and output of the ternary multiplier circuit is as follows: Figure 14The circuit is shown below. In this circuit, STI stands for Standard Triple Inverter (PTI). By combining the STI with a transmission gate, the final product output is achieved. In this multiplier, B... STI The three signals VDD / 2 and B are used as the transmission signals of the transmission gate. When A=-1 (A Z When A=-1 (AP=-1, AN=+1), the output B is the value of STI; when A=0 (AP=-1, AN=+1), VDD / 2 will be directly output, which is logic level 0; when A=+1 (AP=-1), the current value of B will be directly output.

[0056] The following detailed description is based on specific embodiments, but the scope of protection of the present invention is not limited to these embodiments. Univariate balanced ternary arithmetic circuit

[0057] This embodiment is a single-input single-output balanced three-valued arithmetic circuit with logic states of -1, 0, and +1.

[0058] AM circuit: Input signal A is generated into AP via PTI; pull-up / pull-down levels are VDD (+1) and Gnd (-1).

[0059] A=0→AP=+1→N1, N2 conduct→output AM=-1; A=-1 / +1→P0, P1 conduct, N1 / N2 do not conduct simultaneously→output AM=+1.

[0060] A⁻ Circuit: Pull-up / pull-down levels are VDD / 2 (0) and Gnd (-1); Input A generates AN via NTI. A=-1→AN=-1→P transistor turns on→output -1; A=0 / +1→AN=+1→N transistor turns on→output 0.

[0061] A + Circuit: Pull-up / pull-down levels are VDD (+1) and VDD / 2 (0); Input A generates AP via PTI. A=+1 → P transistor turns on → output +1; A=-1 / 0 → N transistor turns on → output 0.

[0062] A ⁻ Circuit: Pull-up / pull-down levels are VDD / 2 (0) and Gnd (-1); Input A is generated as AP via PTI. A=+1→output 0; A=-1 / 0→output -1.

[0063] A + Circuit: Pull-up / pull-down levels are VDD / 2 (0) and Gnd (-1); input A is converted to AN via NTI. A=-1 → output 0; A=0 / +1 → output +1.

[0064] Az circuit: pull-up / pull-down levels are VDD (+1) and Gnd (-1); input A is generated into AN via NTI.

[0065] A=-1 → N transistor turns on → output -1; A=0 / +1 → P transistor turns on → output +1.

[0066] Example 2: Balanced Triple Half-Adder Circuit like Figure 7 As shown, the diagram includes a Sum output section (a) and a Carry output section (b), with inputs A and B, and outputs Sum and Carry. Transmission gates TG0, TG1, and TG2 are set, with inputs B2, B, and B1 respectively. B=-1 / 0 / +1→B2=+1 / -1 / +1; B=-1 / 0 / +1→B1=0 / +1 / -1.

[0067] Logical working method: A=-1 (AN=+1) → TG0 conducts → Sum=B2; CN1 conducts → Carry=B⁻; A=0 (AM=-1) → TG1 turns on → Sum=B; CP0 turns on → Carry=0; A=+1 (AP=-1) → TG2 conducts → Sum=B1; CP1 conducts → Carry=B⁺.

[0068] The input-output logic relationship of the half-adder is as follows: Figure 8 As shown.

[0069] Example 3: First Topology Balanced Triple Full Adder Circuit like Figure 9 As shown, the inputs are A, B, and C, and the output is Sum. ABC Carry ABC .

[0070] Half-adder 1 takes inputs A and B and outputs SUM. AB CARRY1; Half-adder 2 takes C as input and SUM_AB as output, and outputs Sum. ABC CARRY2; CARRY1 and CARRY2 are input to balanced ternary ANY gates, and the output is Carry. ABC .

[0071] The logical relationship is as follows: Figure 10 As shown.

[0072] Example 4: Second Topology Carry-Optimized Balanced Triple Adder Circuit like Figure 11 As shown, it is based on a univariate balanced ternary arithmetic circuit and a half-adder.

[0073] A two-stage half-adder summing circuit generates Sum ABC The first-stage half-adder output and input C are used as unary operation signals. Combined with the transmission characteristics of transistors, the carry is directly generated. ABC Eliminating multi-stage cascading significantly shortens the critical path and reduces the number of transistors.

[0074] Example 5: Balanced ternary multiplier circuit It is constructed based on a standard ternary inverter (STI) and a transmission gate, with inputs A and B, and output Product.

[0075] A=-1 → Select B_STI branch → Output B after STI; A=0 → Select VDD / 2 branch → Output 0; A=+1 → Select B branch → Directly output B.

[0076] Performance Comparison Comparison of the full adder of this invention with existing technologies (Table 1):

[0077] Current design: 134 transistors, power consumption 0.38μW, worst latency 60ps; The first full adder of this invention has 100 transistors, a power consumption of 0.35μW, and a worst-case delay of 48.76ps. The second full adder of this invention has 88 transistors, consumes 0.32μW, has a worst latency of 40.94ps, and its PDP and EDP are significantly better than existing solutions.

[0078] Industrial Applicability: This invention can be implemented using standard CMOS technology and is suitable for very large-scale integrated circuits such as artificial intelligence chips, big data processing, 5G / 6G communication, and digital signal processing. It can effectively improve computing speed, reduce power consumption and chip area, and has broad industrial application value.

[0079] In summary, this invention overcomes the drawback of high interconnect overhead in traditional binary logic, thereby increasing the information density of the circuit. Employing balanced ternary logic, it can carry more logic states (-1, 0, +1) on a single node compared to traditional binary logic. When processing the same amount of data, it effectively reduces the required signal bit width and the number of interconnects, thus reducing parasitic capacitance and gate delay caused by dense interconnections and improving the physical space utilization of the integrated circuit. The novel balanced ternary arithmetic circuit (including a half-adder, a full adder, and a multiplier) proposed in this invention achieves a perfect balance between zero-error accurate calculation and low latency compared to existing balanced ternary calculation techniques. Compared to existing approximate calculation schemes that sacrifice calculation accuracy for speed, this invention achieves more complete functionality while ensuring 100% logical integrity and calculation accuracy. To address the shortcomings of existing balanced ternary full adders, such as long critical paths and significant delays, the proposed design breaks away from the traditional multi-stage cascaded pattern in the carry output section. Instead, it utilizes only the output of the first-stage half adder and the third input signal, combined with a newly proposed three-input logic circuit module and a balanced unary ternary arithmetic circuit, to directly derive the final carry output. This design eliminates lengthy carry wait times at the underlying circuit topology level, significantly reducing delays while maintaining zero error. It achieves a streamlined circuit structure. In terms of hardware structure, by combining unary arithmetic units and transmission gate structures, and leveraging the characteristics of transistor transmission levels, the proposed balanced ternary half adder, full adder, and multiplier structures all use a very small number of transistors. This minimalist design not only significantly reduces the chip physical area occupied by the core arithmetic unit but also overcomes the problems of low signal propagation efficiency and weakened driving capability caused by transistor stacking redundancy in existing technologies.

[0080] Finally, it should be noted that the present invention is not limited to the above embodiments, and many variations are possible. All variations that can be directly derived or conceived by those skilled in the art from the disclosure of the present invention should be considered within the scope of protection of the present invention.

Claims

1. A single-element balanced ternary arithmetic circuit suitable for balanced ternary systems, characterized in that, It includes a dedicated single-input single-output arithmetic circuit that can adapt to a balanced ternary logic system, wherein the logic states of the balanced ternary logic system are -1, 0, and +1; A single-element balanced three-valued arithmetic circuit includes an AM circuit and an A circuit. - Circuit, A + Circuit, A - Circuit, A + The circuits, including the Az circuit, each include a polarity ternary inverter, a P-type transistor, and an N-type transistor; each circuit is functionally matched with corresponding pull-up and pull-down level combinations, which are one of VDD and Gnd, VDD and VDD / 2, and VDD / 2 and Gnd, respectively corresponding to the +1 and -1, +1 and 0, and 0 and -1 levels of balanced ternary logic; among them, the AM circuit and A... - Circuit, A + The circuit is connected to a positive polarity ternary inverter PTI, A - Circuit, A + The circuit and Az circuit are connected to the negative polarity ternary inverter NTI; the input balanced ternary logic signal is processed by the corresponding polarity ternary inverter into a transistor on / off control signal. The on and off states of the P-type transistor and N-type transistor in the circuit are controlled by the control signal to achieve a precise mapping from the input signal to the preset balanced ternary logic output signal. Each core circuit achieves its own input and output logic relationship by using the on and off states of the transistor in conjunction with the corresponding pull-up and pull-down levels.

2. The unary balanced ternary arithmetic circuit suitable for balanced ternary systems according to claim 1, characterized in that, The pull-up and pull-down levels of the AM circuit are VDD and Gnd, corresponding to balanced ternary logic levels +1 and -1, respectively. The input-output logic relationship of the AM circuit is as follows: when the input balanced ternary logic signal A is 0, the output logic level is +1; when the input signal A is -1 or +1, the output logic level is -1. The input signal A is processed into the AP signal by the positive polarity ternary inverter PTI. The AP signal serves as the on / off control signal for transistors N1, N2, P0, and P1. When the input signal A is 0, the AP signal outputs a logic level of +1, and transistors N1 and N2 are simultaneously on, pulling the AM signal at the output terminal down to a logic level of -1. When the input signal A is -1 or +1, transistors P0 and P1 are both on, and transistors N1 and N2 are not simultaneously on, keeping the AM signal at the output terminal at a logic level of +1.

3. The unary balanced ternary arithmetic circuit suitable for balanced ternary systems according to claim 1, characterized in that, The A - The circuit's pull-up and pull-down levels are VDD / 2 and Gnd, corresponding to balanced ternary logic levels 0 and -1, respectively. Its input-output logic relationship is as follows: when input signal A is -1, the output logic level is -1; when input signal A is 0 or +1, the output logic level is 0. Input signal A is processed into the AN signal by a negative polarity ternary inverter NTI. The AN signal controls the on / off state of the P-type and N-type transistors in the circuit. When input signal A is -1, the AN signal outputs a logic level of -1, the P-type transistor is turned on, and the circuit outputs a logic level of -1; when input signal A is 0 or +1, the AN signal outputs a logic level of +1, the N-type transistor is turned on, and the circuit outputs a logic level of 0. - The pull-up and pull-down levels of the circuit are also VDD / 2 and Gnd, respectively. Its input-output logic relationship is as follows: when the input signal A is +1, the output logic level is 0; when the input signal A is -1 or 0, the output logic level is -1. The input signal A is processed into the AP signal by the positive polarity ternary inverter PTI. The AP signal controls the on / off state of the P-type and N-type transistors in the circuit. When the input signal A is +1, the AP signal controls the P-type transistor to conduct, and the circuit outputs a logic level of 0; when the input signal A is -1 or 0, the AP signal controls the N-type transistor to conduct, and the circuit outputs a logic level of -1.

4. A unary balanced ternary arithmetic circuit suitable for balanced ternary systems according to claim 1, characterized in that, The A + The circuit's pull-up and pull-down levels are VDD and VDD / 2, corresponding to balanced ternary logic levels +1 and 0, respectively. Its input-output logic relationship is as follows: when input signal A is +1, the output logic level is +1; when input signal A is -1 or 0, the output logic level is 0. Input signal A is processed into the AP signal by a positive polarity ternary inverter PTI. The AP signal controls the on / off state of the P-type and N-type transistors in the circuit. When input signal A is +1, the AP signal controls the P-type transistor to conduct, and the circuit outputs a logic level of +1; when input signal A is -1 or 0, the AP signal controls the N-type transistor to conduct, and the circuit outputs a logic level of 0. + The circuit's pull-up and pull-down levels are VDD / 2 and Gnd, corresponding to balanced ternary logic levels 0 and -1, respectively. Its input-output logic relationship is as follows: when input signal A is -1, the output logic level is 0; when input signal A is 0 or +1, the output logic level is +1. Input signal A is processed into the AN signal by the negative polarity ternary inverter NTI. The AN signal controls the on / off state of the P-type and N-type transistors within the circuit. When input signal A is -1, the AN signal controls the N-type transistor to conduct, and the circuit outputs a logic level of 0; when input signal A is 0 or +1, the AN signal controls the P-type transistor to conduct, and the circuit outputs a logic level of +1.

5. A unary balanced ternary arithmetic circuit suitable for balanced ternary systems according to claim 1, characterized in that, The pull-up and pull-down levels of the Az circuit are VDD and Gnd, corresponding to balanced ternary logic levels +1 and -1, respectively. Its input-output logic relationship is as follows: when the input signal A is -1, the output logic level is -1; when the input signal A is 0 or +1, the output logic level is +1. The input signal A is processed into the AN signal by the negative polarity ternary inverter NTI. The AN signal serves as the on / off control signal for the P-type and N-type transistors within the circuit. When the input signal A is -1, the AN signal outputs a logic level of -1, the N-type transistor is turned on, and the output signal is pulled low to logic level -1. When the input signal A is 0 or +1, the AN signal outputs a logic level of +1, the P-type transistor is turned on, and the output signal is pulled up to logic level +1.

6. A ternary half-adder circuit suitable for balanced ternary systems, characterized in that, The circuit employs the unary balanced ternary arithmetic circuit described in any one of claims 1-5, combined with three transmission gates TG0, TG1, and TG2. The half-adder has two balanced ternary logic input ports, with input signals A and B, and two output ports, outputting a sum signal Sum and a carry signal Carry, respectively. Input signal A is processed by the unary balanced ternary arithmetic circuit corresponding to claims 1-5 to generate control signals AN, AM, and AP. These three control signals independently regulate the on / off states of transmission gates TG0, TG1, and TG2. B2, B, and B1 are used as input signals to transmission gates TG0, TG1, and TG2, respectively. The logical mapping relationship between B2 and input signal B is as follows: when B is -1, 0, or +1, B2 corresponds to +1, -1, or +1; the logical mapping relationship between B1 and input signal B is as follows: when B is -1, 0, or +1, B1 corresponds to 0, +1, or -1. The logical mapping between input signals A and B and the sum signal Sum and carry signal Carry is achieved through the switching of the transmission gates.

7. A ternary half-adder circuit suitable for balanced ternary systems according to claim 6, characterized in that, The on / off switching of the transmission gate and carry branch is realized based on different values ​​of the input signal A: When the input signal A is -1, the AN signal processed by the negative polarity ternary inverter NTI is +1, which controls the transmission gate TG0 to turn on and the transmission gates TG1 and TG2 to turn off. The sum signal Sum output is equal to B2. At the same time, the carry branch CN1 is turned on and the carry signal Carry output is equal to B⁻. When the input signal A is 0, the AM signal processed by the AM circuit is -1, which controls the transmission gate TG1 to turn on and the transmission gates TG0 and TG2 to turn off. The sum signal Sum output is equal to B. At the same time, the carry branch CP0 is turned on and the carry signal Carry output is a balanced ternary logic level 0. When the input signal A is +1, the AP signal processed by the positive polarity ternary inverter PTI is -1, which controls the transmission gate TG2 to turn on and the transmission gates TG0 and TG1 to turn off. The sum signal Sum output is equal to B1. At the same time, the carry branch CP1 is turned on and the carry signal Carry output is equal to B⁺.

8. A ternary full adder circuit suitable for balanced ternary systems, characterized in that, The ternary half-adder circuit described in any one of claims 6-7 is used as the core arithmetic unit. The full adder is provided with three balanced ternary logic input ports, with input signals A, B, and C, and two output ports, which respectively output the sum signal Sum. ABC With carry signal Carry ABC It includes at least a first topology full adder, which is composed of two cascaded ternary half adders and a balanced ternary ANY logic gate. The first ternary half adder is connected to input signals A and B and outputs an intermediate sum signal SUM. AB The first carry signal CARRY1 is connected to the second ternary half-adder, which is connected to the input signal C and the intermediate sum signal SUM. AB The final output signal is Sum. ABC The balanced ternary ANY logic gate has two input ports and one output port. The two input ports are respectively connected to the first carry signal CARRY1 and the second carry signal CARRY2, and the output port outputs the final carry signal Carry of the full adder. ABC .

9. A ternary full adder circuit suitable for balanced ternary systems according to claim 8, characterized in that, It also includes a second topology carry-optimized full adder, which comprises a univariate balanced ternary arithmetic circuit as described in any one of claims 1-5 and a ternary half-adder as described in any one of claims 6-7; the summing circuit of the two-stage ternary half-adder sequentially processes the input signals A, B and the intermediate sum signal to achieve the final sum signal Sum. ABC The precise calculation involves extracting the output signal of the first-stage half-adder summing circuit and the control signal after the input signal C has been processed by the unary balanced ternary arithmetic circuit described in any one of claims 1-5. A dedicated carry circuit is designed based on the level transmission characteristics of the transistor. This dedicated carry circuit directly outputs the final carry signal Carry of the full adder. ABC The dedicated carry circuit eliminates the traditional multi-stage cascaded structure, directly generating the carry through the operation signal of the first-stage half-adder output and the input signal C, thus shortening the critical carry path.

10. A ternary multiplier circuit suitable for balanced ternary systems, characterized in that, Based on the circuit described in any one of claims 1-9 as the basic hardware unit, it is constructed by connecting a standard ternary inverter (STI) and a transmission gate; the multiplier is provided with two balanced ternary logic input ports, with input signals A and B, and also has a product output port; with B... STI The three signals, VDD / 2 and B, serve as the transmission control signals for the transmission gate. BSTI is the signal obtained by processing input signal B through a standard ternary inverter STI, and VDD / 2 corresponds to a balanced ternary logic level of 0. Different values ​​of input signal A control the selection of different branches by the transmission gate, thus achieving balanced ternary multiplication: when input signal A is -1, the transmission gate selects B. STI The multiplier outputs the value of B after processing by a standard ternary inverter (STI). When the input signal A is 0, the transmission gate selects the VDD / 2 branch, and the multiplier directly outputs a balanced ternary logic level of 0. When the input signal A is +1, the transmission gate selects the B branch, and the multiplier directly outputs the original value of the input signal B.

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