Hybrid high-precision power supply control method fusing dynamic error cancellation technique

Abstract

This invention discloses a hybrid high-precision power source control method and device integrating dynamic error cancellation technology, relating to the field of power metering and testing technology. The method first constructs an asymmetric heterogeneous hybrid power stage topology composed of a high-power IGBT inverter main stage and a high-frequency broadband linear auxiliary stage connected in parallel. Then, it utilizes an FPGA high-speed acquisition link to separate the comprehensive error signal, including dead-zone distortion and switching noise, in real time, and introduces an iterative learning control algorithm to establish a dead-zone inverse model reflecting the device characteristics. Subsequently, based on model prediction, a leading inverse cancellation command is generated to drive the linear auxiliary stage to inject a precision compensation current, performing nanosecond-level dynamic shaping and ripple cancellation on the main stage output. Simultaneously, by monitoring the load current amplitude, full-range adaptive operating condition switching is performed, locking the main stage under weak current conditions to avoid nonlinear interference. This invention, through master-slave collaborative control and dynamic error cancellation, effectively overcomes the bottleneck of traditional power sources' difficulty in simultaneously achieving high energy efficiency and high signal-to-noise ratio, completely eliminating zero-crossing distortion, ensuring output stability and high waveform fidelity across the entire range from microamps to hundreds of amps, and providing ideal standard signal support for power metering traceability.

Description

Technical Field

[0001] This invention relates to the field of power metering and testing technology, specifically to a hybrid high-precision power source that integrates dynamic error cancellation technology. Background Technology

[0002] With the strategic advancement of building a new power system and a ubiquitous power Internet of Things, electricity metering, as the cornerstone of power grid value transmission and trade settlement, directly determines the fairness of energy trading and the reliability of system operation. This places extremely high technical requirements on the standard power source, which is the core verification equipment.

[0003] In the existing technological system, the design of high-precision power sources has long faced the dilemma of balancing high energy efficiency and high signal purity. While traditional linear power amplification technology boasts excellent dynamic response and extremely low harmonic distortion, its high heat loss and low power density make it unsuitable for high-power output scenarios. Although IGBT-based switching-mode power sources significantly improve energy conversion efficiency, they are limited by the inherent switching dead-time characteristics and on-state voltage drop nonlinearity of power devices, easily generating significant crossover distortion at the zero-crossing point of the output waveform, accompanied by high-frequency switching ripple that is difficult to filter out. This results in a serious stability bottleneck in low-current output and high-precision metering applications.

[0004] Furthermore, existing single-loop feedback control strategies are often limited by finite control bandwidth, resulting in response lag and an inability to effectively suppress nonlinear transient distortions and high-frequency disturbances caused by switching devices. Conventional fixed dead-time compensation techniques are ill-suited to adapting to the nonlinear variations of high-power devices over a wide dynamic range, making it difficult to meet the requirements for high-precision traceability across the entire range when dealing with weak current outputs.

[0005] Therefore, there is an urgent need for a high-precision power source control method that can balance high energy efficiency and high signal-to-noise ratio, and effectively suppress dead zone effect and zero-crossing distortion. Summary of the Invention

[0006] To address the challenges of existing power sources that struggle to achieve both high energy efficiency and high signal-to-noise ratio, as well as waveform zero-crossing distortion and unstable small-signal output due to the dead-time effect of switching devices, this invention proposes a hybrid high-precision power source control method and device incorporating dynamic error cancellation technology. This invention constructs an asymmetric heterogeneous hybrid topology where an "IGBT switching master stage" and a "wideband linear auxiliary stage" work collaboratively. The extremely high frequency response characteristics of the linear auxiliary stage are used to shape the master stage output in real time. Based on the repetitive characteristics of periodic signals, an error inverse model prediction algorithm is established to accurately identify and quantify voltage collapse and high-frequency ripple caused by the IGBT dead time. An inverse compensation current is generated in the time domain and dynamically injected to actively cancel crossover distortion and switching noise. Simultaneously, a master-slave power allocation and smooth switching strategy is implemented for different load conditions. Under low current conditions, the linear stage dominates to avoid nonlinear regions, while under high current conditions, hybrid drive ensures efficiency. This constructs a metering-grade power platform that combines ultra-high precision and low heat loss, providing high-purity standard signal support for electricity meter verification and value transmission.

[0007] To meet the above requirements, the present invention proposes the following technical solution: A hybrid high-precision power source control method incorporating dynamic error cancellation technology, the method comprising the following steps: 1) Construct an asymmetric heterogeneous hybrid power stage topology: Construct a hybrid hardware architecture consisting of a high-power IGBT inverter main stage and a high-frequency broadband linear auxiliary stage connected in parallel. The IGBT inverter main stage serves as the core of fundamental wave energy output, and the linear auxiliary stage serves as a high dynamic response unit connected to the main circuit through a decoupling inductor. 2) Real-time acquisition and separation of high-precision error signals: Real-time monitoring of the actual output waveform of the hybrid topology, synchronous differential comparison with the standard reference signal, and using digital signal processing technology to separate the comprehensive error signal containing dead-zone distortion, switching noise and harmonics from the output signal, and establish a dynamic error feature library; 3) Establish a dead-zone inverse model based on periodic memory: Utilize the periodic characteristics of the signal, introduce an iterative learning control algorithm, construct a time-domain inverse model reflecting the dead-zone effect and on-state voltage drop characteristics of IGBT based on the error data of the previous cycle, and perform time-domain lead operation to generate an inverse cancellation instruction. 4) Implement dynamic error anti-phase cancellation and master-slave collaborative control: According to the anti-phase cancellation command, drive the linear auxiliary stage to inject compensation current at the IGBT switching dead time and ripple fluctuation, and use the output of the linear auxiliary stage to perform physical-level anti-phase cancellation and waveform shaping on the output of the IGBT inverter master stage. 5) Perform full-range adaptive operating condition switching: monitor the output current amplitude in real time, determine the current operating condition according to the preset nonlinear threshold, switch to linear level dominant mode under weak current conditions, and restore hybrid cooperative mode under high current conditions to maintain full-range output stability.

[0008] Further, in step 1), the construction of the asymmetric heterogeneous hybrid power stage topology specifically includes: selecting a trench gate field cutoff type IGBT module to construct a single-phase full-bridge inverter topology as the IGBT inverter main stage, cascading an LC passive filter to bear a predetermined proportion or more of the fundamental wave energy component in the load current; A high-slew rate wideband linear power amplifier is selected as the linear auxiliary stage and connected to the output node of the main circuit via a microhenry-level high-frequency decoupling inductor. Total system output current i total Following the superposition principle, the dynamic equations are satisfied: ; in, G LPF ( s The transfer function of the master stage filter. i inv (t) is the main stage output current. i lin ( t The compensation current injected into the auxiliary stage is configured to be much larger than the switching frequency of the IGBT inverter main stage.

[0009] Furthermore, in step 2), the real-time acquisition and separation of high-precision error signals specifically includes: constructing a high-speed parallel data acquisition link based on FPGA, and using an analog-to-digital converter to discretize analog quantities into digital sequences. y meas ( k ); Generating an ideal reference sine wave sequence using the all-digital phase-locked loop inside the FPGA y ref (k), calculate the original instantaneous error ; Design a deep-wave infinite impulse response digital filter with a transfer function. H ( z )for: ; in r It is the extreme contraction factor. The fundamental angular frequency is used; the filter is used to suppress the fundamental component and extract the pure error signal. e pure ( k ); By combining spectrum analysis algorithms, the error is decomposed into deterministic periodic error and random high-frequency noise, and a dynamic error feature database is established using the phase angle as an index.

[0010] Further, in step 3), establishing the dead-zone inverse model based on periodic memory specifically includes: for the periodic energy verification signal, establishing a P-type iterative control law in the discrete-time domain, whose state update equation is: ; in j For the number of iterations, u For auxiliary control signals, e j For the first j Periodic storage error K P For learning gain, λ The number of phase lead steps designed for system group delay; A phase-error mapping table is built inside the FPGA to map the phase before the distortion phase point is reached in the current cycle. N In microseconds, the required compensation current amplitude of the linear auxiliary stage at the next moment is calculated, and an inverted cancellation instruction with a leading phase is generated to compensate for the physical response lag of the hardware circuit.

[0011] Furthermore, in step 4), the implementation of dynamic error inverse cancellation and master-slave collaborative control specifically includes: adopting a master-slave collaborative mechanism that combines feedforward dominance and feedback correction; the IGBT inverter master stage is controlled by closed loop to output a fundamental current containing switching ripple, and the linear auxiliary stage operates in a high-frequency controlled current source mode. Output compensation current of linear auxiliary stage i lin ( t Following the dynamic error cancellation equation: ; in For the feedforward component predicted by the dead-zone inverse model, i ripple For residual high-frequency noise in real-time sampling feedback, To compensate for system latency; In the zero-crossing region of the waveform, the slew rate of the linear auxiliary stage is used to inject pulse current to fill the energy gap; at the peaks and troughs, the linear auxiliary stage is used to reverse absorb the high-frequency ripple generated by the switching frequency.

[0012] Furthermore, in step 5), the execution of full-range adaptive operating condition switching specifically includes: calculating the effective value of the load current in real time using a sliding window algorithm. I rmsIntroduce decision logic with hysteresis characteristics and define a switching function. S mode : ; in and These are the set lower and upper limits of the threshold, respectively; When in Linear_Mode, the gate drive of the IGBT inverter master stage is locked, and the linear auxiliary stage handles all outputs; when in Hybrid_Mode, master-slave cooperative control is restored. Gain scheduling technology is used during mode switching to dynamically adjust controller parameters according to the current mode and achieve a smooth transition through interpolation.

[0013] Compared with existing technologies, the technical advantages of this invention are as follows: By constructing a heterogeneous hybrid topology with "master-slave collaboration," the performance bottleneck of traditional single switching sources in high-precision applications is broken. Utilizing the anti-phase error injection of a linear auxiliary stage and a dead-zone prediction algorithm based on iterative learning, nanosecond-level dynamic cancellation of IGBT switching ripple and crossover distortion is achieved, significantly enhancing the spectral purity and time-domain tracking of the output waveform. Combined with an adaptive smooth switching strategy for small-signal conditions, nonlinear interference from high-power devices is effectively avoided, ensuring extremely high output stability and consistency across the entire measurement range from microamperes to hundreds of amperes. This technical solution, while maintaining high system energy efficiency, completely solves the stringent requirements of "zero distortion" and "ultra-high precision" in power metering verification, providing strong technical support for the traceability of measurement values ​​in new power systems, and possessing significant engineering practical value and promising prospects for widespread application. Attached Figure Description

[0014] To more clearly present the relevant technical solutions of the present invention, the accompanying drawings used in the description of the implementation methods are briefly introduced below. These drawings represent only part of the content of the present invention, and not all of it.

[0015] in: Figure 1 This is a schematic diagram of the asymmetric heterogeneous hybrid power stage topology in an embodiment of the present invention; Figure 2 This is a schematic diagram of the real-time acquisition and separation extraction process of high-precision error signals in an embodiment of the present invention; Figure 3 This is a schematic diagram illustrating the implementation process of the dynamic error anti-cancellation and master-slave collaborative control strategy in an embodiment of the present invention; Detailed Implementation

[0016] The following description, in conjunction with the accompanying drawings and specific embodiments, provides further details. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of the invention.

[0017] This embodiment selects the standardized laboratory of the power metering verification center of a provincial power research institute as the engineering application scenario. In this scenario, to meet the traceability requirements of a large number of high-precision smart energy meters, especially the full-range high-precision testing requirements for weak current points (such as 1mA to 50mA) and large current points (such as 100A), the hybrid high-precision power source integrating dynamic error cancellation technology proposed in this invention is used for construction and verification.

[0018] In this embodiment, a heterogeneous hybrid standard power source device with a rated output voltage of 57.7V / 220V and a maximum output current of 100A was constructed. The design goal of this device is to solve the zero-crossing distortion and high-frequency switching ripple problems of traditional switching sources while maintaining high energy efficiency, and to overcome the nonlinearity defects of high-power devices in the small-signal domain.

[0019] Step 1: Construction of Asymmetric Heterogeneous Hybrid Power Stage Topology To resolve the inherent conflict between high energy efficiency and high signal purity, this embodiment first establishes a master-slave heterogeneous power hardware platform based on a current parallel superposition mechanism. This platform employs an asymmetric design approach, consisting of a high-power IGBT full-bridge inverter master stage and a high-frequency broadband linear auxiliary stage connected in parallel.

[0020] Specifically, the main power stage, as the energy core of the system, uses trench gate field-stop IGBT modules with a rated voltage of 1200V and a current rating of 200A to construct a single-phase full-bridge inverter topology. Considering the low on-state voltage drop of IGBTs under high current and controllable switching losses, the main stage is configured to handle more than 95% of the fundamental energy component of the load current, thereby significantly reducing the overall heat loss of the device under high power output. A passive LC low-pass filter with a cutoff frequency of 1.5kHz is cascaded at the rear of the main stage inverter. The filter inductor L is 1.2mH, using an amorphous alloy core to reduce hysteresis losses; the filter capacitor C is 30μF, using a high-frequency, low-resistance metallized polypropylene film capacitor. The switching frequency of the main stage... f sw Setting it to 20kHz, this frequency choice achieves an engineering balance between ensuring waveform quality and limiting switching losses.

[0021] The auxiliary power stage, connected in parallel with the main stage, is positioned as a "waveform trimming unit" and employs a wideband linear power amplifier with a high slew rate. This linear stage does not prioritize output power but focuses on high dynamic response; its bandwidth is configured as follows: This is much greater than the switching frequency of the main stage and the cutoff frequency of the LC filter. The linear stage is connected via a high-frequency decoupling inductor of a microhenry stage (10μH in this example). L d Connect to the output node of the main circuit. The function of this decoupling inductor is to isolate the high-frequency switching voltage ripple of the main stage from directly entering the linear stage, while ensuring that the high-frequency compensation current injected into the linear stage can flow smoothly into the load.

[0022] Total system output current i total ( t Following Kirchhoff's Current Law (KCL) and the superposition principle, its dynamic equation can be expressed as: ; In the formula, G LPF ( s The transfer function of the master-stage LC filter is . i inv ( t () represents the SPWM modulated current output by the IGBT inverter bridge arm. i lin ( t This is a precision compensation current injected into the linear auxiliary stage. Through this topology, the auxiliary stage possesses the physical capability to track and correct the main stage's output ripple and dead-zone distortion at the nanosecond level, thereby achieving the decoupled coexistence of high-efficiency energy conversion and high-dynamic waveform reconstruction at the hardware level.

[0023] Step 2: Real-time acquisition and separation of high-precision error signals Accurate error detection is a prerequisite for dynamic cancellation. This embodiment constructs a high-speed parallel data acquisition link based on a field-programmable gate array (FPGA).

[0024] At the hardware detection front end, a 0.01-class high-stability closed-loop Hall current transformer and a precision resistor voltage divider network are selected, along with a low-temperature drift operational amplifier to complete signal isolation and conditioning. The analog signal is then digitized by a 16-bit high-resolution successive approximation analog-to-digital converter (ADC). The system sampling rate is set to 500. kSPS That is, the sampling period T s = 2μs, capable of capturing ripple details at the main stage's 20kHz switching frequency. The discretized digital sequence acquired by the ADC is denoted as... y meas ( k ).

[0025] Inside the FPGA controller, a fully digital phase-locked loop (DPLL) maintains microsecond-level synchronization with a high-stability crystal oscillator, generating an ideal standard reference sine wave sequence with adjustable amplitude, frequency, and phase in real time. y ref ( k FPGA calculates raw instantaneous error in real time. e raw ( k ) = y ref ( k ) - y meas ( k Since the original error includes minute deviations in the fundamental amplitude and phase, low-order harmonics, dead-zone steps, and high-frequency switching noise, a deep-notch infinite-impulse response digital filter with a center frequency of 50Hz was designed to accurately separate the nonlinear distortion characteristics caused by the IGBT dead zone. Its transfer function... H ( z The design is as follows: ; In the formula, This is the digital angular frequency corresponding to the fundamental angular frequency. r This is the extreme contraction factor. In this embodiment... r The value is set to 0.995 to ensure an extremely narrow stopband bandwidth (-3dB bandwidth less than 1Hz), thereby filtering out the fundamental frequency component to the maximum extent without attenuating the high-frequency components in the dead zone.

[0026] After this notch filtering process, the residual fundamental frequency leakage is effectively suppressed, and the remaining signal is the clean composite error signal containing dead zone steps, higher harmonics (mainly the 3rd, 5th, and 7th harmonics), and switching ripple. e pure ( k The system further incorporates a sliding window Fast Fourier Transform (FFT) spectral analysis algorithm to decompose the error into deterministic periodic error and random high-frequency noise based on frequency domain characteristics. The FPGA maps the deterministic error components to its internal dual-port RAM, establishing a phase angle... This is a dynamic error feature database indexed by load conditions. This database is updated in real time according to the load conditions, providing an accurate data source for subsequent iterative compensation.

[0027] Step 3: Establish a dead-zone inverse model prediction algorithm based on periodic memory. The electrical energy verification signal has a strict periodicity ( T Given the characteristic of 20ms, this embodiment introduces an iterative learning control (ILC) strategy based on memory evolution, aiming to eliminate the nonlinear distortion caused by the inherent dead-time voltage drop and switching delay of the IGBT.

[0028] The system first constructs a physical model of the dead-time voltage regarding the direction of the output current. ,in T d This refers to the dead time. Since conventional PID feedback control cannot completely eliminate this non-smooth, nonlinear disturbance due to bandwidth limitations, this embodiment establishes a P-type iterative control law in the discrete-time domain. Its state update equation is expressed as: ; In the formula, j For the number of iterations, u For auxiliary control signals, e j For the first j Periodic storage error K P This represents the proportional learning gain. λ The phase lead step is designed to compensate for the physical delay between the detection link and the power amplifier, which is used to address system group delay.

[0029] In practice, the algorithm utilizes a dynamic phase-error mapping table in the FPGA's internal RAM to read the error trajectory from the previous cycle and construct an inverse dead-zone model. This inverse model can accurately identify voltage collapse characteristics (i.e., dead-zone steps) near the zero-crossing point of the waveform. This model is applied before the current sine cycle reaches this distortion phase point. N microseconds (as set in this example) N =10μs, the algorithm performs time-domain lead calculations to determine the required compensation current amplitude and waveform of the linear stage at the next moment, generating an inverted cancellation command with a leading phase. This "learning from history" prediction mechanism enables the system to prepare for compensation before the distortion actually occurs, thereby overcoming the physical response lag of the hardware circuit and theoretically achieving "zero-delay" precise cancellation of dead-time disturbances.

[0030] Step 4: Implementation of dynamic error inversion cancellation and master-slave collaborative control strategy This step transforms the digital domain algorithm into a physical domain waveform reconstruction. In this embodiment, the digital domain lead cancellation instruction generated by the FPGA is converted into an analog control voltage via an isolated 16-bit high-speed digital-to-analog converter (DAC) to drive a wideband linear auxiliary stage to perform microsecond-level power combining operations.

[0031] The system control strategy follows a master-slave collaborative mechanism of "feedforward dominance + feedback correction": 1) Main stage control: The IGBT main stage is controlled by a low-bandwidth (<1kHz) voltage and current dual closed-loop control, responsible for outputting a high-power fundamental current containing switching ripple. i invBecause of the low loop bandwidth, the main stage is not sensitive to high-frequency disturbances and primarily ensures the efficiency of energy transfer.

[0032] 2) Auxiliary stage control: The linear auxiliary stage operates in high-frequency controlled current source mode, and its output current... i lin It is directly controlled by the cancellation command. This compensation action strictly follows the dynamic error cancellation equation: ; In the formula, For the dead zone feedforward component predicted by the ILC model, i ripple For residual high-frequency noise in real-time sampling feedback, To compensate for system latency.

[0033] In the zero-crossing region of the waveform, to address the voltage "step" effect caused by the IGBT dead zone (typically lasting several microseconds to tens of microseconds), the linear stage utilizes its extremely high slew rate to instantaneously inject a pulse current in the opposite direction to the collapse, filling the energy loss caused by the turn-off of the main stage power transistor and preventing discontinuities or distortions in the current waveform. At the peaks and troughs, the linear stage outputs an inverted high-frequency current to absorb the IGBT switching frequency. f sw And the high-frequency ripple generated by its frequency multiplication. This "macro-micro combined" cancellation mechanism acts like "electronic putty" to perform sub-micron level real-time trimming of the coarse waveform of the main stage output.

[0034] Experimental test data shows that after implementing this strategy, the total harmonic distortion (THD) of the output waveform under 50A output conditions is significantly reduced from 1.8% (typical value) when the main stage is operating alone to below 0.05%. Particularly noteworthy is the attenuation rate of over 40dB for switching noise at 20kHz. This indicates that the system has successfully synthesized a standard sine wave output with mathematically high purity on a nonlinear physical device architecture.

[0035] Step 5: Full-range adaptive operating condition switching and output stability optimization To address the issues of severe transconductance nonlinearity and excessive switching noise in high-power IGBT devices under low current (e.g., below 1A), this embodiment designs a full-range adaptive switching control strategy based on a state machine to ensure performance across the entire range from milliampere to hundred ampere.

[0036] The system first calculates the effective value of the load current in real time using a sliding window algorithm (with a window length of one fundamental cycle). I rms To prevent repeated oscillations at the switching critical point, a decision logic with hysteresis characteristics is introduced, and a switching function is defined. S mode as follows: ; In this embodiment, the lower threshold Set to 0.5A, upper limit of threshold The current is set to 0.8A. When the detected current is less than 0.5A, the FPGA determines that it has entered the small-signal operating condition, i.e., the linear-dominant mode (Linear_Mode). At this time, the system sends a command to lock the gate drive signal of the IGBT master stage (Duty Cycle = 0 or turn-off enable), causing the IGBT to completely stop working. The system is equivalent to a pure Class A linear power amplifier, with the output task entirely undertaken by the linear auxiliary stage. This mode completely avoids PWM switching noise and dead-time nonlinearity, ensuring the extreme purity of weak signals. When the current exceeds 0.8A, the system reverts to master-slave cooperative control, i.e., the hybrid cooperative mode (Hybrid_Mode), where the IGBT takes over the main power, and the linear stage reverts to a compensation role.

[0037] To ensure system stability during the switching process and prevent sudden output changes, this embodiment employs gain scheduling technology. The system pre-sets two sets of PI controller parameters: 1) Small-signal linear mode: using high gain ( K P =12.5), strong damping ( The configuration prioritizes extremely high steady-state accuracy and zero switching noise, while suppressing step response overshoot.

[0038] 2) Large signal mixing mode: using moderate gain ( K P =4.8), standard damping ( The configuration optimizes dynamic response and maintains system phase margin while ensuring energy efficiency.

[0039] At the moment of mode switching, the system utilizes the transition weighting factor. Perform linear interpolation on the control parameters: This achieves a smooth transition of the control law. Through this strategy, the device achieves phase margin across the entire dynamic range. Its absolute stability has successfully solved the industry problem of large distortion of high-power sources under small signals.

[0040] In summary, this invention achieves a comprehensive breakthrough in high-precision power source performance through five core steps: constructing an asymmetric heterogeneous topology, high-precision error extraction, periodic dead-zone prediction, dynamic phase deregulation, and adaptive operating condition switching. In actual operation, this device not only maintains the high efficiency characteristics of a switching source but also achieves the level of a linear source in terms of waveform purity, dynamic response, and small-signal stability, fully meeting the stringent requirements of the next-generation smart grid for traceability of power metering values.

Claims

1. A hybrid high-precision power source control method integrating dynamic error cancellation technology, characterized in that, Includes the following steps: 1) Construct an asymmetric heterogeneous hybrid power stage topology: Construct a hybrid hardware architecture consisting of a high-power IGBT inverter main stage and a high-frequency broadband linear auxiliary stage connected in parallel. The IGBT inverter main stage serves as the core of fundamental wave energy output, and the linear auxiliary stage serves as a high dynamic response unit connected to the main circuit through a decoupling inductor. 2) Real-time acquisition and separation of high-precision error signals: Real-time monitoring of the actual output waveform of the hybrid topology, synchronous differential comparison with the standard reference signal, and using digital signal processing technology to separate the comprehensive error signal containing dead-zone distortion, switching noise and harmonics from the output signal, and establish a dynamic error feature library; 3) Establish a dead-zone inverse model based on periodic memory: Utilize the periodic characteristics of the signal, introduce an iterative learning control algorithm, construct a time-domain inverse model reflecting the dead-zone effect and on-state voltage drop characteristics of IGBT based on the error data of the previous cycle, and perform time-domain lead operation to generate an inverse cancellation instruction. 4) Implement dynamic error anti-phase cancellation and master-slave collaborative control: According to the anti-phase cancellation command, drive the linear auxiliary stage to inject compensation current at the IGBT switching dead time and ripple fluctuation, and use the output of the linear auxiliary stage to perform physical-level anti-phase cancellation and waveform shaping on the output of the IGBT inverter master stage. 5) Perform full-range adaptive operating condition switching: monitor the output current amplitude in real time, determine the current operating condition according to the preset nonlinear threshold, switch to linear level dominant mode under weak current conditions, and restore hybrid cooperative mode under high current conditions to maintain full-range output stability.

2. The hybrid high-precision power source control method integrating dynamic error cancellation technology according to claim 1, characterized in that, Step 1) specifically includes: A trench gate field cutoff type IGBT module is selected to construct a single-phase full-bridge inverter topology as the main stage of the IGBT inverter, and a cascaded LC passive filter is used to bear the fundamental energy component of the load current with a preset proportion or more. A high-slew rate wideband linear power amplifier is selected as the linear auxiliary stage and connected to the output node of the main circuit via a microhenry-level high-frequency decoupling inductor. Total system output current i total Following the superposition principle, the dynamic equations are satisfied: ； in, G LPF ( s The transfer function of the master stage filter. i inv ( t Main stage output current, i lin ( t The compensation current injected into the auxiliary stage is configured to be much larger than the switching frequency of the IGBT inverter main stage.

3. The hybrid high-precision power source control method integrating dynamic error cancellation technology according to claim 1, characterized in that, Step 2) specifically includes: Construct a high-speed parallel data acquisition link based on FPGA, and use an analog-to-digital converter to discretize analog quantities into digital sequences. y meas ( k ); Generating an ideal reference sine wave sequence using the all-digital phase-locked loop inside the FPGA y ref ( k ), calculate the original instantaneous error ; Design a deep-wave infinite impulse response digital filter with a transfer function. H ( z )for: ； in r It is the extreme contraction factor. The fundamental angular frequency is used; the filter is used to suppress the fundamental component and extract the pure error signal. e pure ( k ); By combining spectrum analysis algorithms, the error is decomposed into deterministic periodic error and random high-frequency noise, and a dynamic error feature database is established using the phase angle as an index.

4. The hybrid high-precision power source control method integrating dynamic error cancellation technology according to claim 1, characterized in that, Step 3) specifically includes: For periodic energy verification signals, a P-type iterative control law in the discrete-time domain is established, and its state update equation is: ； in j For the number of iterations, u For auxiliary control signals, e j For the first j Periodic storage error K P For learning gain, λ The number of phase lead steps designed for system group delay; A phase-error mapping table is built inside the FPGA to map the phase before the distortion phase point is reached in the current cycle. N In microseconds, the required compensation current amplitude of the linear auxiliary stage at the next moment is calculated, and an inverted cancellation instruction with a leading phase is generated to compensate for the physical response lag of the hardware circuit.

5. The hybrid high-precision power source control method integrating dynamic error cancellation technology according to claim 1, characterized in that, Step 4) specifically includes: A master-slave collaborative mechanism combining feedforward dominance and feedback correction is adopted; the IGBT inverter master stage is controlled by a closed loop to output a fundamental current containing switching ripple, and the linear auxiliary stage operates in a high-frequency controlled current source mode. Output compensation current of linear auxiliary stage i lin ( t Following the dynamic error cancellation equation: ； in For the feedforward component predicted by the dead-zone inverse model, i ripple For residual high-frequency noise in real-time sampling feedback, To compensate for system latency; In the zero-crossing region of the waveform, the slew rate of the linear auxiliary stage is used to inject pulse current to fill the energy gap; at the peaks and troughs, the linear auxiliary stage is used to reverse absorb the high-frequency ripple generated by the switching frequency.

6. The hybrid high-precision power source control method integrating dynamic error cancellation technology according to claim 1, characterized in that, Step 5) specifically includes: The effective value of the load current is calculated in real time using a sliding window algorithm. I rms Introduce decision logic with hysteresis characteristics and define a switching function. S mode : ； in and These are the set lower and upper limits of the threshold, respectively; When in Linear_Mode, the gate drive of the IGBT inverter master stage is locked, and the linear auxiliary stage handles all outputs; when in Hybrid_Mode, master-slave cooperative control is restored. Gain scheduling technology is used during mode switching to dynamically adjust controller parameters according to the current mode and achieve a smooth transition through interpolation.

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