A SiC MOSFET device with improved diode reverse recovery characteristics and a method of manufacturing the same

Abstract

The application discloses a SiC MOSFET device with improved diode reverse recovery characteristics and a preparation method thereof, and relates to the technical field of semiconductors.The device comprises, from bottom to top, a drain metal layer, an N-type substrate, a first N-type drift layer, a second N-type drift layer, a P-body region, a P+ contact region, an ohmic contact alloy layer and a source metal layer; a P++ layer extending downward is arranged in the middle of the top surface of the second N-type drift layer; a groove region extending into the P++ layer (4) is arranged on the top surface of the P+ contact region; a gate oxide layer is arranged in the groove region; a filled polysilicon gate is arranged in the gate oxide layer; N+ regions extending downward from the top surface of the P+ contact region into the P-body region are arranged on both sides of the groove region; an isolation medium layer is deposited on the P+ contact region, and the isolation medium layer completely covers the top end surfaces of the polysilicon gate and the gate oxide layer.The application can reduce the deep diffusion of carriers, make the recombination of the carriers better distributed in the surface region of the PN junction, and guarantee the long-term reliability of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a SiCMOSFET device and its fabrication method for improving the reverse recovery characteristics of diodes. Background Technology

[0002] SiC MOSFETs are wide-bandgap silicon carbide-based power switching devices that integrate a PN-type body diode. They can function as freewheeling devices in circuits and are widely used in high-frequency, high-voltage power conversion applications such as photovoltaics, energy storage, and automotive electric drives. The device's performance directly determines the converter's switching losses and overall efficiency. Ideally, the device's built-in body diode should possess characteristics of low reverse recovery charge and short reverse recovery time to adapt to high-frequency operating conditions.

[0003] The existing trench-gate SiC MOSFET basic structure, from bottom to top, includes an N-type substrate, a single-layer N-type drift layer, and a surface P-body region. A trench is formed within the P-body region, with gate oxide grown on the inner wall and filled with polysilicon to form the gate. N+ source regions and P+ contact regions are arranged on both sides of the trench. A dielectric isolation layer, ohmic alloy, and source metal are deposited on the surface layer, and drain metal is fabricated on the back of the substrate. This traditional structure relies solely on the P-body region and the N-type drift layer to form the body diode PN junction. There are no additional doped recombination structures within the drift layer, and the bottom of the trench directly contacts the single-layer N-type drift layer. When the device's body diode is forward-biased, a large number of holes and minority carriers are injected and stored within the N-type drift layer. When the device is turned off and the body diode is subjected to reverse voltage, the minority carriers accumulated in the drift layer cannot recombine and be extracted quickly, resulting in a large reverse recovery current, reverse recovery charge, and a long reverse recovery time. This leads to extremely high reverse recovery switching losses and severe electromagnetic interference, significantly limiting the device's high-frequency application limits.

[0004] To improve the reverse recovery characteristics of body diodes, the industry currently mainly uses the following solutions: First, an independent SiC Schottky diode is connected in parallel outside the power circuit. The Schottky diode's characteristic of having no minority carrier storage is used to share the freewheeling current, avoiding the reverse recovery behavior of the body diode. However, this adds extra components, package leads, and pads, introducing parasitic inductance into the circuit. This can easily generate voltage spikes at high frequencies, while also increasing the overall material and packaging costs, making it impossible to achieve miniaturized integrated device design.

[0005] Second, by fine-tuning the overall doping concentration of the drift layer and adjusting the injection dose in the P-body region, the total amount of minority carriers stored in the drift layer is moderately reduced, resulting in a slight decrease in reverse recovery charge. However, this only slightly reduces the minority carrier injection amount and does not establish a dedicated rapid recombination channel for minority carriers within the drift layer. During the diode conduction phase, a large number of holes still accumulate deep within the drift layer, failing to accelerate carrier recombination at its source. The core defect of high reverse recovery loss remains.

[0006] Therefore, the existing technology lacks a device structure that is integrated inside the MOSFET, requires no external devices, and can efficiently accelerate minority carrier recombination in the drift layer and significantly improve the reverse recovery characteristics of the body diode. Summary of the Invention

[0007] This invention designs a SiC MOSFET device and its fabrication method that are integrated inside a MOSFET, reduce the forward conduction voltage drop of the body diode, improve the switching performance of the device, improve the electric field distribution, enhance the avalanche robustness of the body diode, and thus expand the reverse bias safe region, thereby improving the reverse recovery characteristics of the diode.

[0008] The technical solution of the present invention is: a SiC MOSFET device that improves the reverse recovery characteristics of a diode, comprising, from bottom to top, a drain metal layer, an N-type substrate, a first N-type drift layer, a second N-type drift layer, a P-body region, a P+ contact region, an ohmic contact alloy layer and a source metal layer. A downward-extending P++ layer is provided in the middle of the top surface of the second N-type drift layer; The top surface of the P+ contact region is provided with a trench region extending into the P++ layer (4); a gate oxide layer is provided in the trench region; and a filled polysilicon gate is provided in the gate oxide layer. The groove area has N+ areas on both sides extending downward from the top of the P+ contact area into the P-body area; An isolation dielectric layer is deposited on the P+ contact region, and the isolation dielectric layer completely covers the top surface of the polysilicon gate and the gate oxide layer.

[0009] Specifically, the P++ layer is connected to the second N-type drift layer, the P-body region, and the gate oxide layer, respectively.

[0010] Specifically, the P++ layer is formed between the second N-type drift layer and the P-body region, and is embedded entirely within the second N-type drift layer, with its upper surface in contact with the lower surface of the P-body region and the trench region; The horizontal width of the P++ layer is not less than the horizontal width of the trench area.

[0011] Specifically, the ohmic contact alloy layer is located on the side of the isolation medium layer, and its bottom surface is connected to the N+ region and the P+ contact region, respectively.

[0012] Specifically, the source metal layer is located at the top of the structure, forming a good ohmic contact and serving as the source lead-out; The drain metal layer is located at the bottom of the structure, forming a good ohmic contact and serving as the drain lead-out.

[0013] Specifically, the N-type substrate is an N-type 4H-SiC substrate.

[0014] Specifically, the thickness of the first N-type drift layer is greater than the thickness of the second N-type drift layer.

[0015] Specifically, the source metal layer is located at the top of the structure, covering the upper surface of the isolation dielectric layer and the ohmic contact alloy layer; the drain metal layer covers the bottom of the structure.

[0016] A SiC MOSFET device with improved reverse recovery characteristics and its fabrication method are disclosed, comprising the following steps: Step 1: Sequentially grow a first N-type drift layer and a second N-type drift layer on an N-type substrate; Step 2: An initial trench is formed on the second N-type drift layer by etching, and a P++ layer is formed in the initial trench by ion implantation; after implantation, the initial trench is backfilled and planarized by a medium, and the backfill layer covers the P++ layer and is flush with the top surface of the second N-type drift layer. Step 3: Prepare a P-body region on the second N-type drift layer, and form a trench region extending into the P++ layer through an etching process in the middle. Step 4: A pair of P+ contact regions distributed on both sides of the trench region are formed on the P-body region by ion implantation, and N+ regions extending into the P-body region are prepared on the P+ contact regions. Step 5: Prepare a gate oxide layer in the trench region, and form a polysilicon gate in the gate oxide layer by deposition process; Step 6: Prepare an isolation dielectric layer covering the trench region on the P+ contact region; Step 7: Deposit an ohmic contact alloy layer that is connected to the side of the isolation dielectric layer (11) above the N+ region and P+ contact region; Step 8: A source metal layer (13) is formed on the top of the structure by sputtering to cover the top structure; Specifically, a source metal layer (13) is formed at the top of the structure by metal sputtering, serving as the front metal and used as the source electrode lead-out.

[0017] Step 9: A drain metal layer (14) is formed at the bottom of the structure by sputtering and thinning to cover the bottom structure as the back metal for drain electrode lead-out.

[0018] Specifically, in step two, the P++ layer (4) is formed by ion implantation of boron ions, with a doping concentration of 1E19~5E19 cm⁻³ and a width of 2~4 μm.

[0019] This invention incorporates a dual-layer concentration gradient drift layer within a trench SiC MOSFET structure, along with a high-concentration P++ layer positioned between the high-concentration N-type drift layer and the P-body region. This introduces a synergistic effect between the two structures. In the diode's reverse recovery mode, the high-concentration P++ layer accelerates the recombination of stored charges, enhances hole injection efficiency, optimizes the electric field distribution at the PN junction edge, reduces the forward voltage drop of the body diode, and improves the device's switching characteristics. Furthermore, unlike traditional reverse recovery where the stored charge depends on the entire drift region, the high-concentration drift layer forms a highly doped N-region. Under rapid turn-off conditions with high dv / dt, this reduces deep carrier diffusion, allowing carrier recombination to be better distributed on the surface of the PN junction, thus ensuring long-term device reliability. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the structure of the first N-type drift layer prepared in step one of the present invention; Figure 2 This is a schematic diagram of the structure of the second N-type drift layer prepared in step one of the present invention; Figure 3 This is a structural schematic diagram of step two of the present invention; Figure 4 This is a structural schematic diagram of step three of the present invention; Figure 5 This is a structural schematic diagram of step four of the present invention; Figure 6 This is a structural schematic diagram of step five of the present invention; Figure 7 This is a structural schematic diagram of step six of the present invention; Figure 8 This is a structural schematic diagram of step seven of the present invention; Figure 9 This is a structural schematic diagram of step eight of the present invention; Figure 10 This is a structural schematic diagram of step nine of the present invention; In the figure, 1 is the N-type substrate, 2 is the N-type drift layer, 3 is the second N-type drift layer, 4 is the P++ layer, 5 is the P-body region, 6 is the trench region, 7 is the gate oxide layer, 8 is the polysilicon gate, 9 is the N+ region, 10 is the P+ contact region, 11 is the isolation dielectric layer, 12 is the ohmic contact alloy layer, 13 is the source metal layer, and 14 is the drain metal layer. Detailed Implementation

[0021] The present invention will now be described in detail with reference to specific practical examples. Examples of the embodiments are shown in the accompanying drawings. The illustrative embodiments and descriptions of the present invention are for explaining the present invention only and are not intended to limit the present invention.

[0022] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0023] A SiC MOSFET device for improving the reverse recovery characteristics of a diode includes, from bottom to top, a drain metal layer 14, an N-type substrate 1, a first N-type drift layer 2, a second N-type drift layer 3, a P-body region 5, a P+ contact region 10, an ohmic contact alloy layer 12, and a source metal layer 13. A downwardly extending P++ layer 4 is provided in the middle of the top surface of the second N-type drift layer 3; the P++ layer 4 is formed between the second N-type drift layer 3 and the P-body region 5, and is embedded in the second N-type drift layer 3 as a whole, with its upper surface in contact with the lower surface of the P-body region 5 and the trench region 6; the lateral width of the P++ layer 4 is not less than the lateral width of the trench region 6.

[0024] The top surface of the P+ contact region 10 is provided with a trench region 6 extending into the P++ layer 4; a gate oxide layer 7 is provided in the trench region 6; and a filled polysilicon gate 8 is provided in the gate oxide layer 7. N+ regions 9 are provided on both sides of the trench area 6, extending downward from the top surface of the P+ contact area 10 into the P-body area 5; An isolation dielectric layer 11 is deposited on the P+ contact region 10, and the isolation dielectric layer 11 completely covers the top surface of the polysilicon gate 8 and the gate oxide layer 7.

[0025] The ohmic contact alloy layer 12 is located on the side of the isolation dielectric layer 11, and its bottom surface is connected to the N+ region 9 and the P+ contact region 10, respectively. The source metal layer 13 is located at the top of the structure, forming a good ohmic contact and serving as the source lead-out; the drain metal layer 14 is located at the bottom of the structure, forming a good ohmic contact and serving as the drain lead-out.

[0026] A SiC MOSFET device with improved reverse recovery characteristics and its fabrication method are disclosed, comprising the following steps: Step 1, as follows Figure 1-2 As shown, a first N-type drift layer 2 and a second N-type drift layer 3 are sequentially grown on an N-type substrate 1; the thickness of the first N-type drift layer 2 is greater than the thickness of the second N-type drift layer 3.

[0027] Specifically, the N-type substrate 1 is an N-type 4H-SiC substrate; the doping concentration of the first N-type epitaxial layer 2 is 6E14~10E14 cm⁻³, and the thickness is 8~12 μm; The concentration of the second N-type epitaxial layer 3 is 5E14~9E15 cm⁻³, and the thickness is 2~6 μm, which is different from the concentration of the first N-type epitaxial layer 2; Step two, as Figure 3 As shown, an initial trench is formed on the second N-type drift layer 3 by etching, and a P++ layer 4 is formed in the initial trench by ion implantation; after implantation, the initial trench is backfilled and planarized by a medium, and the backfill layer covers the P++ layer 4 and is flush with the top surface of the second N-type drift layer 3. Specifically, the P++ layer 4 is formed by ion implantation of boron ions, with a doping concentration of 1E19~5E19 cm⁻³ and a width of 2~4 μm.

[0028] Step 3, as shown in Figure 4, prepare a P-body region 5 on the second N-type drift layer 3, and form a trench region 6 extending into the P++ layer 4 through an etching process in the middle; Specifically, a P-body region 5 is formed in the second N-type epitaxial layer 3 region by ion implantation, with a doping concentration of 8E17~5E18 cm⁻³ and aluminum ions implanted. A gate trench region 6 is formed by dry etching, extending vertically through the P-body region 5 and ending within the second N-type epitaxial layer 3 region. The trench region 6 has a depth of 2~4 μm and a width of 1~3 μm, which is smaller than the width of the P++ layer 4.

[0029] Step 4, as shown in Figure 5, forms a pair of P+ contact regions 10 distributed on both sides of the trench region 6 on the P-body region 5 by ion implantation, and prepares an N+ region 9 extending to the P-body region 5 on the P+ contact regions 10. Specifically, N+ region 9 and P+ contact region 10 are formed by ion implantation, wherein the doping concentration of N+ region 9 is 8E19~1E20 cm⁻³, and the doping concentration of P+ contact region 10 is 1E18~5E18 cm⁻³; the two regions are in contact from the side and are formed within the P-body region 5.

[0030] Step 5, as shown in Figure 6, a gate oxide layer 7 is prepared in the trench region 6, and a polysilicon gate 8 is formed in the gate oxide layer 7 by a deposition process. In step five, a trench gate structure is formed. A gate oxide layer 7 with a thickness of 40-60 nm is grown using dry oxygen thermal oxidation. After growth, high-temperature annealing is required to ensure the stability of the gate oxide layer. A polysilicon gate 8 is deposited to fill the internal region of the trench, forming a complete trench gate structure.

[0031] Step 6, as shown in Figure 7, prepare an isolation medium layer 11 covering the trench region 6 on the P+ contact region 10; Specifically, an isolation dielectric layer 11 is formed above the trench region 6 by chemical vapor deposition of oxides such as silicon dioxide, and then further planarized as insulation for the gate.

[0032] Step 7, as shown in Figure 8, deposit an ohmic contact alloy layer 12 that is connected to the side of the isolation dielectric layer 11 above the N+ region 9 and the P+ contact region 10; Specifically, an ohmic contact alloy layer 12 is sputtered over the N+ region 9 and the P+ contact region 10 to form a good ohmic contact with the source metal layer 13.

[0033] Step 8, as shown in Figure 9, involves sputtering to form a source metal layer 13 on the top of the structure, covering the top structure. Specifically, a source metal layer 13 is formed at the top of the structure by metal sputtering, serving as the front metal and used as the source electrode lead-out.

[0034] Step nine, as shown in Figure 10, involves forming a drain metal layer 14 at the bottom of the structure by sputtering and thinning, covering the bottom structure as the back metal for drain electrode lead-out.

[0035] This invention employs a highly doped P++ layer 4 as a recombination center to accelerate the storage of charge, optimizing the PN junction side of the body diode. This effectively reduces the forward voltage drop of the body diode and the conduction loss under operating current conditions. Furthermore, during the diode's reverse recovery process, the electric field distribution is optimized by modulating the current spread of the depletion layer, improving the diode's avalanche robustness and reducing reverse recovery charge, thereby enhancing the reverse recovery characteristics of the body diode. Simultaneously, a two-layer drift layer with different concentrations is used, unlike the traditional single-doped drift layer structure. The upper drift layer can form a locally highly doped N-region, reducing the risk of carrier diffusion into deeper defect regions during body diode conduction. Combined with the P++ layer 4, this further restricts carrier movement near the PN junction region, fundamentally reducing the critical reliability issue of bipolar degradation in the body diode.

[0036] Regarding the information disclosed in this case, the following points need to be clarified: (1) The accompanying drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case; other structures can refer to the general design. (2) Where there is no conflict, the embodiments and features disclosed in this case can be combined with each other to obtain new embodiments; The above are merely specific embodiments disclosed in this case, but the scope of protection of this disclosure is not limited thereto. The scope of protection disclosed in this case shall be determined by the scope of protection of the claims.

Claims

1. A SiC MOSFET device that improves diode reverse recovery characteristics, characterized by, It includes, from bottom to top, a drain metal layer (14), an N-type substrate (1), a first N-type drift layer (2), a second N-type drift layer (3), a P-body region (5), a P+ contact region (10), an ohmic contact alloy layer (12), and a source metal layer (13); The second N-type drift layer (3) has a downwardly extending P++ layer (4) in the middle of its top surface; The top surface of the P+ contact region (10) is provided with a trench region (6) extending into the P++ layer (4); a gate oxide layer (7) is provided in the trench region (6); and a filled polysilicon gate (8) is provided in the gate oxide layer (7). The groove area (6) has N+ areas (9) extending downward from the top surface of the P+ contact area (10) into the P-body area (5) on both sides; An isolation dielectric layer (11) is deposited on the P+ contact region (10), and the isolation dielectric layer (11) completely covers the top surface of the polysilicon gate (8) and the gate oxide layer (7).

2. The SiC MOSFET device for improving the reverse recovery characteristics of a diode according to claim 1, characterized in that, The P++ layer (4) is connected to the second N-type drift layer (3), the P-body region (5) and the gate oxide layer (7), respectively.

3. A SiC MOSFET device for improving the reverse recovery characteristics of a diode according to claim 2, characterized in that, The P++ layer (4) is formed between the second N-type drift layer (3) and the P-body region (5), and is embedded in the second N-type drift layer (3). Its upper surface is in contact with the lower surface of the P-body region (5) and the trench region (6). The horizontal width of the P++ layer (4) is not less than the horizontal width of the trench area (6).

4. The SiC MOSFET device for improving the reverse recovery characteristics of a diode according to claim 1, characterized in that, The ohmic contact alloy layer (12) is located on the side of the isolation medium layer (11), and its bottom surface is connected to the N+ region (9) and the P+ contact region (10) respectively.

5. A SiC MOSFET device for improving the reverse recovery characteristics of a diode according to claim 1, characterized in that, The source metal layer (13) is located at the top of the structure, forming a good ohmic contact and serving as the source lead-out; The drain metal layer (14) is located at the bottom of the structure, forming a good ohmic contact and serving as a drain lead-out.

6. A SiC MOSFET device for improving the reverse recovery characteristics of a diode according to claim 1, characterized in that, The N-type substrate (1) is an N-type 4H-SiC substrate.

7. A SiC MOSFET device for improving the reverse recovery characteristics of a diode according to claim 1, characterized in that, The thickness of the first N-type drift layer (2) is greater than the thickness of the second N-type drift layer (3).

8. A SiC MOSFET device for improving the reverse recovery characteristics of a diode according to claim 1, characterized in that, The source metal layer (13) is located at the top of the structure, covering the upper surface of the isolation dielectric layer (11) and the ohmic contact alloy layer (12); the drain metal layer (14) covers the bottom of the structure.

9. A SiC MOSFET device and its fabrication method for improving the reverse recovery characteristics of a diode, comprising the SiC MOSFET device for improving the reverse recovery characteristics of a diode as described in claim 1, characterized in that, Prepared by the following steps: Step 1: Grow a first N-type drift layer (2) and a second N-type drift layer (3) sequentially on an N-type substrate (1); Step 2: An initial trench is formed on the second N-type drift layer (3) by etching, and a P++ layer (4) is formed in the initial trench by ion implantation; After injection, the initial trench is backfilled and leveled with media. The backfill layer covers the P++ layer (4) and is flush with the top surface of the second N-type drift layer (3). Step 3: Prepare a P-body region (5) on the second N-type drift layer (3), and form a trench region (6) extending into the P++ layer (4) through an etching process in the middle. Step 4: A pair of P+ contact regions (10) distributed on both sides of the trench region (6) are formed on the P-body region (5) by ion implantation process, and an N+ region (9) extending to the P-body region (5) is prepared on the P+ contact region (10). Step 5: Prepare a gate oxide layer (7) in the trench region (6), and form a polysilicon gate (8) in the gate oxide layer (7) by deposition process; Step 6: Prepare an isolation medium layer (11) covering the trench region (6) on the P+ contact region (10); Step 7: Deposit an ohmic contact alloy layer (12) connected to the side of the isolation dielectric layer (11) above the N+ region (9) and the P+ contact region (10); Step 8: A source metal layer (13) is formed on the top of the structure by sputtering to cover the top structure; Specifically, a source metal layer (13) is formed at the top of the structure by metal sputtering, which serves as the front metal and is used as the source electrode lead-out; Step 9: A drain metal layer (14) is formed at the bottom of the structure by sputtering and thinning to cover the bottom structure as the back metal for drain electrode lead-out.

10. The SiC MOSFET device and its fabrication method for improving the reverse recovery characteristics of a diode according to claim 9, characterized in that, In step two, the P++ layer (4) is formed by ion implantation of boron ions, with a doping concentration of 1E19~5E19 cm⁻³ and a width of 2~4 μm.

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