Data representation and error correction method and system based on 128-state abacus encoding

Abstract

This invention discloses a data representation and error correction method and system based on 128-state abacus encoding. The 7-bit binary state vector is divided into four functional partitions: numerical state, operation control state, error detection state, and reserved extension state, achieving 100% space utilization. A four-layer collaborative error correction mechanism is constructed to achieve 100% detection and correction of array-level single-bit errors. A carry-avoidance write operation is adopted, where the write operation only marks the carry state, and subsequent read operations autonomously resolve the carry. It is compatible with SRAM storage arrays and combines the advantages of high-density encoding, strong error correction capability, and low write latency, making it suitable for scenarios such as high-reliability storage, high-speed computation, and low-latency transmission.

Description

Technical Field

[0001] This invention relates to the field of digital encoding and error correction encoding technology, and in particular to a data representation and error correction method and system based on 128-state abacus encoding, which is applicable to digital data representation scenarios that require high-density storage, in-situ parallel reading and writing, and single-bit error detection and correction. Background Technology

[0002] In digital systems, the traditional binary representation of decimal numbers typically uses BCD (Binary-Coded Decimal) or ASCII encoding. BCD uses 4 bits to represent one decimal digit (0-9), with 16 possible states, 6 of which are invalid, resulting in a space utilization rate of only 62.5%. ASCII uses 8 bits to represent one decimal digit, with a space utilization rate of only 12.5%. Both encoding methods have the following technical drawbacks: (1) Low space utilization: The six illegal states of BCD code are wasted, and the 248 states of ASCII code are wasted, resulting in low storage density; (2) No error correction capability: Traditional coding does not reserve a state space for error detection and correction. Single bit flip errors cannot be detected, let alone corrected. (3) High carry propagation delay: In traditional decimal arithmetic, when the lower bit is ten, the carry signal needs to be propagated serially. The write operation delay increases to O(N) as the number of data bits N increases. (4) No operation control identifier: Traditional encoding only stores the value and cannot identify the operation state such as carry and borrow in the original position, which leads to the need for external state machine maintenance for cross-column operation; (5) Insufficient coding distance: The Hamming distance of the 10 legal codewords in the 4-bit space of the BCD code is unevenly distributed. Some codeword pairs have a distance of 1. A single bit flip can generate another legal codeword, forming a "silent error" that cannot be uniquely corrected by the lookup table method. (6) Insufficient check bits: Traditional encoding does not have a dedicated check bit, or the number of check bits is insufficient to support error location and correction; (7) Conflict between check value and data value: The check value of traditional encoding may fall into the data value space, causing the check value to be misread as the data value; (8) Lack of coordination in multi-layer detection: Traditional error correction coding only uses single-layer verification (such as parity check or CRC), lacking layered filtering and collaborative correction mechanisms, resulting in high error correction delay and waste of resources. In high-density, high-reliability scenarios such as AI model weight storage, financial transaction data recording, and medical sensor data acquisition, the above-mentioned defects lead to wasted storage space, inability to self-check data errors, uncontrollable write latency, inability to locate silent errors, conflict between checksums and data values, and inefficient error correction mechanisms.

[0003] Therefore, there is an urgent need in this field for a digital coding scheme that is high-density, error-correctable, low-latency, supports in-situ operation control, isolates check values ​​from data values, supports multi-layer detection collaboration, and whose coding distance meets the single-bit error correction requirement. Summary of the Invention

[0004] This invention aims to solve the following technical problems existing in the prior art: (1) Traditional binary encoding for representing decimal numbers suffers from low space utilization and waste of illegal states; (2) Traditional coding lacks the ability to detect and correct single-bit errors, especially it cannot handle "silent errors" (a single bit flipping produces another valid codeword). (3) The problem that the write operation delay of the traditional carry mechanism increases linearly with the number of data bits; (4) The problem that traditional encoding cannot identify the operation control state in place; (5) The codeword distance of traditional coding is insufficient, which leads to the problem that single-bit error correction cannot be uniquely determined; (6) The traditional coding check bits are insufficient, resulting in a lack of error location capability; (7) The traditional encoding check value conflicts with the data value space, causing the check value to be misread as a data value; (8) Traditional error correction coding lacks a multi-layered collaborative mechanism, resulting in high error correction delay and waste of resources. To address the aforementioned technical problems, this invention provides a data representation and error correction method based on 128-state abacus encoding, applied to a digital storage array in a computer-readable storage medium. The method includes the following steps: S1. State space construction steps: A single-column encoding space is constructed using a 7-bit binary state vector. The 7 bits include 2 upper bead bits (s_1, s_2) and 5 lower bead bits (s_3, s_4, s_5, s_6, s_7), for a total of 128 states. S2, State Partitioning Steps: Divide the 128 states into four functional partitions: (a) Numerical state partitioning: 10 states to represent decimal digits 0-9; (b) Operation control state partition: 16 states, used to identify carry, borrow, addition, subtraction, multiplication and division operation states; (c) Error detection state partition: 64 states, used to identify single-bit error modes, double-bit error types and error location information; (d) Reserved extended state partition: 38 states, used for multimodal coding, semantic tagging, encryption extension and check value storage; The error detection state partition and the reserved extended state partition together constitute a redundant state space, which does not intersect with the numerical state partition and the operation control state partition. S3. Encoding constraint application steps: Apply the following constraints to the numerical state partition: (a) Upper bead constraint: s_1 + s_2 ≤ 1; (b) Lower bead constraint: s_3 + s_4 + s_5 + s_6 ≤ 4; (c) Numerical calculation rules: d = 5 × s_2 + (s_3 + s_4 + s_5 + s_6), where d is a decimal number value; S4. Digital hash calculation steps: For any 7-bit state vector, calculate its digital hash function H_abacus. The digital hash function is constructed based on the principle of cyclic redundancy check. The input is 6 information bits (s_1, s_2, s_3, s_4, s_5, s_6), and the output is a 1-bit check value. S5, Carry Avoidance Write Operation Steps: When performing a single-column write operation, only the state vector of the target column is modified, and cross-column carry signal propagation is not triggered; when the current column overflows, the current column is reset to the numerical state 0, and the carry pending state is marked in the operation control state partition; when the subsequent read operation scans the carry mark, the high-order column is incremented by 1 and the carry mark is cleared; S6. In-situ parallel read / write steps: Perform parallel read / write operations on N independent state vectors without carry chain propagation delay; S7. Four-layer cooperative error correction execution steps: When a state vector error is detected, the four-layer cooperative error correction mechanism is executed to achieve the detection and correction of array-level single-bit errors. First layer (constraint verification layer): Verify upper and lower bead constraints; if a constraint is violated, directly locate the error type and correct it through the error mode mapping table; The second layer (check bit comparison layer): calculates the check value based on cyclic redundancy check and compares it with the actual check bit; if they are not equal, an error is determined. The third layer (error mode lookup table layer): Query the state value mapping table. If the state value falls into the redundant state space, determine the original numerical state and correct it. If the state value falls into the numerical state or the operation control state, mark it as not being able to be corrected separately. The fourth layer (array-level parity layer): It determines and corrects error bits by cross-locating pre-stored row parity values ​​and column parity values, achieving system-level single-bit error correction. The decoding step is the reverse of the encoding step: read the 7-bit state vector, and sequentially perform constraint verification, check bit comparison, error mode lookup table, and array-level verification; if all pass, the decimal number is restored through numerical calculation rules; if any layer of detection fails, the corresponding error correction process is triggered.

[0005] In this specification, the following terms have specific meanings: "Carry pending status": This corresponds to status value 10 in the operation control state partition. It is used to mark that the current column has overflowed and a carry operation needs to be performed to the higher-order column. When the read operation scans this status, the carry is automatically resolved. "Silent Error": An error that results in another valid codeword after a single bit flip, which cannot be uniquely identified by a single column constraint or check bit; "Syndrome": A common term in the field of error correction codes, referring to the difference vector between the check value and the calculated value, used to locate the error location. Beneficial effects

[0006] (1) High-density storage: 128 states are fully covered, with no waste of illegal states and 100% space utilization; (2) System-level single-bit error correction: 100% detection and 100% correction of array-level single-bit errors are achieved through a four-layer collaborative error correction mechanism; (3) Isolation of check value and data value: The error detection state partition and the reserved extended state partition serve as redundant state space, which do not intersect with the numerical state and the operation control state, thus avoiding conflict between error state and normal state; (4) Carry avoidance: The time complexity of a single column write operation is always O(1), which is independent of the number of data bits N; the traditional carry chain write delay increases linearly with N, while this invention reduces the write delay to the constant level; (5) In-situ operation control: The operation control state partition can identify carry, borrow and other states in the coded column in-situ, without the need for an external state machine to maintain the cross-column operation context; (6) Parallel scalability: N independent reads and writes can be completed in parallel in O(N) time, supporting high-throughput access to large-scale data arrays; (7) Silent error elimination: Through a four-layer collaborative error correction mechanism, the silent error risk of "single bit flipping to generate another legal codeword" in traditional coding is eliminated; (8) Multi-layer collaborative efficiency: The layered design of the four-layer collaborative error correction mechanism enables about 1 / 7 of the errors to be filtered in the first layer in O(1) time, about 6 / 7 of the errors to be detected in the second layer in O(1) time, some errors to be corrected in the third layer in O(1) time, and the remaining errors to be corrected in the fourth layer in O(M+N) time; compared with the single-layer error correction mechanism, the average error correction delay is reduced by 40%~70%. Detailed Implementation

[0007] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments.

[0008] This embodiment describes in detail the single-column physical structure of the 128-state abacus encoding.

[0009] Each column of the abacus is encoded using a 7-bit binary state vector, and its physical structure is analogous to that of a traditional abacus. • Upper bead 2 (s_1, s_2): Corresponds to the upper column of the abacus, each bead represents the value 5; • Lower 5 beads (s_3, s_4, s_5, s_6, s_7): These correspond to the lower rows of the abacus, where s_3-s_6 are counting beads (each bead represents the value 1), and s_7 is the check digit. State vector format: [s_1, s_2, s_3, s_4, s_5, s_6, s_7] In the 7-bit state vector, s_1 to s_6 are information bits, used to carry numerical values ​​and control status; s_7 is a check bit, which is generated by the first 6 information bits through a digital hash function, does not participate in numerical calculations, and is only used for error detection and correction. Status partition table: Redundancy space is defined as the union of error detection states (26-89) and reserved expansion states (90-127), totaling 102 states with state values ​​ranging from 26 to 127. Redundancy space does not intersect with the numerical state space (0-9) or the operational control state space (10-25). Example of coding constraint validation: Example 1: Encoding the decimal number 7. Upper bead: s_2=1 (representing 5), s_1=0; Lower bead: s_3=1, s_4=1, s_5=0, s_6=0 (representing 2); Check bit: s_7 is calculated from H_abacus; State vector: [0,1,1,1,0,0,s_7]; Numerical verification: d=5×1+(1+1+0+0)=7; Constraint verification: s_1 + s_2 = 1 ≤ 1, s_3 + s_4 + s_5 + s_6 = 2 ≤ 4.

[0010] Example 2: Encoding of the decimal digit 0. Upper bead: s_1=0, s_2=0; Lower bead: s_3=0, s_4=0, s_5=0, s_6=0; Check bit: s_7 is calculated from H_abacus; State vector: [0,0,0,0,0,0,s_7]; Numerical verification: d = 0.

[0011] Example 3: Encoding the decimal number 9. Upper bead: s_2=1 (representing 5), s_1=0; Lower bead: s_3=1, s_4=1, s_5=1, s_6=1 (representing 4); State vector: [0,1,1,1,1,1,s_7]; Numerical verification: d = 9; Constraint verification: s_3 + s_4 + s_5 + s_6 = 4 ≤ 4 (reaching the upper limit of the lower bead).

[0012] This embodiment describes the specific implementation of the digital hash function H_abacus.

[0013] The digital hash function H_abacus is constructed based on the principle of cyclic redundancy check. The input is 6 information bits (s_1, s_2, s_3, s_4, s_5, s_6), and the output is a 1-bit check value.

[0014] Calculation steps: (1) Initialize the linear feedback shift register; (2) Input information bits s_1 to s_6 bit by bit. Shift the register left by 1 bit for each bit input. If the shifted-out bit is 1, perform a bitwise XOR operation with the preset coefficient vector; (3) After inputting, extract the least significant bit of the register as a 1-bit check value s_7'; (4) Compare s_7 and s_7'. If they are not equal, an error is determined.

[0015] Cyclic redundancy check can detect all single-bit and double-bit errors, but a 1-bit check output cannot distinguish the seven error locations.

[0016] This embodiment describes in detail the four-layer collaborative error correction mechanism of the present invention.

[0017] First layer: Constraint verification layer. (1) Read the state vector V=[s_1, s_2, s_3, s_4, s_5, s_6, s_7]; (2) Verify the upper bead constraint: if s_1 + s_2 > 1, it is determined to be ERR_UPPER; (3) Verify the lower bead constraint: if s_3 + s_4 + s_5 + s_6 > 4, it is determined to be ERR_LOWER; (4) The error state falls into the error detection state partition or the operation control state partition, and the original numerical state is determined and corrected through the pre-stored error mode mapping table.

[0018] Constraint verification coverage: Of the 70 single-bit error modes, about 1 / 7 of the error modes (10 s_1 / s_2 flips) will cause constraint violations, which can be directly located through constraint verification. Second layer: Check bit comparison layer. (1) Calculate the check value s_7' based on H_abacus; (2) Compare s_7 and s_7': if they are equal, the check passes; if they are not equal, an error is found; (3) Cyclic redundancy check can detect all single-bit errors and double-bit errors.

[0019] Check bit alignment coverage: In 70 single-bit error modes, about 6 / 7 of the error modes (60 s_3−s_7 flips) will change the information bit or check bit, resulting in s_7 ≠ s_7'. The third layer: Error mode lookup table layer. (1) Pre-store 128 state values ​​to the mapping table of "original numerical state" or "error type"; Mapping table construction rules: For each of the 10 numerical states, flip each bit of the 7 bits in turn to obtain 7 single-bit error states, store the error states that fall into the redundancy state space in order into the error detection state partition, and establish a one-to-one mapping with the original numerical state; (2) For error states where the state value falls into the redundancy state space (26-127), directly determine the original numerical state and correct it through the mapping table; (3) For error states where the state value falls into the numerical state space (0-9) or the operation control state space (10-25) (silent error), mark it as "cannot be corrected separately" and enter the fourth layer.

[0020] Mapping example (core part): The remaining error mode mapping tables are generated according to the above construction rules, covering all error states in the redundant state space.

[0021] Lookup table coverage: Among the 70 single-bit error modes, approximately 1 / 7 of the error modes (10 s_1 and s_2 flips) fall into the redundant state space and can be uniquely corrected through the mapping table. Approximately 6 / 7 of the error modes (60 s_3-s_7 flips) may fall into the numerical state or the operation control state, forming silent errors that require fourth-level processing. Fourth layer: Array-level verification layer. (1) Array structure: M rows × N columns of storage units, with additional row verification columns and column verification rows, pre-stored XOR verification values ​​of information bits for each row and each column; (2) Row verification calculation: For the N columns of state vector of each row, extract the 6 information bits (s_1−s_6) of each column, perform bitwise XOR, and obtain the row verification value; (3) Column verification calculation: For the M rows of state vector of each column, extract the 6 information bits (s_1−s_6) of each row, perform bitwise XOR, and obtain the column verification value; (4) Error location calculation Method: Assume a single-bit error occurs in the i-th row and j-th column (the k-th information bit is flipped); recalculate the XOR value of the i-th row excluding the j-th column, and compare it with the pre-stored row check value to obtain the row Syndrome; recalculate the XOR value of the j-th column excluding the i-th row, and compare it with the pre-stored column check value to obtain the column Syndrome; the intersection of the row with a row Syndrome of 1 and the column with a column Syndrome of 1 uniquely determines the error location; flip the located error bit to restore the original state vector.

[0022] Array-level parity coverage: Under the assumption of single-bit error, 100% error location and correction can be achieved. Four-layer collaborative effect: The first layer filters about 1 / 7 of constraint violation errors with O(1) complexity; the second layer detects about 6 / 7 of information bit errors with O(1) complexity; the third layer corrects some locatable errors with O(1) complexity; the fourth layer corrects the remaining silent errors with O(M+N) complexity; the system-level total coverage is 100% detection and 100% correction (under the assumption of single-bit error).

[0023] This embodiment provides a mathematical proof of the uniqueness of array-level check cross-location.

[0024] Theorem: In an M×N storage array, if each row has an additional row parity value and each column has an additional column parity value, and assuming that at most one single-bit error occurs per row / column, then the cross-location of row and column parities can uniquely determine the error location.

[0025] Proof: (1) Assume the error occurs at the k-th position of the i-th row and j-th column; (2) Row check value R_row[i] = ⊕_{n=1..N} (s_1[i][n]...s_6[i][n]); (3) Recalculate the XOR value R'_row[i] of the i-th row excluding the j-th column; (4) Row Syndrome S_row[i] = R_row[i] ⊕ R'_row[i], since only the k-th position is flipped, the k-th position of S_row[i] is 1; (5) Similarly, the k-th position of column Syndrome S_col[j] is 1; (6) The intersection of row i corresponding to non-zero S_row and column j corresponding to non-zero S_col uniquely determines the error position; (7) Flipping the k-th position of the i-th row and j-th column restores the original value. Q.E.D.

[0026] This embodiment describes the specific implementation of carry-avoidance write operations.

[0027] Traditional decimal addition: when the least significant bit reaches 10, a carry-over is made to the next significant bit. The carry signal needs to be propagated serially, and the write operation delay increases to O(N) as the number of data bits N increases.

[0028] The carry avoidance mechanism of the present invention is as follows: (1) A single column write operation only modifies the state vector of the target column and does not trigger a cross-column signal; (2) When the current column performs a +1 operation and the current value is 9, the current column is reset to the numerical state 0; (3) At the same time, the "carry pending" state (state value 10) is marked in the operation control state partition; (4) When the subsequent read operation scans the carry mark, a +1 operation is performed on the high-order column and the carry mark is cleared; (5) Carry propagation is digested asynchronously by the read operation, and the write operation delay is constant at O ​​(1).

[0029] Write operation latency comparison: Traditional carry-chain write latency increases linearly with N, while the write latency of this invention remains constant and independent of N. In typical large-scale arrays, traditional carry-chain write latency can reach the millisecond level, while the write latency of this invention is at the nanosecond level per cycle.

[0030] This embodiment describes a parallel mechanism for independent reading and writing of N columns.

[0031] Assume the storage array contains N columns of abacus-coded data, each a unique 7-bit state vector. Perform parallel read operations on the N columns: (1) simultaneously read the state vectors of all N columns; (2) independently perform constraint verification and numerical calculation on each column; (3) for columns containing carry flags, perform carry resolution; (4) output N decimal numbers. The time complexity of the parallel read operation is O(N). The time complexity of the parallel write operation is O(N).

[0032] This embodiment describes the complete encoding-decoding process and verifies its correctness.

[0033] Encoding process (decimal number → 7-bit state vector): (1) Input: Decimal number d∈[0,9]; (2) If d≥5: s_2=1, residual value r=d−5; otherwise s_2=0, r=d; (3) Decompose r into lower bead combinations: s_3=min(r,1), s_4=min(max(r−1,0),1), s_5=min(max(r−2,0),1), s_6=min(max(r−3,0),1); (4) s_1=0; (5) Calculate the check bit s_7 = H_abacus(s_1, s_2, s_3, s_4, s_5, s_6); (6) Output 7-bit state vector. Decoding process (7-bit state vector → decimal number or error code): (1) Read the 7-bit state vector; (2) First layer: constraint verification; (3) Second layer: check bit comparison; (4) Third layer: error mode lookup table; (5) Fourth layer: array-level verification; (6) If all checks pass, calculate d = 5 × s_2 + (s_3 + s_4 + s_5 + s_6); (7) Output d∈[0,9]. Verification results: Encoding-decoding loop was performed on all 10 numbers, and 100% restoration was achieved; system-level error correction tests were performed on 70 single-bit error patterns, and 100% detection and correction were achieved. The above embodiments are only used to illustrate the technical solutions of the present invention in detail, and are not intended to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications can be made to the technical solutions described in the above embodiments, or equivalent substitutions, parameter adjustments, and structural modifications can be made to some of the technical features without departing from the core principles and inventive concept of the present invention; the 128-state abacus encoding architecture, four-layer collaborative error correction mechanism, and carry-avoidance writing method of the present invention can also be applied to other types of storage media, computing devices, or data transmission scenarios. These modifications, substitutions, modifications, or extended applications should all fall within the protection scope defined by the claims of the present invention. The specific embodiments in this specification are merely illustrative descriptions and should not be construed as limiting the protection scope of the claims of the present invention.

Claims

1. A data representation and error correction method based on 128-state abacus encoding, characterized in that, A digital storage array applied in a computer-readable storage medium, wherein the digital storage array pre-stores row check columns and column check rows, and records the XOR check value of each row and each column of information bits respectively, the method comprising the following steps: S1. A single-column encoding space is constructed using a 7-bit binary state vector. The 7 bits include 2 upper bead bits (s_1, s_2) and 5 lower bead bits (s_3, s_4, s_5, s_6, s_7), for a total of 128 states. S2. Divide the 128 states into four functional partitions: numerical state partition (10 states, representing decimal numbers 0-9), operation control state partition (16 states, identifying carry / borrow / operation states), error detection state partition (64 states, used for single-bit error mode identification and double-bit error detection), and reserved extension state partition (38 states, used for multimodal / semantic / encryption extension and checksum storage); among them, the error detection state partition and the reserved extension partition together constitute a redundant state space, which does not intersect with the numerical state partition and the operation control partition; S3. Apply coding constraints to the numerical state partition: upper bead constraint s_1 + s_2 ≤ 1, lower bead constraint s_3 + s_4 + s_5 + s_6 ≤ 4, numerical calculation rule d = 5 × s_2 + (s_3 + s_4 + s_5 + s_6); S4. Calculate the digital hash function H_abacus, which is constructed based on the principle of cyclic redundancy check, with 6 information bits as input and 1 check value as output. S5. When performing a single-column write operation, only the state vector of the target column is modified, and the cross-column carry signal propagation is not triggered; when overflow occurs, the current column is reset to the numerical state 0 and the carry-to-process state is marked in the operation control state partition; when the subsequent read operation scans the carry mark, the high-order column is incremented by 1 and the carry mark is cleared. S6. Perform parallel read and write operations on N independent state vectors; S7. When a state vector error is detected, a four-layer collaborative error correction mechanism is executed to detect and correct array-level single-bit errors: The first layer, the constraint verification layer, verifies the upper and lower bead constraints; the second layer, the check bit comparison layer, calculates and compares the check value based on cyclic redundancy check; the third layer, the error mode lookup table layer, queries the state value mapping table, and if the state value falls into the redundancy state space, the original numerical state is determined and corrected; if the state value falls into the numerical state or the operation control state, it is marked as not being correctable by a single column; the fourth layer, the array-level check layer, determines and corrects the error bit by cross-locating the pre-stored row check value and column check value.

2. The method according to claim 1, characterized in that, The state value ranges of the four functional partitions in step S2 are as follows: numerical state 0-9, operation control state 10-25, error detection state 26-89, and reserved extension state 90-127.

3. The method according to claim 1, characterized in that, The specific calculation process of the digital hash function H_abacus in step S4 includes: initializing the linear feedback shift register; inputting information bits s_1 to s_6 bit by bit, shifting the register left by 1 bit for each input bit, and XORing the shifted-out bit with the preset coefficient vector if it is 1; after the 6 bits are input, extracting the least significant bit of the register as a 1-bit check value.

4. The method according to claim 1, characterized in that, The third-layer error mode lookup table layer in step S7 includes a mapping table that pre-stores 128 state values ​​to the original numerical state or error type. The mapping table covers 64 states in the error detection state partition and some states in the reserved extended state partition. The construction rule of the mapping table is as follows: for each of the 10 numerical states, flip each of the 7 bits in sequence to obtain 7 single-bit error states. Store the error states that fall into the redundant state space in the error detection state partition in sequence and establish a one-to-one mapping with the original numerical state.

5. The method according to claim 1, characterized in that, The fourth array-level verification layer in step S7 includes: performing a bitwise XOR operation on the information bits of each row and N columns of the state vector to obtain the row verification value; performing a bitwise XOR operation on the information bits of each column and M rows of the state vector to obtain the column verification value; and determining and correcting error bits through the cross-location of row Syndrome and column Syndrome.

6. The method according to claim 1, characterized in that, The digital storage array is a static random access memory (SRAM) array, which consists of 6T SRAM storage cells with M rows × N columns. Each column stores a 7-bit state vector. The SRAM array includes a state vector register, a read / write controller, an address decoder, a word line driver, a bit line driver, a sensitive amplifier, and a precharge circuit.

7. The method according to claim 6, characterized in that, The read / write timing of the SRAM array includes: a precharge phase, a word line activation phase, a read / write execution phase, and a word line shutdown phase.

8. A data representation and error correction system based on 128-state abacus encoding, characterized in that, include: The state space construction module is used to construct a single-column encoding space of 128 states using a 7-bit binary state vector; The system comprises four functional modules: a state partitioning management module, a state control module, an error detection module, and a reserved extension module; a coding constraint verification module, a state constraint of s_1 + s_2 ≤ 1, and a state constraint of s_3 + s_4 + s_5 + s_6 ≤ 4; a numerical calculation module, a state calculation module, and a digit hashing module. The digit hashing module is used to calculate a 1-bit checksum based on the cyclic redundancy check principle. The single-bit error correction module executes a four-layer collaborative error correction mechanism: a constraint verification layer, a checksum comparison layer, an error mode lookup table layer, and an array-level checksum layer. The carry avoidance writing module performs single-column write operations and asynchronously resolves carry using the operation control state flag. Finally, the in-situ parallel read / write module performs parallel read / write operations on N independent state vectors. A digital storage array is used to store the 7-bit state vector, and the digital storage array pre-stores row check columns and column check rows.

9. The system according to claim 8, characterized in that, The system is applied to an AI model weight storage device, which includes a digital storage array, a read / write controller, an array-level verification engine, and a bus interface. It supports transparent loading of abacus-encoded models and system-level single-bit error self-repair.