Three-dimensional memory and memory systems

Abstract

This application provides a three-dimensional memory. The three-dimensional memory includes: a memory array structure, including a first memory array structure and a second memory array structure disposed along a first direction; a bridging structure connecting the first memory array structure and the second memory array structure, including a plurality of alternately stacked dielectric layers and a plurality of conductive layers; and a plurality of dummy channel structures, each dummy channel structure passing through the bridging structure along the stacking direction of the bridging structure, and in a plane perpendicular to the stacking direction, the maximum dimension of the dummy channel structure in the first direction is greater than its maximum dimension in the second direction, and the second direction intersects with the first direction.

Description

[0001] This application is a divisional application of the patent filed on February 16, 2022, with application number 202210139610.4, entitled "Three-Dimensional Memory and Memory System". Technical Field

[0002] This application relates to the field of semiconductor technology, and more specifically, to three-dimensional memory and memory systems. Background Technology

[0003] In some three-dimensional memories, a ladder structure for word line outgoings is located in the middle of the storage plane, enabling, for example, a line decoder to drive word lines bidirectionally in opposite directions from the middle position of the storage plane, thereby reducing the resistance in the load and electrically connecting the word lines separated by the ladder through a bridging structure. Summary of the Invention

[0004] This application provides a three-dimensional memory, which includes: a memory array structure, including a first memory array structure and a second memory array structure disposed along a first direction; a bridging structure, including a plurality of alternately stacked dielectric layers and a plurality of conductive layers; and a plurality of dummy channel structures, each dummy channel structure passing through the bridging structure along the stacking direction of the bridging structure, and on a plane perpendicular to the stacking direction, the maximum dimension of the shape of the dummy channel structure in the first direction is greater than its maximum dimension in the second direction, and the second direction intersects with the first direction.

[0005] In some implementations, the ratio of the maximum dimension of the dummy channel structure in the first direction to its maximum dimension in the second direction is 1.2 to 1.8 in a plane perpendicular to the stacking direction.

[0006] In some implementations, the dummy channel structure has a smooth profile in a plane perpendicular to the stacking direction.

[0007] In some implementations, the dummy channel structure is elliptical in shape on a plane perpendicular to the stacking direction.

[0008] In some embodiments, the three-dimensional memory further includes: a first gate slot structure located in the bridging structure and extending continuously along a first direction; and at least one second gate slot structure located in the bridging structure and on one side of the first gate slot structure, each of the second gate slot structures extending intermittently along the first direction; wherein a plurality of dummy channel structures are arranged in rows along the first direction, and the plurality of dummy channel structures are arranged in at least one row between adjacent first gate slot structures and second gate slot structures.

[0009] In some embodiments, the three-dimensional memory further includes: a first gate slot structure located in the bridging structure and extending continuously along a first direction; and at least one second gate slot structure located in the bridging structure and on one side of the first gate slot structure, each second gate slot structure extending intermittently along the first direction; wherein a plurality of dummy channel structures are arranged in rows along the first direction, and between adjacent second gate slot structures, the plurality of dummy channel structures are arranged in at least one row. In some embodiments, between adjacent first gate slot structures and second gate slot structures, or between adjacent second gate slot structures, the plurality of dummy channel structures are arranged in one or two rows.

[0010] In some embodiments, the number of second grid line slot structures located on one side of the first grid line slot structure is greater than or equal to 2.

[0011] In some embodiments, there is a predetermined interval between adjacent dummy channel structures, and there is a predetermined interval between the dummy channel structure and the first grid line slot structure or the second grid line slot structure.

[0012] In some embodiments, at least one second gate line slot structure is located on the other side of the first gate line slot structure.

[0013] In some embodiments, the three-dimensional memory further includes a plurality of steps disposed adjacent to the bridging structure in a second direction and at different heights, each step being electrically connected to at least one of the first memory array structure and the second memory array structure via the bridging structure.

[0014] This application also provides a memory system comprising: at least one three-dimensional memory as described in any of the embodiments above; and a memory controller electrically connected to the three-dimensional memory for controlling the three-dimensional memory.

[0015] According to at least one embodiment of this application, the three-dimensional memory and memory system provided by this application, by making the maximum dimension of each dummy channel structure in the first direction larger than the maximum dimension in the second direction, results in a smaller area of ​​each fourth conductive layer occupied by the dummy channel structure in the plane perpendicular to the first direction (i.e., the current transmission direction of each fourth conductive layer of the bridging structure). This allows each fourth conductive layer in the bridging structure to have a relatively large area, thereby reducing the equivalent resistance of the bridging structure and improving the overall electrical performance of the three-dimensional memory in connecting the first memory array structure and the second memory array structure through the bridging structure. Furthermore, it also helps reduce the risk of open circuits due to voids caused by incomplete filling during the fabrication of each fourth conductive layer. Simultaneously, the larger maximum dimension in the first direction helps ensure the support performance of the dummy channel structure. Attached Figure Description

[0016] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein: Figure 1 This is a top view schematic diagram of a three-dimensional memory according to an embodiment of this application; Figure 2 It is based on Figure 1 A partially enlarged schematic diagram of the three-dimensional memory is shown; Figure 3 This is a perspective view of a stepped structure according to another embodiment of this application; Figure 4A and Figure 4B This is a perspective view of the stepped structure according to Embodiment 1 of this application; Figure 4C This is a top view schematic diagram of a part of the stepped structure according to Embodiment 1 of this application; Figure 5A and Figure 5B This is a perspective view of the stepped structure according to Embodiment 2 of this application; Figure 5C This is a top view schematic diagram of a portion of the stepped structure according to Embodiment 2 of this application; and Figure 6A and Figure 6B This is a schematic diagram of a memory system according to an embodiment of this application. Detailed Implementation

[0017] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0018] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first part discussed herein may also be referred to as the second part, and the first channel structure may also be referred to as the second structure, and vice versa.

[0019] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0020] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0021] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0022] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The present application will now be described in detail with reference to the accompanying drawings and embodiments. In the various drawings of this application, the x-direction and y-direction represent two perpendicular directions in a three-dimensional memory. For example, the x-direction may be the word line (WL) direction of the three-dimensional memory, and the y-direction may be the bit line (BL) direction of the three-dimensional memory. The same concepts used to describe spatial relationships are applied throughout the present application. For example, the x-direction may be a first direction, and the y-direction a second direction.

[0023] Furthermore, when the term "connection" or "linkage" is used in this application, it may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or deduced from the context.

[0024] Figure 1 This is a top view schematic diagram of a three-dimensional memory 100 according to an embodiment of this application. (See attached diagram.) Figure 1As shown, the three-dimensional memory 100 includes, for example, two memory planes 101. Each memory plane 101 includes a first memory array structure 110-1 and a second memory array structure 110-2 arranged along the x-direction, and a stepped structure 120 located between the first memory array structure 110-1 and the second memory array structure 110-2. In some examples, the stepped structure 120 may equally divide the memory array structure into a first memory array structure 110-1 and a second memory array structure 110-2 having the same number of memory cells. For example, the first memory array structure 110-1 and the second memory array structure 110-2 may be symmetrically distributed in the x-direction with respect to the stepped structure 120. In other examples, the stepped structure 120 may not be in the middle (center) of the memory array structure, such that the first memory array structure 110-1 and the second memory array structure 110-2 may have different numbers of memory cells.

[0025] In some embodiments, a plurality of word lines (not shown) extending in the x-direction of storage plane 101 may be divided into two parts by a step structure 120, namely a plurality of first word lines located in a first storage array structure 110-1 and a plurality of second word lines located in a second storage array structure 110-2. As will be described in detail below, the plurality of first word lines and the plurality of second word lines may be electrically connected by a bridging structure (not shown) in the step structure 120. In some examples, a line decoder (not shown) may be provided directly above, directly below, or near the step structure 120 in each storage plane 101 to reduce interconnect length. When the ladder structure 120 is located between the first memory array structure 110-1 and the second memory array structure 110-2, the row decoder can drive the memory cells in the first memory array structure 110-1 and the second memory array 110-2 bidirectionally (positive x direction and negative x direction), thereby helping to reduce the time required to drive the memory cells via word lines and improve the problem of resistor-capacitor (RC) delay.

[0026] Figure 2 It is based on Figure 1 A partially enlarged schematic diagram of the three-dimensional memory 100 is shown. (See attached image.) Figure 2 As shown, the three-dimensional memory 100 may include memory blocks 102 divided by a first gate line slot structure 141 extending continuously along the x-direction. Exemplarily, in the three-dimensional memory 100, each memory block 102 is a minimum erasable unit. Each memory block 102 may also include a pointer memory region 103 divided by a second gate line slot structure 142 extending discontinuously along the x-direction and having discontinuous portions 153.

[0027] In some embodiments, the stepped structure 120 may include a stepped region consisting of multiple steps arranged along the y-direction and a bridging structure 121 adjacent to the stepped region. For example, the stepped region and the bridging structure 121 do not overlap. The bridging structure 121 may span two memory blocks 102 in the y-direction. In other words, the two portions 121-1 and 121-2 of the bridging structure 121 may be located in the two memory blocks 102 respectively. Exemplarily, the three-dimensional memory 100 may also include multiple word line contacts (e.g., 132) in the respective stepped regions of the stepped structure 120 to land at each step in the respective steps of the stepped structure 120.

[0028] In some embodiments, the first memory array 110-1 may include a first stacked structure (not shown) of a plurality of first dielectric layers and a plurality of first conductive layers alternately stacked in the z-direction (i.e., perpendicular to the x and y directions). The material of the first conductive layer may include, but is not limited to, tungsten (W), cobalt (Co), copper (Gu), aluminum (Al), polycrystalline silicon (e.g., doped polycrystalline silicon), silicides, or any combination thereof. The material of the first dielectric layer may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. Exemplarily, the number of pairs of first dielectric layers and first conductive layers may correspond to the number of memory cells in the three-dimensional memory 100.

[0029] In some embodiments, the first memory array structure 110-1 may include, for example, a plurality of channel structures (e.g., 111) extending through the first stacked structure along the z-direction. Exemplarily, the channel structure 111 may have a generally external contour shape such as a cylinder, a frustum, or a prism. Exemplarily, the channel structure 111 may include a charge blocking layer, a charge trapping layer, a tunneling layer, and a channel layer (not shown) arranged sequentially from the outside in. In this application, the charge blocking layer, charge trapping layer, and tunneling layer may be referred to, for example, as memory functional layers. Exemplarily, the materials of the charge blocking layer, charge trapping layer, and tunneling layer may sequentially include, for example, silicon oxide, silicon nitride, and silicon oxide. The material of the channel layer may include, for example, polysilicon.

[0030] In some embodiments, the storage function layer and the channel layer in the channel structure 111, along with a portion corresponding to a first conductive layer in the first stacked structure and a portion of the first conductive layer, together constitute a storage cell. For example, the first conductive layer can serve as a control gate for a storage cell, and also as a first word line connecting multiple storage cells in the first storage array structure 110-1.

[0031] In some implementations, multiple memory cells may be distributed in a three-dimensional array relative to the xy plane. As described above, the multiple channel structures (e.g., 111) and the first stack structure may be referred to as "first memory array structure 110-1".

[0032] In some embodiments, the second memory array structure 110-2 may include a second stacked structure (not shown) comprising a plurality of second dielectric layers and a plurality of second conductive layers alternately stacked in the z-direction. It is understood that since the second memory array structure 110-2 has a similar internal structure to the first memory array structure 110-2, it will not be described in detail here. It should be noted that the second conductive layer may serve as a second word line connecting the plurality of memory cells in the second memory array structure 110-2. The plurality of first conductive layers (first word lines) in the same z-direction correspond one-to-one with the plurality of second conductive layers (second word lines).

[0033] Figure 3 This is a perspective view of a stepped structure 220 according to another embodiment of this application. The stepped structure 220 may be... Figure 1 and Figure 2 An example of a portion of the stepped structure 120 shown.

[0034] like Figure 3 As shown, in some embodiments, within the step region 203 of the step structure 220, multiple steps (e.g., steps 231-1, 231-2, 232-1, 232-2, 233-1, 233-2 and 234-1, 234-2) are arranged (e.g., arranged) along the x-direction and located at different heights.

[0035] The structure of step 231-1 is further illustrated below using it as an example. In some embodiments, step 231-1 includes a plurality of third dielectric layers and a plurality of third conductive layers 237 alternately stacked in the z-direction. Each of the third conductive layers in step 231-1 may be connected to the first memory array structure 110-1 (see reference 110-1). Figure 2 Each of the first conductive layers (first word lines) in the step 231-1 corresponds one-to-one in the same z-direction. In other words, each of the third conductive layers in the step 231-1 can be physically connected to its corresponding first conductive layer (first word line) to achieve electrical connection.

[0036] In some embodiments, the staircase 231-1 includes multiple steps. It should be noted that, in this application, a step may refer to a structure having two staggered (or aligned) horizontal first surfaces (e.g., first surfaces parallel to the xy plane) and a second surface vertically (or substantially vertically) connecting the two horizontal first surfaces. Exemplarily, the first surface of a step may be the surface of a third conductive layer. Exemplarily, the offset distance in the z-direction between the two first surfaces in one step of the staircase 231-1 may be the sum of the thicknesses of a pair of third dielectric layers and a third conductive layer. Optionally, the second surfaces in adjacent steps of the staircase 231-1 may be offset by the same distance in the x-direction. Exemplarily, the first surface in each step may serve as a word line contact 132 extending along the z-direction (see reference). Figure 1The “landing zone” of the word line contact 132, in other words, the word line contact 132 contacts the third conductive layer on the first surface of each step and achieves electrical connection for leading out the third conductive layer.

[0037] It is understood that since each step includes multiple steps, the height of the step referred to in this application may be referenced to the height of the same step at the same relative level in the z direction (e.g., the horizontal plane where the lowest plane of the first stacked structure in the z direction is located in the first storage array structure 110-1), such as the top step or the bottom step.

[0038] In some embodiments, the multiple staircases 231-1, 231-2, 232-1, 232-2, 233-1, 233-2, 234-1, and 234-2 can be divided into multiple pairs of staircases, such as a first pair of staircases 231-1 / 231-2, a second pair of staircases 232-1 / 232-2, a third pair of staircases 233-1 / 233-2, and a fourth pair of staircases 234-1 / 234-2. Exemplarily, each pair of staircases 231-1 / 231-2, 232-1 / 232-2, 233-1 / 233-2, and 234-1 / 234-2 can have an inclined orientation facing each other; for example, the inclined orientation of staircase 231-1 is in the positive x-direction, and the inclined orientation of staircase 231-2 is in the negative x-direction. For example, each of the pairs of steps (e.g., 231-1 / 231-2) is located at a different height. For example, the height of step 231-1 is higher than the height of step 231-2. For example, the height of the top step in step 231-1 is higher than the height of the top step in step 231-2.

[0039] It is worth noting that, Figure 3 The stepped structure 220 shown is exemplary, and the stepped structure 220 may also have other stepped forms that can lead out the third conductive layer. For example, the stepped structure may include a pair of steps with an inclined orientation facing each other, which is not specifically limited in this application.

[0040] like Figure 3As shown, the bridging structure 221 may include a plurality of fourth conductive layers that correspond one-to-one with each of the first conductive layers (first word lines) in the first memory array structure 110-1 and each of the second conductive layers (second word lines) in the second memory array structure 110-2 in the same z-direction, and the fourth dielectric layers are located between adjacent fourth conductive layers. In other words, the bridging structure 221 includes a plurality of fourth dielectric layers and a plurality of fourth conductive layers stacked alternately along the z-direction. The first conductive layers (first word lines) in the first memory array structure 110-1 and the second conductive layers (second word lines) in the second memory array structure 110-2 are physically connected through the fourth conductive layers in the bridging structure 221, so that each first conductive layer (first word line) and its corresponding second conductive layer (second word line) are electrically connected.

[0041] In one exemplary embodiment, the third conductive layer corresponding to each step in the staircase 231-2 can be electrically connected to the first memory array structure 110-1 and the second memory array structure 110-2 via a fourth conductive layer extending in the negative x-direction and the positive x-direction, respectively, through the bridging structure 221. For example, Figure 3 The middle arrow indicates the current path when the third conductive layer in step 231-2 is electrically connected to the first memory array structure 110-1 and the second memory array structure 110-2.

[0042] In another exemplary embodiment, the third conductive layer corresponding to each step in the staircase 231-1 can be electrically connected to the second memory array structure 110-2 via a fourth conductive layer extending in the positive x direction through the bridging structure 221. However, the third conductive layer corresponding to each step in the staircase 231-1 may not be electrically connected to the first memory array structure 110-1 via the bridging structure 221, because the third conductive layer of the staircase 231-1 extending in the negative x direction and the first conductive layer (first word line) in the first memory array structure 110-1 are not cut off.

[0043] Figure 4A and Figure 4B This is a schematic diagram of the stepped structure 320 according to Embodiment 1 of this application. Figure 4B for Figure 4A A partially enlarged view of the stepped structure 320 is shown. Figure 4C This is a top view schematic diagram of a portion of the stepped structure 320 according to Embodiment 1 of this application. The stepped structure 320 may be... Figure 1 or Figure 2 An example of a portion of the stepped structure 120 is shown. In Embodiment 1, as... Figure 4AAs shown, the first gate line slot structure 341 and the second gate line slot structures 342-1 and 342-2 are located in the bridging structure 321. The second gate line slot structures 342-1 and 342-2 are located on both sides of the first gate line slot structure 341 along the y-direction. In other words, a second gate line slot structure 342-1 or 342-2 is provided on the same side of the extension direction (x-direction) of the first gate line slot structure 341 in the bridging structure 321. As described above, each of the fourth conductive layers (e.g., 3211) in the bridging structure 321 extends along the x-direction and is physically and electrically connected to each of the first conductive layers (first word lines) in the first memory array structure 110-1 and each of the second conductive layers (second word lines) in the second memory array structure 110-2 (see reference). Figure 2 ).

[0044] In Embodiment 1, the first gate line slot structure 341 and the second gate line slot structure (e.g., 342-1) may have the same or different internal structures. Figure 4B As shown, exemplarily, each second gate line slot structure (e.g., 342-1) may be composed of a conductive layer 3422 and an insulating layer 3421 surrounding the conductive layer 3422. The conductive layer 3422 in the second gate line slot structure 342-1 may be connected to a common source layer along with multiple channel structures (e.g., 111), and may serve as, for example, a common source lead-out structure (not shown) for multiple channel structures. The insulating layer 3421 may, for example, be used to form electrical isolation between multiple first conductive layers (first word lines), multiple second conductive layers (second word lines), multiple third word lines, or multiple fourth word lines (e.g., 3211) on both sides of its extension direction (x-reverse). In some examples, such as... Figure 4B As shown, the internal structure of the first grid line slot structure 341 may differ from that of the second grid line slot structure 342-1. For example, the first grid line slot structure 341 may be made of insulating material.

[0045] In implementation method one, such as Figure 4B As shown, for each fourth conductive layer (e.g., 3211), charges (e.g., electrons) in the fourth conductive layer can be transported along the x-direction, thereby generating a current connecting the first conductive layer (first word line) in the first memory array structure 110-1 and the second conductive layer (second word line) in the second memory array structure 110-2, for example... Figure 4B The arrows shown indicate the direction of the current path.

[0046] In implementation method one, such as Figure 4CAs shown, multiple dummy channel structures (e.g., 331-1, 331-2) may be located in the bridging structure 321-2. Each dummy channel structure (e.g., 331-1) may extend through the bridging structure 321-2 along the z-direction, for example, extending along the z-direction and located in the bridging structure 321-2. Exemplarily, the dummy channel structure 331-1 may be used to provide mechanical support and / or load balancing.

[0047] The maximum dimension of each dummy channel structure (e.g., 331-1) in the x-direction can be greater than its maximum dimension in the y-direction (i.e., by reducing the maximum dimension of the dummy channel structure (e.g., 331-1) in the y-direction), so that the area occupied by each fourth conductive layer of the dummy channel structure 331-1 is smaller in the plane perpendicular to the x-direction (i.e., the current transmission direction of each fourth conductive layer in the bridging structure 321). This results in each fourth conductive layer in the bridging structure 321 having a relatively large area, which in turn helps to reduce the equivalent resistance Rs of the bridging structure 321 and improves the overall electrical performance of the three-dimensional memory that connects the first memory array structure and the second memory array structure through the bridging structure 321. On the other hand, it also helps to reduce the risk of open circuits due to voids caused by incomplete filling during the fabrication of each fourth conductive layer (e.g., 3211). At the same time, having a larger maximum dimension in the x-direction helps to ensure the support performance of the dummy channel structure.

[0048] For example, the cross-sectional shape of the dummy channel structure 331-1 in the plane perpendicular to the z-direction can be an ellipse with its major axis parallel to the x-direction. For instance, the ratio of the major axis a to the minor axis b of the ellipse can satisfy 1.2 to 1.8, and more specifically, the ratio of the major axis a to the minor axis b of the ellipse can satisfy 1.3 to 1.5 or 1.7 to 1.8. In some examples, the value of the major axis a of the ellipse can be 430 to 490 nm, and the value of the minor axis b can be 240 to 355 nm. It should be noted that the cross-sectional shape of the dummy channel structure 331-1 in the plane perpendicular to the z-direction can also be other shapes that satisfy the above-mentioned maximum size condition, such as rectangles, polygons, etc., and this application does not specifically limit them.

[0049] In Embodiment 1, each dummy channel structure (e.g., 331-1) may have a smooth outer contour in its cross-sectional shape on the xy plane. For example, each dummy channel structure (e.g., 331-1) may have an elliptical cross-sectional shape on the xy plane. Using an elliptical cross-sectional shape for the dummy channel structure 331-1 reduces the risk of mouse-bite defects, resulting in good shape retention and minimal deformation. It also reduces the risk of merging with adjacent structures (e.g., dummy channel structures, first grid line slot structures, or second grid line slot structures) due to shape variations. Furthermore, the dummy channel structure 331-1 provides better support.

[0050] In Embodiment 1, adjacent dummy channel structures 331-1 and 331-2 in the x-direction may have a predetermined spacing distance x, dummy channel structure 331-4 and the first gate line slot structure 341 in the y-direction may have a predetermined spacing distance y2, and dummy channel structure 331-3 and the second gate line slot structure 342-2 in the y-direction may have a predetermined spacing distance y3. For example, the values ​​of spacing distances x, y2, and y3 may not be less than 80 nm. By ensuring that spacing distances x, y2, and y3 meet predetermined thresholds, it is beneficial to reduce the risk of dummy channel structures (e.g., 331-1, 331-2), the first gate line slot structure 341, and the second gate line slot structure 342-2 combining with each other due to morphological changes.

[0051] In one implementation, such as Figure 4C As shown, multiple dummy channel structures (e.g., 341-1, 341-2) can be arranged in rows along the x-direction. Between adjacent first grid line slot structures 341 and second grid line slot structures 342-2, multiple dummy channel structures (e.g., 331-1, 331-2) can be arranged in at least one row. For example, between adjacent first grid line slot structures 341 and second grid line slot structures 342-2, multiple dummy channel structures (e.g., 331-1, 331-2) can be arranged in a row, which allows each dummy channel structure (e.g., 331-1 or 331-2) to have maximized size within a defined area, thus providing better support.

[0052] Figure 5A and Figure 5B This is a schematic diagram of the stepped structure 420 according to Embodiment 2 of this application. Figure 5B for Figure 5A A partially enlarged view of the stepped structure 420 is shown. Figure 5C This is a top view schematic diagram of a portion of the stepped structure 420 according to Embodiment 2 of this application. The stepped structure 420 may be... Figure 1 or Figure 2 An example of a portion of the stepped structure 120 is shown. The contents identical to those in Embodiment 1 will not be repeated here.

[0053] In implementation method two, such as Figure 5A As shown, the first grid line slot structure 441 and the second grid line slot structures 442-1, 442-2, 442-3, and 442-4 are located in the bridging structure 421. The second grid line slot structures 442-1 and 442-3 are located on one side of the first grid line slot structure 441 along the y-direction, and the second grid line slot structures 442-2 and 442-4 are located on the other side of the first grid line slot structure 441 along the y-direction. In other words, two second grid line slot structures 442-1 and 442-3 or 442-2 and 442-4 are provided on the same side of the extension direction (x-direction) of the first grid line slot structure 441 in the bridging structure 421. As described above, each of the fourth conductive layers (e.g., 4211) in the bridging structure 421 extends along the x-direction and is physically and electrically connected to each of the first conductive layers (first word lines) in the first memory array structure 110-1 and each of the second conductive layers (second word lines) in the second memory array structure 110-2.

[0054] In implementation method two, such as Figure 5B As shown, each of the fourth conductive layers (e.g., 4211) in the bridging structure 442-1 can allow charge to be transferred across both sides of the second gate line slot structure 442-1 through the discontinuity 453 of the second gate line slot structure 422-1. Thus, for each fourth conductive layer (e.g., 4211), the charge (e.g., electrons) in the fourth conductive layer can be transferred along the x-direction, thereby generating a current connecting the first conductive layer (first word line) in the first memory array structure 110-1 and the second conductive layer (second word line) in the second memory array structure 110-2, for example... Figure 5B The arrows shown indicate the direction of the current path. By increasing the area of ​​each fourth conductive layer (e.g., 4211) of the bridging structure 421 in a plane perpendicular to the current transmission direction, it is beneficial to reduce the equivalent resistance Rs of each fourth conductive layer (e.g., 4211), thereby improving the problem of RC delay.

[0055] It should be noted that, Figure 5A and Figure 5B The two second gate slot structures shown (e.g., 442-2 and 442-4) located in the bridging structure 421 and on one side of the first gate slot structure 441 are merely exemplary. Under other structural layouts in the three-dimensional memory, n second gate slot structures may be located in the bridging structure and on one side of the first gate slot structure. Here, n is an integer positive number greater than or equal to 2.

[0056] In implementation method two, such as Figure 5C As shown, adjacent dummy channel structures 431-1 and 431-2 in the x-direction may have a predetermined spacing distance x; adjacent dummy channel structures 431-1 and 431-3 in the y-direction may have a predetermined spacing distance y1; dummy channel structure 431-4 and the first gate line slot structure 441 in the y-direction may have a predetermined spacing distance y2; and dummy channel structure 431-3 and the second gate line slot structure 442-2 in the y-direction may have a predetermined spacing distance y3. For example, the values ​​of spacing distances x, y1, y2, and y3 may not be less than 80 nm. By ensuring that spacing distances x, y1, y2, and y3 meet predetermined thresholds, it is beneficial to reduce the risk of dummy channel structures (e.g., 431-1 to 431-4), the first gate line slot structure 441, and the second gate line slot structures 442-2 and 442-4 combining due to morphological changes.

[0057] In implementation method two, such as Figure 5C As shown, multiple dummy channel structures (e.g., 441-1 to 441-4) can be arranged in rows along the x-direction. Between adjacent first grid line slot structures 441 and second grid line slot structures 442-2, or between adjacent second grid line slot structures 442-2 and 442-4, multiple dummy channel structures (e.g., 431-1 to 431-4) can be arranged in at least one row. For example, between adjacent first grid line slot structures 441 and second grid line slot structures 442-2, multiple dummy channel structures (e.g., 431-4) can be arranged in a row, allowing each dummy channel structure (e.g., 431-4) to have a larger size within a defined area, which is beneficial for providing better support. Between adjacent second grid line slot structures 442-2 and 442-4, multiple dummy channel structures (e.g., 431-1 and 431-3) can be arranged in two rows. This is beneficial for each dummy channel structure (e.g., 431-1) to have a larger size within a defined area, while the two rows of dummy channel structures are relatively evenly distributed, thereby facilitating better stress balance.

[0058] Although an exemplary structure of a three-dimensional memory has been described herein, it will be understood that one or more features may be omitted, substituted, or added to the structure of the three-dimensional memory. For example, the three-dimensional memory may also include multiple peripheral devices. Furthermore, the materials of the layers described are merely exemplary.

[0059] Figure 6A and Figure 6B These are schematic diagrams of memory systems 2000a and 2000b according to embodiments of this application. Figure 6A and Figure 6BAs shown, the memory system 2000a or 2000b includes at least one three-dimensional memory 2100 and a memory controller 2200.

[0060] The three-dimensional memory 2100 may include the structures described in any of the embodiments above, which will not be repeated here. The memory controller 2200 may control the three-dimensional memory 2100 via, for example, a channel (not shown), and the three-dimensional memory 2100 may perform operations based on the control of the memory controller 2200. Exemplarily, the three-dimensional memory 2100 may receive commands and addresses from the memory controller 2200 via, for example, a channel and access regions of the memory array structure responsive to the address. In other words, the three-dimensional memory 2100 may perform internal operations corresponding to commands on regions selected by addresses.

[0061] In some examples, the storage controller 2200 and one or more three-dimensional memories 2100 can be integrated into various types of storage devices; in other words, the memory systems 2000a and 2000b can be implemented and packaged into different types of final electronic products. Figure 6A In one example shown, the storage controller 2200 and a single three-dimensional memory 2100 may be integrated into a memory card-type memory system 2200a. The memory card may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a compact flash (CF) card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a universal flash memory card (UFS), etc. The memory card-type memory system 2200a may also include a memory card connector 2300a that couples it to a host (not shown).

[0062] In such Figure 6B In another example shown, a storage controller 2200 and multiple 3D memories 2100 may be integrated into a memory system 2000b formed by a solid-state drive (SSD). The SSD may also include an SSD connector 2300b that couples it to a host. In some embodiments, the storage capacity and / or operating speed of the SSD may be higher than that of a memory card.

[0063] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A three-dimensional memory, comprising: The storage array structure includes a first storage array structure and a second storage array structure disposed along a first direction; A bridging structure, connecting the first memory array structure and the second memory array structure along the first direction, includes multiple dielectric layers and multiple conductive layers stacked alternately. Multiple steps are arranged adjacent to the bridging structure in a second direction and are located at different heights. The second direction intersects with the first direction. Each step is connected to at least one of the first storage array structure and the second storage array structure through the bridging structure. as well as Multiple dummy channel structures, each of which passes through the bridging structure along the stacking direction of the bridging structure, and in a plane perpendicular to the stacking direction, the dummy channel structure is elliptical in shape.

2. The three-dimensional memory according to claim 1, wherein, In a plane perpendicular to the stacking direction, the maximum dimension of the shape of the dummy channel structure in the first direction is greater than its maximum dimension in the second direction.

3. The three-dimensional memory according to claim 1, wherein, On a plane perpendicular to the stacking direction, the ratio of the maximum dimension of the shape of the dummy channel structure in the first direction to its maximum dimension in the second direction is 1.2 to 1.

8.

4. The three-dimensional memory according to claim 1, wherein, The plurality of steps includes at least three pairs of steps arranged in the first direction, each pair of steps including two steps having an inclined orientation facing each other.

5. The three-dimensional memory according to claim 4, wherein, Each of the aforementioned step pairs includes a first step and a second step arranged opposite to each other, wherein: Along the first direction, the step height of the first step gradually increases, and the step height of the second step gradually decreases; or Along the first direction, the step height of the first step gradually decreases, while the step height of the second step gradually increases.

6. The three-dimensional memory according to claim 5, wherein, Both the first and second steps include multiple steps, and in the stacking direction, the height of the top step of the first step is higher than the height of the top step of the second step.

7. The three-dimensional memory according to claim 1, wherein, The three-dimensional memory also includes: A grid line slot structure, at least partially located in the bridging structure and extending continuously along the first direction, wherein the bridging structure includes a first bridging structure and a second bridging structure arranged in the second direction, and the grid line slot structure is located between the first bridging structure and the second bridging structure.

8. The three-dimensional memory according to claim 7, wherein: The first storage array includes a first sub-storage array and a second sub-storage array arranged in the second direction, and at least a portion of the gate slot structure extends along the first direction and is located between the first sub-storage array and the second sub-storage array; The second storage array includes a third sub-storage array and a fourth sub-storage array arranged in the second direction, and at least a portion of the gate slot structure extends along the first direction and is located between the third sub-storage array and the fourth sub-storage array; as well as The first bridging structure connects the first sub-storage array and the third sub-storage array, and the second bridging structure connects the second sub-storage array and the fourth sub-storage array.

9. The three-dimensional memory according to claim 8, further comprising: A first storage block and a second storage block are arranged in the second direction, wherein the first storage block includes a first sub-storage array, a third sub-storage array and a first bridging structure, and the second storage block includes a second sub-storage array, a fourth sub-storage array and a second bridging structure.

10. The three-dimensional memory according to claim 7, wherein: The plurality of virtual channel structures include a plurality of first virtual channel structures and a plurality of second virtual channel structures; The plurality of first dummy channel structures pass through the first bridging structure along the stacking direction and are arranged in rows along the first direction; as well as The plurality of second dummy channel structures pass through the second bridging structure along the stacking direction and are arranged in rows along the first direction.

11. The three-dimensional memory according to claim 10, wherein, Multiple first dummy channel structures are arranged in one or two rows between adjacent grid line slot structures and steps; multiple second dummy channel structures are arranged in one or two rows between adjacent grid line slot structures and steps.

12. A three-dimensional memory, comprising: The storage array structure includes a first storage array structure and a second storage array structure disposed along a first direction; A bridging structure, connecting the first memory array structure and the second memory array structure along the first direction, includes multiple dielectric layers and multiple conductive layers stacked alternately. Multiple dummy channel structures, each of which passes through the bridging structure along the stacking direction of the bridging structure, and in a plane perpendicular to the stacking direction, the maximum dimension of the shape of the dummy channel structure in the first direction is greater than its maximum dimension in the second direction, the second direction intersecting the first direction; as well as The grid line slot structure is at least partially located in the bridging structure and extends continuously along the first direction.

13. The three-dimensional memory according to claim 12, wherein, The bridging structure includes a first bridging structure and a second bridging structure arranged in the second direction, and the grid line slot structure is located between the first bridging structure and the second bridging structure.

14. The three-dimensional memory according to claim 13, further comprising: Multiple steps are arranged adjacent to the bridging structure in the second direction and are located at different heights. Each step is connected to at least one of the first storage array structure and the second storage array structure through the bridging structure.

15. The three-dimensional memory according to claim 12, wherein, On a plane perpendicular to the stacking direction, the ratio of the maximum dimension of the shape of the dummy channel structure in the first direction to its maximum dimension in the second direction is 1.2 to 1.

8.

16. The three-dimensional memory according to claim 12, wherein, On a plane perpendicular to the stacking direction, the shape of the dummy channel structure has a smooth profile.

17. The three-dimensional memory according to any one of claims 12 to 16, wherein, On a plane perpendicular to the stacking direction, the shape of the dummy channel structure is elliptical.

18. The three-dimensional memory according to claim 14, wherein, The plurality of steps includes at least three pairs of steps arranged in the first direction, each pair of steps including two steps having an inclined orientation facing each other.

19. The three-dimensional memory according to claim 18, wherein, Each of the aforementioned step pairs includes a first step and a second step arranged opposite to each other, wherein: Along the first direction, the step height of the first step gradually increases, and the step height of the second step gradually decreases; or Along the first direction, the step height of the first step gradually decreases, while the step height of the second step gradually increases.

20. The three-dimensional memory according to claim 19, wherein, Both the first and second steps include multiple steps, and in the stacking direction, the height of the top step of the first step is higher than the height of the top step of the second step.

21. The three-dimensional memory according to claim 14, wherein: The first storage array includes a first sub-storage array and a second sub-storage array arranged in the second direction, and at least a portion of the gate slot structure extends along the first direction and is located between the first sub-storage array and the second sub-storage array; The second storage array includes a third sub-storage array and a fourth sub-storage array arranged in the second direction, and at least a portion of the gate slot structure extends along the first direction and is located between the third sub-storage array and the fourth sub-storage array; as well as The first bridging structure connects the first sub-storage array and the third sub-storage array, and the second bridging structure connects the second sub-storage array and the fourth sub-storage array.

22. The three-dimensional memory according to claim 21, further comprising: A first storage block and a second storage block are arranged in the second direction, wherein the first storage block includes a first sub-storage array, a third sub-storage array and a first bridging structure, and the second storage block includes a second sub-storage array, a fourth sub-storage array and a second bridging structure.

23. The three-dimensional memory according to claim 14, wherein: The plurality of virtual channel structures include a plurality of first virtual channel structures and a plurality of second virtual channel structures; The plurality of first dummy channel structures pass through the first bridging structure along the stacking direction and are arranged in rows along the first direction; as well as The plurality of second dummy channel structures pass through the second bridging structure along the stacking direction and are arranged in rows along the first direction.

24. The three-dimensional memory according to claim 23, wherein, Multiple first dummy channel structures are arranged in one or two rows between adjacent grid line slot structures and steps; multiple second dummy channel structures are arranged in one or two rows between adjacent grid line slot structures and steps.

25. A memory system, comprising: The three-dimensional memory as described in any one of claims 1 to 24; as well as A storage controller, electrically connected to the three-dimensional memory, is used to control the three-dimensional memory.

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