Tunneling passivation battery structure

Abstract

The utility model discloses a tunneling passivation battery structure, which comprises a substrate, a first passivation layer, a tunneling silicon oxide layer and a doped polycrystalline silicon layer, and is characterized in that the first passivation layer is located at one side of the substrate, and the first passivation layer is a microcrystalline film layer; the tunneling silicon oxide layer is located on the side, away from the first passivation layer, of the substrate; the doped polycrystalline silicon layer is located on the side, away from the substrate, of the tunneling silicon oxide layer, the multi-layer microcrystalline film layer is adopted as a passivation layer of the tunneling passivation cell, light attenuation of the tunneling passivation cell is reduced, the conductivity and the absorption coefficient of the tunneling passivation cell are improved, the tunneling passivation cell can better conduct transverse transmission of front face current, and therefore the tunneling passivation cell can be used for improving the performance of the tunneling passivation cell. The power loss of transverse transmission is reduced, the loss after light penetrates through the substrate is reduced, and the light utilization rate can be greatly increased.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a tunnel passivation cell structure. Background Art

[0002] The front passivation film layer of the existing TOPCON (tunneling passivation cell) battery is an amorphous structure. The amorphous film layer has the characteristics of good passivation effect, but has the disadvantages of low conductivity, high photoinduced attenuation and low absorption coefficient. Especially when the front square resistance is getting higher and higher, the loss of the front current transmission in the laterally doped silicon is getting higher and higher. The loss of the two-dimensional lateral transmission on the front is one of the bottleneck problems of TOPCON battery efficiency. Utility Model Content

[0003] The present application provides a tunnel passivation cell structure to solve the problems of large lateral transmission power loss and low light utilization of TOPCON cells in the related art.

[0004] According to one aspect of the present application, a tunneling passivation battery structure is provided, comprising: a substrate; a first passivation layer, located on one side of the substrate, the first passivation layer being a microcrystalline film layer; a tunneling silicon oxide layer, located on the side of the substrate away from the first passivation layer; and a doped polysilicon layer, located on the side of the tunneling silicon oxide layer away from the substrate.

[0005] Optionally, the thickness of the first passivation layer is 48 nm to 100 nm.

[0006] Optionally, the number of layers of the first passivation layer is 4 to 7 layers.

[0007] Optionally, the first passivation layer includes a first sub-passivation layer, a second sub-passivation layer, a third sub-passivation layer, a fourth sub-passivation layer and a fifth sub-passivation layer, and the first sub-passivation layer, the second sub-passivation layer, the third sub-passivation layer, the fourth sub-passivation layer and the fifth sub-passivation layer are stacked along a first direction on the side of the first passivation layer away from the substrate, and the first direction is the direction of the tunneling silicon oxide layer pointing to the first passivation layer.

[0008] Optionally, the thickness of the first sub-passivation layer and the second sub-passivation layer are both 4nm-12nm, the thickness of the third sub-passivation layer and the fourth sub-passivation layer are both 15nm-25nm, and the thickness of the fifth sub-passivation layer is 10nm-25nm.

[0009] Optionally, the thickness of the second sub-passivation layer is consistent with the thickness of the first sub-passivation layer, and the thickness of the fourth sub-passivation layer is consistent with the thickness of the third sub-passivation layer.

[0010] Optionally, the refractive index of the first sub-passivation layer is 1.50-1.70, the refractive index of the second sub-passivation layer is 1.20-2.30, the refractive index of the third sub-passivation layer is 1.70-3.20, the refractive index of the fourth sub-passivation layer is 1.70-3.20, and the refractive index of the fifth sub-passivation layer is 1.20-2.30.

[0011] Optionally, the first sub-passivation layer is an aluminum microcrystalline film layer, the second sub-passivation layer, the third sub-passivation layer, the fourth sub-passivation layer are silicon microcrystalline film layers, and the fifth sub-passivation layer is a silicon microcrystalline film layer.

[0012] Optionally, the first sub-passivation layer is an aluminum oxide microcrystalline film layer, the second sub-passivation layer is a silicon oxide microcrystalline film layer, the third sub-passivation layer is a silicon nitride microcrystalline film layer, the fourth sub-passivation layer is a silicon oxynitride microcrystalline film layer, and the fifth sub-passivation layer is a silicon oxide microcrystalline film layer.

[0013] Optionally, the battery structure further includes at least one first electrode and at least one second electrode, the first electrode is located on a side of the first passivation layer away from the substrate, and the second electrode is located on a side of the tunneling silicon oxide layer away from the substrate.

[0014] Through the present application, a tunneling passivation cell structure is adopted, which includes a substrate, a first passivation layer, a tunneling silicon oxide layer and a doped polysilicon layer, wherein the first passivation layer is located on one side of the substrate, and the first passivation layer is a microcrystalline film layer; the tunneling silicon oxide layer is located on the side of the substrate away from the first passivation layer; the doped polysilicon layer is located on the side of the tunneling silicon oxide layer away from the substrate, wherein a plurality of microcrystalline film layers are used as the passivation layer of the tunneling passivation cell, which reduces the light attenuation of the tunneling passivation cell, improves the conductivity and absorption coefficient of the tunneling passivation cell, enables the tunneling passivation cell to better perform the lateral transmission of the front current, reduces the power loss of the lateral transmission, reduces the loss of light after passing through the substrate, and can greatly increase the utilization rate of light. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings constituting a part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0016] Figure 1 is a cross-sectional schematic diagram of a tunnel passivation battery structure provided according to an embodiment of the present application;

[0017] Figure 2 is a cross-sectional schematic diagram of another tunnel passivation battery structure provided according to an embodiment of the present application;

[0018] Figure 3 It is a cross-sectional schematic diagram of another tunnel passivation battery structure provided according to an embodiment of the present application.

[0019] The above drawings include the following reference numerals:

[0020] 10. substrate; 20. first passivation layer; 201. first sub-passivation layer; 202. second sub-passivation layer; 203. third sub-passivation layer; 204. fourth sub-passivation layer; 205. fifth sub-passivation layer; 30. tunneling silicon oxide layer; 40. doped polysilicon layer; 50. first electrode; 60. second electrode. DETAILED DESCRIPTION

[0021] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0022] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0023] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0024] According to an embodiment of the present application, a tunneling passivation battery structure is provided. Figure 1 FIG. 1 is a schematic cross-sectional view of a tunnel passivation battery structure according to an embodiment of the present application. Figure 1 As shown, the tunneling passivation battery structure includes: a substrate 10; a first passivation layer 20, located on one side of the substrate, the first passivation layer 20 is a microcrystalline film layer; a tunneling silicon oxide layer 30, located on the side of the substrate 10 away from the first passivation layer 20; and a doped polysilicon layer 40, located on the side of the tunneling silicon oxide layer 30 away from the substrate 10.

[0025] By setting a microcrystalline film layer on the front side of the above-mentioned tunneling passivation cell, it is possible to reduce the light attenuation of the tunneling passivation cell, improve the conductivity and absorption coefficient of the tunneling passivation cell, enable the tunneling passivation cell to better transmit the front current laterally, reduce the power loss of lateral transmission, reduce the loss of light after passing through the substrate, and greatly increase the utilization rate of light.

[0026] In the above optional implementation, if Figure 1 As shown, the tunneling passivation cell structure includes a substrate 10, a first passivation layer 20, a tunneling silicon oxide layer 30 and a doped polysilicon layer 40, wherein the first passivation layer 20 and the tunneling silicon oxide layer 30 are respectively located on both sides of the substrate 10, and the doped polysilicon layer 40 is located on the side of the tunneling silicon oxide layer 30 away from the substrate 10, wherein the first passivation layer 20 is a microcrystalline film layer, so that the tunneling passivation cell has low attenuation, high conductivity and absorption coefficient, so that the tunneling passivation cell can better perform lateral transmission of front current, reduce the power loss of lateral transmission, reduce the loss of light after passing through the substrate 10, and can greatly increase the utilization rate of light.

[0027] In the above optional implementation, if Figure 1 As shown, the material of the substrate 10 can be P-type silicon or N-type silicon. Those skilled in the art can reasonably select the material of the substrate according to actual conditions, and this application does not make any specific limitation.

[0028] In some optional embodiments, such as Figure 1 As shown, the thickness of the first passivation layer 20 is 48 nm to 100 nm.

[0029] In the above optional implementation, if Figure 1 As shown, the first passivation layer 20 is located on the side of the substrate 10 away from the tunneling silicon oxide layer 30, which is the front of the tunneling passivation battery structure. The light enters the first passivation layer 20 from the side surface of the first passivation layer 20 away from the substrate 10, is emitted through the side surface of the first passivation layer 20 close to the substrate 10, enters the substrate 10, and then passes through the substrate 10 and is emitted from the tunneling silicon oxide layer 30 and the doped polysilicon layer 40 in sequence. In this process, the loss of light is relatively large. The first passivation layer 20, which is a microcrystalline film layer with a thickness of 48nm to 100nm, reduces the photo-induced attenuation and improves the absorption coefficient, so that the loss of light after passing through the substrate 10 is reduced, and the utilization rate of light is greatly increased. The first passivation layer 20 of the microcrystalline film layer has a high conductivity, which is conducive to the lateral transmission of the front current of the tunneling passivation battery and reduces the power loss of the lateral transmission.

[0030] In some optional embodiments, such as Figure 1 As shown, the number of layers of the first passivation layer 20 is 4 to 7 layers.

[0031] In the above optional implementation, if Figure 1As shown, if the number of the first passivation layer 20 is too many, it is likely that the overall passivation layer of the tunnel passivation cell will be very thick, so that the energy of the light penetrating the substrate 10 is reduced, and even the light cannot pass through the substrate 10. If the number of the first passivation layer 20 is too few, it will lead to low conversion efficiency of the light, affecting the light conversion efficiency of the tunnel passivation cell.

[0032] In the above optional implementation, if Figure 1 As shown, those skilled in the art can reasonably select the number of layers of the first passivation layer 20 according to actual conditions, and this application does not make any specific limitation.

[0033] In some optional embodiments, such as Figure 2 As shown, the first passivation layer 20 includes a first sub-passivation layer 201, a second sub-passivation layer 202, a third sub-passivation layer 203, a fourth sub-passivation layer 204 and a fifth sub-passivation layer 205. The first sub-passivation layer 201, the second sub-passivation layer 202, the third sub-passivation layer 203, the fourth sub-passivation layer 204 and the fifth sub-passivation layer 205 are stacked along a first direction X on a side of the first passivation layer 20 away from the substrate 10, and the first direction X is a direction from the tunneling silicon oxide layer 30 to the first passivation layer 20.

[0034] In the above optional implementation, if Figure 2 As shown, the first passivation layer 20 has 5 layers, wherein the first passivation layer 20 specifically includes a first sub-passivation layer 201, a second sub-passivation layer 202, a third sub-passivation layer 203, a fourth sub-passivation layer 204 and a fifth sub-passivation layer 205, the first sub-passivation layer 201 is located on the side of the substrate 10 away from the doped polysilicon layer 40, the second sub-passivation layer 202 is located on the side of the first sub-passivation layer 201 away from the substrate 10, the third sub-passivation layer 203 is located on the side of the second sub-passivation layer 202 away from the first sub-passivation layer 201, the fourth sub-passivation layer 204 is located on the side of the third sub-passivation layer 203 away from the second sub-passivation layer 202, and the fifth sub-passivation layer 205 is located on the side of the fourth sub-passivation layer 204 away from the second sub-passivation layer 202, that is, the first The sub-passivation layer 201, the second sub-passivation layer 202, the third sub-passivation layer 203, the fourth sub-passivation layer 204 and the fifth sub-passivation layer 205 are stacked along the direction of the tunneling silicon oxide layer 30 pointing to the first passivation layer 20. The above-mentioned first passivation layer 20 is a multi-layer microcrystalline film layer. The multi-layer microcrystalline film layer can increase the reflection and refraction of light, improve the light absorption capacity, thereby improving the photoelectric conversion efficiency of the solar cell, reduce the reflection loss of light, and improve the utilization rate of light, thereby increasing the output power of the solar cell, and can adjust the transmission and reflection of light of different wavelengths, so that the solar cell can absorb a wider spectrum range, improve the photoelectric conversion efficiency, reduce the erosion and damage of the external environment to the surface of the solar cell, and extend the service life of the battery.

[0035] In some optional embodiments, such as Figure 2 As shown, the thickness of the first sub-passivation layer 201 and the second sub-passivation layer 202 are both 4nm-12nm, the thickness of the third sub-passivation layer 203 and the fourth sub-passivation layer 204 are both 15nm-25nm, and the thickness of the fifth sub-passivation layer 205 is 10nm-25nm.

[0036] In the above optional implementation, if Figure 2 As shown, the thickness of the first sub-passivation layer 201 and the second sub-passivation layer 202 is relatively smaller than that of the third sub-passivation layer 203 and the fourth sub-passivation layer 204. The first sub-passivation layer 201 and the second sub-passivation layer 202 are located on the side of the tunneling passivation cell close to the substrate 10. The thickness within the range of 4nm to 12nm can make the light conversion efficiency better, and does not affect the color of the film wrapped on the surface of the tunneling passivation cell, which can play a role in protecting and enhancing the light absorption effect.

[0037] In some optional embodiments, such as Figure 2 As shown, the thickness of the second sub-passivation layer 202 is consistent with the thickness of the first sub-passivation layer 201 , and the thickness of the fourth sub-passivation layer 204 is consistent with the thickness of the third sub-passivation layer 203 .

[0038] In the above optional implementation, if Figure 2 As shown, under the condition that the thickness range of the second sub-passivation layer 202 and the first sub-passivation layer 201 is met, the thickness of the second sub-passivation layer 202 and the first sub-passivation layer 201 are made consistent, and the thickness of the third sub-passivation layer 203 and the fourth sub-passivation layer 204 are made consistent, which can make the battery manufacturing process simpler.

[0039] In some optional embodiments, such as Figure 2 As shown, the refractive index of the first sub-passivation layer 201 is 1.50-1.70, the refractive index of the second sub-passivation layer 202 is 1.20-2.30, the refractive index of the third sub-passivation layer 203 is 1.70-3.20, the refractive index of the fourth sub-passivation layer 204 is 1.70-3.20, and the refractive index of the fifth sub-passivation layer 205 is 1.20-2.30.

[0040] In the above optional implementation, if Figure 2As shown, the first sub-passivation layer 201, the second sub-passivation layer 202, the third sub-passivation layer 203, the fourth sub-passivation layer 204 and the fifth sub-passivation layer 205 in the tunnel passivation battery need to have a moderate refractive index. When the first sub-passivation layer 201, the second sub-passivation layer 202, the third sub-passivation layer 203, the fourth sub-passivation layer 204 and the fifth sub-passivation layer 205 are in the above-mentioned refractive index range, the above-mentioned passivation layer can have a higher refractive index, increase the reflection and refraction of light in the above-mentioned passivation layer, thereby improving the light absorption efficiency, and the refractive index of the above-mentioned passivation layer will not be too high, resulting in part of the light being reflected multiple times inside the above-mentioned passivation layer and unable to pass through the substrate 10, thereby reducing the utilization rate of light.

[0041] In some optional embodiments, such as Figure 2 As shown, the first sub-passivation layer 201 is an aluminum microcrystalline film layer, and the second sub-passivation layer 202, the third sub-passivation layer 203, the fourth sub-passivation layer 204 and the fifth sub-passivation layer 205 are all silicon microcrystalline film layers.

[0042] In the above optional implementation, if Figure 2 As shown, the first sub-passivation layer 201 is an aluminum microcrystalline film layer. The passivation layer of the aluminum microcrystalline film layer can prevent aluminum from chemically reacting with the electrolyte, thereby slowing down the self-discharge rate of the battery and extending the life of the battery. The second sub-passivation layer 202, the third sub-passivation layer 203, the fourth sub-passivation layer 204 and the fifth sub-passivation layer 205 are all silicon microcrystalline film layers. The passivation layer of the silicon microcrystalline film layer can prevent silicon from chemically reacting with the electrolyte, while improving the electrochemical stability of the silicon material, thereby enhancing the cycle performance and charge and discharge efficiency of the battery, and improving the performance of the tunnel passivation battery. At the same time, the microcrystalline film layer serves as the passivation layer of the tunnel passivation battery, which reduces the light attenuation of the tunnel passivation battery, improves the conductivity and absorption coefficient of the tunnel passivation battery, enables the tunnel passivation battery to better perform the lateral transmission of the front current, reduces the power loss of the lateral transmission, reduces the loss of light after passing through the substrate, and can greatly increase the utilization rate of light.

[0043] For example, the first sub-passivation layer 201 may be an aluminum oxide microcrystalline film layer, the second sub-passivation layer 202 may be a silicon oxide microcrystalline film layer, the third sub-passivation layer 203 may be a silicon nitride microcrystalline film layer, the fourth sub-passivation layer 204 may be a silicon oxynitride microcrystalline film layer, and the fifth sub-passivation layer 205 may be a silicon oxide microcrystalline film layer.

[0044] In some optional embodiments, such as Figure 3 As shown, the battery structure further includes at least one first electrode 50 and at least one second electrode 60 . The first electrode 50 is located on a side of the first passivation layer 20 away from the substrate 10 , and the second electrode 60 is located on a side of the doped polysilicon layer 40 away from the substrate 10 .

[0045] In the above optional implementation, if Figure 3 As shown, the tunnel passivation battery also has a first electrode 50 and a second electrode 60. Figure 3 Two first electrodes 50 and two second electrodes 60 are shown. The present application does not specifically limit the number of the first electrodes 50 and the second electrodes 60. The first passivation layer 20 includes a first sub-passivation layer 201, a second sub-passivation layer 202, a third sub-passivation layer 203, a fourth sub-passivation layer 204 and a fifth sub-passivation layer 205. The first passivation layer 20 is located on the side of the tunneling silicon oxide layer 30 away from the substrate 10, and the first electrode 50 is located on the side of the fifth sub-passivation layer 205 away from the fourth sub-passivation layer 204.

[0046] In the above optional implementation, if Figure 3 As shown, the first electrode 50 and the second electrode 60 control the discharge and charge process of the battery by adjusting the gate voltage of the tunnel passivation battery, thereby realizing regulation of the charge and discharge performance of the battery, making the performance of the battery more stable and reliable. The first electrode 50 and the second electrode 60 can effectively improve the energy density and cycle life of the tunnel passivation battery, and can also reduce the internal resistance of the tunnel passivation battery and improve the charge and discharge efficiency of the battery.

[0047] In the above optional implementation, if Figure 3 As shown, the material of the first electrode 50 and the second electrode 60 can be any one or more of silver, molybdenum, platinum, copper and aluminum. Those skilled in the art can reasonably select the material of the first electrode and the second electrode according to actual conditions, and this application does not make specific limitations.

[0048] In the above optional implementation, if Figure 2As shown, each passivation layer in the first passivation layer 20 is prepared from an amorphous film layer, wherein the process steps for preparing the first sub-passivation layer 201 may include: introducing 8000SCCM of N2O, 6000SCCM of C3H9Al and 30000SCCM of H2, reacting for 70S at a temperature of 400°C, a power of 6800W, a pressure of 1250mTorr, and a duty cycle of 1%-5% to obtain the first sub-passivation layer 201 of the microcrystalline film layer, wherein the duty cycle selected when preparing the first sub-passivation layer 201 is 1.25%. The process steps for preparing the second sub-passivation layer 202 may include: introducing 8000 SCCM of N2O, 900 SCCM of SiH4 and 40000 SCCM of H2, reacting for 90 seconds at a temperature of 400°C, a power of 13000 W, a pressure of 1200 mTorr, and a duty cycle of 1%-5% to obtain the second sub-passivation layer 202 of the microcrystalline film layer, wherein the duty cycle selected when preparing the second sub-passivation layer 202 is 1.35%. The process steps for preparing the third sub-passivation layer 203 may include: introducing 18000SCCM of N2O, 1600SCCM of SiH4 and 40000SCCM of H2, reacting for 120S at a temperature of 400°C, a power of 16000W, a pressure of 1800mTorr, and a duty cycle of 1%-5% to obtain the third sub-passivation layer 203 of the microcrystalline film layer, wherein the duty cycle selected when preparing the third sub-passivation layer 203 is 1.4%. The process steps for preparing the third sub-passivation layer 203 may include: introducing 8000SCCM of N2O, 700SCCM of SiH4 and 14000SCCM of H2, reacting for 240S at a temperature of 400°C, a power of 13000W, a pressure of 1800mTorr, and a duty cycle of 1%-5% to obtain a fourth sub-passivation layer 204 of a microcrystalline film layer, wherein when preparing the third sub-passivation layer 203, the selected duty cycle is 1.25%. The process steps for preparing the fifth sub-passivation layer 205 may include: introducing 7000SCCM of N2O, 900SCCM of SiH4 and 30000SCCM of H2, reacting for 170S at a temperature of 400°C, a power of 13000W, a pressure of 900mTorr, and a duty cycle of 1%-5% to obtain the fifth sub-passivation layer 205 of the microcrystalline film layer, wherein the duty cycle selected when preparing the fifth sub-passivation layer 205 is 1.25%.

[0049] The tunnel passivation battery structure in the present application will be further described below in conjunction with examples and comparative examples.

[0050] Example 1

[0051] This embodiment provides a tunnel passivation battery structure including:

[0052] A substrate, a first passivation layer, a tunneling silicon oxide layer and a doped polysilicon layer, wherein the first passivation layer is located on one side of the substrate, and the first passivation layer is a microcrystalline film layer; the tunneling silicon oxide layer is located on the side of the substrate away from the first passivation layer; the doped polysilicon layer is located on the side of the tunneling silicon oxide layer away from the substrate, wherein the first passivation layer includes a first sub-passivation layer, a second sub-passivation layer, a third sub-passivation layer, a fourth sub-passivation layer and a fifth sub-passivation layer, and the first sub-passivation layer, the second sub-passivation layer, the third sub-passivation layer, the fourth sub-passivation layer and the fifth sub-passivation layer are stacked along a first direction on the side of the first passivation layer away from the substrate On one side, the first direction is the direction of the tunneling silicon oxide layer pointing to the first passivation layer, and the above passivation layers are all microcrystalline film layers, wherein the first sub-passivation layer is an aluminum oxide microcrystalline film layer, the second sub-passivation layer is a silicon oxide microcrystalline film layer, the third sub-passivation layer is a silicon nitride microcrystalline film layer, the fourth sub-passivation layer is a silicon oxynitride microcrystalline film layer, and the fifth sub-passivation layer is a silicon oxide microcrystalline film layer. The thickness of the first sub-passivation layer and the second sub-passivation layer is 4nm to 12nm, the thickness of the third sub-passivation layer and the fourth sub-passivation layer is 15nm to 25nm, and the thickness of the fifth sub-passivation layer is 10nm to 25nm. Specific experimental data are shown in Table 1.

[0053] Comparative Example 1

[0054] This comparative example provides a tunnel passivation battery structure comprising:

[0055] A substrate, an amorphous passivation layer, a tunneling silicon oxide layer and a doped polysilicon layer, wherein the amorphous passivation layer is located on one side of the substrate, and the amorphous passivation layer is an amorphous film layer; the tunneling silicon oxide layer is located on the side of the substrate away from the amorphous passivation layer; the doped polysilicon layer is located on the side of the tunneling silicon oxide layer away from the substrate, wherein the amorphous passivation layer includes a first sub-amorphous passivation layer, a second sub-amorphous passivation layer, a third sub-amorphous passivation layer, a fourth sub-amorphous passivation layer and a fifth sub-amorphous passivation layer, and the first sub-amorphous passivation layer, the second sub-amorphous passivation layer, the third sub-amorphous passivation layer, the fourth sub-amorphous passivation layer and the fifth sub-amorphous passivation layer are stacked along a first direction on the side of the amorphous passivation layer away from the substrate. On one side, the first direction is the direction of the tunneling silicon oxide layer pointing to the amorphous passivation layer, and the above passivation layers are all amorphous film layers, wherein the first sub-amorphous passivation layer is an aluminum oxide amorphous film layer, the second sub-amorphous passivation layer is a silicon oxide amorphous film layer, the third sub-amorphous passivation layer is a silicon nitride amorphous film layer, the fourth sub-amorphous passivation layer is a silicon oxynitride amorphous film layer, and the fifth sub-amorphous passivation layer is a silicon oxide amorphous film layer. The thickness of the first sub-amorphous passivation layer and the second sub-amorphous passivation layer is 4nm to 12nm, the thickness of the third sub-amorphous passivation layer and the fourth sub-amorphous passivation layer is 15nm to 25nm, and the thickness of the fifth sub-amorphous passivation layer is 10nm to 25nm. Specific experimental data are shown in Table 1.

[0056] Table 1

[0057]

[0058] It can be seen from the above data that by adopting the solution of Example 1 of the present application, the short-circuit current, fill factor and conversion efficiency of the front and back sides of the tunnel passivated solar cell are improved to a certain extent, and the series resistance is reduced to a certain extent, thereby achieving the purpose of reducing the light attenuation of the tunnel passivated battery, improving the conductivity and absorption coefficient of the tunnel passivated battery, enabling the tunnel passivated battery to better perform the lateral transmission of the front current, reducing the power loss of the lateral transmission, and reducing the loss of light after passing through the substrate, which can greatly increase the utilization rate of light.

[0059] It should be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of further restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0060] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A tunnel passivation battery structure, characterized in that: include: substrate; A first passivation layer, located on one side of the substrate, wherein the first passivation layer is a microcrystalline film layer; a tunneling silicon oxide layer, located on a side of the substrate away from the first passivation layer; The doped polysilicon layer is located on a side of the tunneling silicon oxide layer away from the substrate.

2. The battery structure according to claim 1, characterized in that: The thickness of the first passivation layer is 48 nm to 100 nm.

3. The battery structure according to claim 1, characterized in that: The number of layers of the first passivation layer is 4 to 7 layers.

4. The battery structure according to claim 1, characterized in that: The first passivation layer includes a first sub-passivation layer, a second sub-passivation layer, a third sub-passivation layer, a fourth sub-passivation layer and a fifth sub-passivation layer, and the first sub-passivation layer, the second sub-passivation layer, the third sub-passivation layer, the fourth sub-passivation layer and the fifth sub-passivation layer are stacked along a first direction on a side of the first passivation layer away from the substrate, and the first direction is the direction from the tunneling silicon oxide layer to the first passivation layer.

5. The battery structure according to claim 4, characterized in that: The thickness of the first sub-passivation layer and the second sub-passivation layer are both 4nm-12nm, the thickness of the third sub-passivation layer and the fourth sub-passivation layer are both 15nm-25nm, and the thickness of the fifth sub-passivation layer is 10nm-25nm.

6. The battery structure according to claim 4, characterized in that: The thickness of the second sub-passivation layer is consistent with the thickness of the first sub-passivation layer, and the thickness of the fourth sub-passivation layer is consistent with the thickness of the third sub-passivation layer.

7. The battery structure according to claim 4, characterized in that: The refractive index of the first sub-passivation layer is 1.50-1.70, the refractive index of the second sub-passivation layer is 1.20-2.30, the refractive index of the third sub-passivation layer is 1.70-3.20, the refractive index of the fourth sub-passivation layer is 1.70-3.20, and the refractive index of the fifth sub-passivation layer is 1.20-2.

30.

8. The battery structure according to claim 4, characterized in that: The first sub-passivation layer is an aluminum microcrystalline film layer, and the second sub-passivation layer, the third sub-passivation layer, the fourth sub-passivation layer and the fifth sub-passivation layer are all silicon microcrystalline film layers.

9. The battery structure according to claim 8, characterized in that: The first sub-passivation layer is an aluminum oxide microcrystalline film layer, the second sub-passivation layer is a silicon oxide microcrystalline film layer, the third sub-passivation layer is a silicon nitride microcrystalline film layer, the fourth sub-passivation layer is a silicon oxynitride microcrystalline film layer, and the fifth sub-passivation layer is a silicon oxide microcrystalline film layer.

10. The battery structure according to any one of claims 1 to 9, characterized in that: The battery structure further includes at least one first electrode and at least one second electrode. The first electrode is located on a side of the first passivation layer away from the substrate, and the second electrode is located on a side of the tunneling silicon oxide layer away from the substrate.

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