Universal single-channel digital anti-interference baseband circuit

Abstract

The utility model discloses a universal single-channel digital anti-interference baseband circuit. Comprising a power supply protection circuit, a DC / DC power supply conversion circuit, a power supply current detection circuit, a temperature detection circuit, an FPGA baseband signal anti-interference processing circuit, an ARM A8 microprocessor unit circuit, an A / D analog-to-digital conversion circuit, a D / A digital-to-analog conversion circuit, a clock signal distribution circuit, an Ethernet data (IP) Switch switching circuit, a photoelectric conversion circuit, a storage circuit, an interface circuit and a synchronous Ethernet circuit. According to the utility model, zero intermediate frequency analog signal transmission can be realized, the fault tolerance performance of phase noise and phase jump can be improved through digital equalization, the simplified design of the radio frequency unit is better improved, the parameter requirements of some devices are reduced, the material cost is also reduced, and the manufacturability of the radio frequency unit is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of wireless communication, in particular to a universal single-channel digital anti-interference baseband circuit. Background Art

[0002] Microwave transmission equipment is a point-to-point device that uses high-frequency radio signals to transmit data. Traditional split-type microwave equipment generally uses a transmitting intermediate frequency of 350MHz and a receiving intermediate frequency of 140MHz. In order to ensure sufficient isolation between the transmitting and receiving intermediate frequencies, the maximum bandwidth can only support 56MHz. At the same time, multiple frequency conversions, filtering and amplification are required to reach the required microwave frequency. The RF circuit is relatively complex. In addition, traditional split-type microwave equipment also has strict requirements on phase noise and frequency deviation.

[0003] Based on the above points, we propose a universal single-channel digital anti-interference baseband circuit that can solve these problems. Utility Model Content

[0004] The purpose of the utility model is to provide a universal single-channel digital anti-interference baseband circuit to solve the problems raised in the above background technology.

[0005] To achieve the above-mentioned purpose, the utility model provides the following technical solutions: a universal single-channel digital anti-interference baseband circuit, including a power protection circuit, a DC / DC power conversion circuit, a power current detection circuit, a temperature detection circuit, an FPGA baseband signal anti-interference processing circuit, an ARM A8 microprocessor unit circuit, an A / D analog-to-digital conversion circuit, a D / A digital-to-analog conversion circuit, a clock signal distribution circuit, an Ethernet data (IP) Switch switching circuit, a photoelectric conversion circuit, a storage circuit, an interface circuit and a synchronous Ethernet circuit;

[0006] The power protection circuit is connected to the DC / DC power conversion circuit; the DC / DC power conversion circuit is respectively connected to the FPGA baseband signal anti-interference processing circuit, the ARM A8 microprocessor unit circuit, the A / D analog-to-digital conversion circuit, the D / A digital-to-analog conversion circuit, the clock signal distribution circuit, the Ethernet data (IP) Switch switching circuit, the photoelectric conversion circuit, the storage circuit, the power current detection circuit, the temperature detection circuit, the synchronous Ethernet circuit and the interface circuit; the FPGA baseband signal anti-interference processing circuit is respectively connected to the A / D analog-to-digital conversion circuit, the D / A digital-to-analog conversion circuit, the clock signal distribution circuit, the ARM A8 microprocessor unit circuit, and the Ethernet data (IP) Switch switching circuit; the clock signal distribution circuit is connected to the A / D analog-to-digital conversion circuit, the D / A digital-to-analog conversion circuit, the Ethernet data (IP) Switch switching circuit and the FPGA baseband signal anti-interference processing circuit; the ARM The A8 microprocessor unit circuit is respectively connected to the FPGA baseband signal anti-interference processing circuit, the power supply current detection circuit, the temperature detection circuit, the storage circuit and the Ethernet data (IP) Switch switching circuit; the Ethernet data (IP) Switch switching circuit is connected to the FPGA baseband signal anti-interference processing circuit, the ARM A8 microprocessor unit circuit and the photoelectric conversion circuit; the photoelectric conversion circuit is connected to the Ethernet data (IP) Switch switching circuit, the FPGA baseband signal anti-interference processing circuit and the interface circuit.

[0007] The power protection circuit uses an air discharge tube to achieve primary surge protection with a DC overvoltage of 90V and a pulse discharge current of 5KA; then a TVS tube is used to achieve secondary surge protection with a peak pulse power consumption of at least 3000W; finally, a Schottky diode is used to achieve anti-reverse plug-in protection with a surge peak reverse voltage of 100V.

[0008] The power protection circuit protects the -36V to -75V DC voltage input through the MCX socket against static electricity, surge and reverse insertion, and then converts it into a +12V voltage through the DC / DC power module. The +12V voltage is then converted into six voltages through the DC / DC power chip, namely +5V, +1.2V, +1.8V, +3.3V, +1.0V and +1.1V.

[0009] The power supply current detection circuit detects the +12V voltage after the input power is converted, and sends the detected signal to the ADC interface of the ARM A8 microprocessor unit circuit for processing to determine the working power consumption state of the digital anti-interference baseband circuit.

[0010] The temperature detection circuit detects the working temperature of the board and sends the detected signal to the ADC interface of the ARMA8 microprocessor unit circuit for processing to determine the working temperature status of the digital anti-interference baseband circuit. The working temperature of the digital anti-interference baseband circuit can be viewed in real time through the network management software.

[0011] The core of the ARM A8 microprocessor circuit is TI's AM3352 (taking this as an example but not limited to this model). This chip implements parameter configuration of the RF unit module through the SPI interface; analyzes and processes the power supply current detection signal and the temperature detection signal through the ADC interface; uses the PS mode to load the program for the FPGA baseband signal anti-interference processing circuit through the 8-bit parallel interface; downloads and upgrades the program online through the MMC interface; and implements out-of-band network management functions through the MII interface.

[0012] The core of the storage circuit mainly includes two chips, NANDFLASH and SDRAM. NANDFLASH has a capacity of 2Gb and is connected to the ARM A8 microprocessor circuit and the FPGA baseband signal anti-interference processing circuit through an 8-bit data line. It mainly stores the FPGA baseband signal anti-interference processing circuit program, the ARM A8 microprocessor circuit application program and the out-of-band network management program; SDRAM is DDR2 with a capacity of 2Gbit. It is connected to the ARM A8 microprocessor circuit through a 16-bit data line, a 14-bit address line and other control signals. It mainly stores the running data of the ARM A8 microprocessor circuit application program and the network management program.

[0013] The interface circuit mainly includes microwave intermediate frequency interface RX / TX, RS232 to USB level interface 1, RS232 to USB level interface 2, MMC interface and 1.25G SFP optical interface. The microwave intermediate frequency interface RX is connected to the A / D analog-to-digital conversion circuit through the RX I / Q signal, the microwave intermediate frequency interface TX is connected to the D / A digital-to-analog conversion circuit through the TX I / Q signal, and the microwave intermediate frequency interface RX is connected to the ARM A8 microprocessor circuit through the SPI signal; RS232 to USB level interface 1 is used for debugging and online program upgrade of the ARM A8 microprocessor circuit; RS232 to USB level interface 2 is used for FPGA baseband signal anti-interference processing circuit GUIDebug; MMC interface is used for program download and upgrade of the ARM A8 microprocessor circuit; 1.25G SFP optical interface is used for transmitting 1.25G optical fiber signals and network management.

[0014] The clock signal distribution circuit includes TCXO, VCXO, Crystal, clock fan-out buffer and clock generator, among which TCXO is a 3.3V active crystal oscillator, with a sine wave output of 25MHz and a frequency stability of ±2PPM. TCXO provides input clock for the clock fan-out buffer; the maximum output frequency of the clock fan-out buffer is 350MHz, with a maximum of 4 LVCMOS outputs, of which a 25MHz clock output is given to the FPGA baseband signal anti-interference processing circuit, a 25MHz clock output is given to the Ethernet data (IP) Switch switching circuit, and a 25MHz clock output is given to the clock generator; the maximum output frequency of the clock generator is 1.8GHz, with a maximum of 4 LVPECL outputs and 4 LVDS outputs, of which a 200MHz LVPECL output is given to the D / A digital-to-analog conversion circuit, a 200M LVDS output is given to the A / D analog-to-digital conversion circuit, and a 100M LVDS output is given to the FPGA baseband signal anti-interference processing circuit; VCXO is a 3.3V active crystal oscillator, 25MHz LVCMOS output, frequency stability ±30PPM, one 25MHz output to the FPGA baseband signal anti-interference processing circuit as a reference clock, one 25MHz output to the photoelectric conversion circuit as a working clock; Crystal1 is a random crystal oscillator, 24MHz output, frequency stability ±20PPM, Crystal1 provides the working clock for the ARM A8 microprocessor unit circuit; Crystal2 is a random crystal oscillator, 32.768KHz output, frequency stability ±20PPM, Crystal2 provides the RTC clock for the ARM A8 microprocessor unit circuit.

[0015] The core of the A / D analog-to-digital conversion circuit is the ADC chip, which supports dual 11-bit, 200MSPS, parallel LVDS / CMOS output, and 1.8V operating voltage. Among them, 11 LVDS outputs are sent to the FPGA baseband signal anti-interference processing circuit, and 2 I / Q signals are connected to the microwave intermediate frequency interface RX through the filtering circuit.

[0016] The core of the D / A digital-to-analog conversion circuit is the DAC chip, which supports dual-channel 12-bit, 500MSPS, parallel LVDS input, and 1.8V and 3.3V operating voltages. Among them, 12 LVDS data inputs are provided by the FPGA baseband signal anti-interference processing circuit, and 2 differential scalable signals are connected to the microwave intermediate frequency interface TX through the filtering circuit.

[0017] The core of the Ethernet data (IP) Switch switching circuit is the Switch chip, which supports 7 10 / 100 / 1000Mbps ports, 1 SGMII / Serdes interface, and 3 GMII / RGMII / MIIto the MAC. One SGMII interface is connected to the photoelectric conversion circuit; one RGMII interface is connected to the FPGA baseband signal anti-interference processing circuit; and one MII interface is connected to the ARMA8 microprocessor unit circuit.

[0018] The core of the photoelectric conversion circuit is the PHY chip, which supports 4 10 / 100 / 1000BASE-T PHY interfaces, 2 Serial MAC (SerDes) interfaces, 2 MDISerDes interfaces, and 2 recovered clock outputs for synchronous Ethernet. One MDISerDes interface is connected to the 1.25G SFP optical interface; one Serial MAC (SerDes) interface is connected to the Ethernet data (IP) Switch switching circuit; and one recovered clock of synchronous Ethernet is connected to the FPGA baseband signal anti-interference processing circuit.

[0019] The synchronous Ethernet circuit mainly consists of the PHY of the optoelectronic conversion circuit that recovers the SYNC_E clock and sends it to the FPGA of the FPGA baseband signal anti-interference processing circuit. The FPGA modulates the recovered clock onto the data and sends it to the D / A digital-to-analog conversion circuit, which is then sent to the TX of the intermediate frequency interface after digital-to-analog conversion. The RX of the intermediate frequency interface sends the analog data to the A / D analog-to-digital conversion circuit, which is then sent to the FPGA after analog-to-digital conversion. The FPGA demodulates the data to recover the SYNC_E clock and compares it with the reference clock of the FPGA. It then calibrates the output clock of the VCXO by giving the control signal to the VCXO to complete the synchronous Ethernet.

[0020] The FPGA baseband signal anti-interference processing circuit is the core part of the utility model. It mainly modulates the data sent from the Ethernet data (IP) Switch switching circuit through the RGMII interface and sends it to the D / A digital-to-analog conversion circuit. After the digital-to-analog conversion, the analog zero intermediate frequency signal is sent to the radio frequency unit through the TX of the intermediate frequency interface; the analog zero intermediate frequency signal from the radio frequency unit is sent to the A / D analog-to-digital conversion circuit through the RX of the intermediate frequency interface, and the data is sent to the FPGA after the analog-to-digital conversion. The FPGA performs anti-interference demodulation processing on the analog zero intermediate frequency signal collected by the A / D, and the demodulated signal is sent to the Ethernet data (IP) Switch switching circuit through the RGMII interface. The Ethernet data (IP) Switch switching circuit then forwards it downstream to the photoelectric conversion circuit, and finally sends it out through the 1.25G SFP optical interface. The entire data link can transmit a maximum data capacity of 900Mbps.

[0021] Compared with the prior art, the beneficial effects of the utility model are:

[0022] 1. The utility model sets a maximum bandwidth of 112MHz through network management, which meets the bandwidth requirements of different standards (ETSI 3.5 / 7 / 14 / 28 / 56 / 112MHz, ANSI 20 / 30 / 40 / 80MHz), and provides users with a more flexible transmission mode in various application environments;

[0023] 2. The utility model sets a variety of modulation and demodulation coding modes through network management, supports QPSK, QAM8, QAM16, QAM32, QAM64, QAM128, QAM256, QAM512 and QAM1024, and meets the needs of customers in various application environments;

[0024] 3. The network management of the utility model can realize real-time online management and online program upgrade, which is easy to manage and maintain;

[0025] 4. The utility model realizes zero intermediate frequency analog signal transmission and improves the fault tolerance performance of phase noise and phase jump through digital equalization, which can improve the simplified design of the radio frequency unit, reduce the parameter requirements of some devices, and also reduce the material cost and improve the manufacturability of the radio frequency unit.

[0026] 5. The single-channel digital anti-interference baseband circuit of the utility model meets the requirements of radio frequency units of different frequency bands in terms of power supply circuit design, anti-interference software and hardware requirement design, and real-time processing of large amounts of data, thereby achieving universal design.

[0027] This circuit can realize zero intermediate frequency analog signal transmission, and can improve the fault tolerance performance of phase noise and phase jump through digital equalization, better improve the simplified design of the RF unit, reduce the parameter requirements of some devices, and also reduce the material cost and improve the manufacturability of the RF unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a circuit connection schematic diagram of a single-channel digital anti-interference baseband circuit unit of the utility model;

[0029] Figure 2 It is a schematic diagram of synchronous Ethernet connection of a single-channel digital anti-interference baseband circuit unit of the utility model;

[0030] Figure 3 The utility model is a schematic diagram of the network management configuration of a single-channel digital anti-interference baseband circuit unit. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0032] See also Figure 1-3 The utility model provides a technical solution: a universal single-channel digital anti-interference baseband circuit, including a power protection circuit, a DC / DC power conversion circuit, a power current detection circuit, a temperature detection circuit, an FPGA baseband signal anti-interference processing circuit, an ARM A8 microprocessor unit circuit, an A / D analog-to-digital conversion circuit, a D / A digital-to-analog conversion circuit, a clock signal distribution circuit, an Ethernet data (IP) Switch switching circuit, a photoelectric conversion circuit, a storage circuit, an interface circuit and a synchronous Ethernet circuit;

[0033] The power protection circuit is connected to the DC / DC power conversion circuit; the DC / DC power conversion circuit is respectively connected to the FPGA baseband signal anti-interference processing circuit, the ARM A8 microprocessor unit circuit, the A / D analog-to-digital conversion circuit, the D / A digital-to-analog conversion circuit, the clock signal distribution circuit, the Ethernet data (IP) Switch switching circuit, the photoelectric conversion circuit, the storage circuit, the power current detection circuit, the temperature detection circuit, the synchronous Ethernet circuit and the interface circuit; the FPGA baseband signal anti-interference processing circuit is respectively connected to the A / D analog-to-digital conversion circuit, the D / A digital-to-analog conversion circuit, the clock signal distribution circuit, the ARM A8 microprocessor unit circuit, and the Ethernet data (IP) Switch switching circuit; the clock signal distribution circuit is connected to the A / D analog-to-digital conversion circuit, the D / A digital-to-analog conversion circuit, the Ethernet data (IP) Switch switching circuit and the FPGA baseband signal anti-interference processing circuit; the ARM The A8 microprocessor unit circuit is respectively connected to the FPGA baseband signal anti-interference processing circuit, the power supply current detection circuit, the temperature detection circuit, the storage circuit and the Ethernet data (IP) Switch switching circuit; the Ethernet data (IP) Switch switching circuit is connected to the FPGA baseband signal anti-interference processing circuit, the ARM A8 microprocessor unit circuit and the photoelectric conversion circuit; the photoelectric conversion circuit is connected to the Ethernet data (IP) Switch switching circuit, the FPGA baseband signal anti-interference processing circuit and the interface circuit.

[0034] The power protection circuit uses an air discharge tube to achieve primary surge protection with a DC overvoltage of 90V and a pulse discharge current of 5KA; then a TVS tube is used to achieve secondary surge protection with a peak pulse power consumption of at least 3000W; finally, a Schottky diode is used to achieve anti-reverse plug-in protection with a surge peak reverse voltage of 100V.

[0035] The power protection circuit converts the -36V to -75V DC voltage input through the MCX socket into +12V voltage through the DC / DC power module after performing anti-static, anti-surge and anti-reverse plug-in protection. The +12V voltage is then converted into six voltages through the DC / DC power chip, namely +5V, +1.2V, +1.8V, +3.3V, +1.0V and +1.1V, among which:

[0036] -48V is converted into +12V through a DC / DC power module. The DC / DC power module has a negative logic input and can provide an output of 12V / 6.25A, with a maximum output ripple of 100mV, a maximum output noise peak-to-peak of 150mV, and a typical conversion efficiency of 91%. With an aluminum backplane, the heat dissipation performance is relatively good;

[0037] +5V is used to power the ARM A8 microprocessor unit circuit, and the voltage range is 4.5V to 5.5V. This circuit is mainly a power management chip of TI. The ARM A8 microprocessor controls the power management chip to output 1.1V, 1.8V and 3.3V to power the ARM A8 microprocessor unit circuit.

[0038] +1.2V is used to power the photoelectric conversion circuit, and the voltage range is 1.1V to 1.3V; the DC / DC power supply chip of this circuit is TI's TPS54620 (take this as an example but not limited to this model), with an input of 12V, an output of 1.2V / 6A, an output ripple of less than 50mV, and a typical conversion efficiency of more than 92%;

[0039] +1.8V is mainly used to power the A / D analog-to-digital conversion circuit, the D / A digital-to-analog conversion circuit and the FPGA baseband signal anti-interference processing circuit, with a voltage range of 1.7V to 1.9V; the DC / DC power supply chip of this circuit is TI's TPS54620 (taking this as an example but not limited to this model), with an input of 12V, an output of 1.8V / 6A, an output ripple of less than 50mV, and a typical conversion efficiency of more than 92%;

[0040] +3.3V is used to power the entire digital anti-interference circuit, with a voltage range of 3V to 3.6V; the DC / DC power supply chip of this circuit is TI's TPS54620 (take this as an example but not limited to this model), with an input of 12V, an output of 3.3V / 6A, an output ripple of less than 50mV, and a typical conversion efficiency of more than 92%;

[0041] +1.1V is used to power the Ethernet data (IP) Switch circuit, with a voltage range of 1.1V to 1.26V; the DC / DC power supply chip of this circuit is TI's TPS54620 (this is used as an example but not limited to this model), with an input of 12V, an output of 1.1V / 6A, an output ripple of less than 50mV, and a typical conversion efficiency of more than 92%;

[0042] +1.0V is the core voltage power supply of the FPGA baseband signal anti-interference processing circuit, and the voltage range is 0.95V to 1.05V. The DC / DC power supply chip of this circuit is TI's TPS54620 (take this as an example but not limited to this model), with an input of 12V, an output of 1.0V / 6A, an output ripple of less than 50mV, and a typical conversion efficiency of more than 92%;

[0043] The power supply current detection circuit detects the +12V voltage after the input power is converted, and sends the detected signal to the ADC interface of the ARM A8 microprocessor unit circuit for processing to determine the working power consumption state of the digital anti-interference baseband circuit.

[0044] The temperature detection circuit detects the working temperature of the board and sends the detected signal to the ADC interface of the ARMA8 microprocessor unit circuit for processing to determine the working temperature status of the digital anti-interference baseband circuit. The working temperature of the digital anti-interference baseband circuit can be viewed in real time through the network management software.

[0045] The core of the ARM A8 microprocessor circuit is TI's AM3352 (taken as an example but not limited to this model). This chip implements parameter configuration of the RF unit module through the SPI interface; analyzes and processes the power supply current detection signal and the temperature detection signal through the ADC interface; loads the program for the FPGA baseband signal anti-interference processing circuit in PS mode through the 8-bit parallel interface; downloads and upgrades the program online through the MMC interface; and implements out-of-band network management functions through the MII interface.

[0046] The core of the storage circuit mainly includes two chips, NANDFLASH and SDRAM. NANDFLASH has a capacity of 2Gb and is connected to the ARM A8 microprocessor circuit and the FPGA baseband signal anti-interference processing circuit through an 8-bit data line. It mainly stores the FPGA baseband signal anti-interference processing circuit program, the ARM A8 microprocessor circuit application program and the out-of-band network management program; SDRAM is DDR2 with a capacity of 2Gbit. It is connected to the ARM A8 microprocessor circuit through a 16-bit data line, a 14-bit address line and other control signals. It mainly stores the running data of the ARM A8 microprocessor circuit application program and the network management program.

[0047] The interface circuit mainly includes microwave intermediate frequency interface RX / TX, RS232 to USB level interface 1, RS232 to USB level interface 2, MMC interface and 1.25G SFP optical interface. The microwave intermediate frequency interface RX is connected to the A / D analog-to-digital conversion circuit through the RX I / Q signal, the microwave intermediate frequency interface TX is connected to the D / A digital-to-analog conversion circuit through the TX I / Q signal, and the microwave intermediate frequency interface RX is connected to the ARM A8 microprocessor circuit through the SPI signal; RS232 to USB level interface 1 is used for debugging and online program upgrade of the ARM A8 microprocessor circuit; RS232 to USB level interface 2 is used for GUI debugging of the FPGA baseband signal anti-interference processing circuit; MMC interface is used for program download and upgrade of the ARM A8 microprocessor circuit; 1.25G SFP optical interface is used for transmitting 1.25G optical fiber signals and network management.

[0048] The clock signal distribution circuit includes TCXO, VCXO, Crystal, clock fan-out buffer and clock generator, among which:

[0049] TCXO is a 3.3V active crystal oscillator with a sine wave output of 25MHz and a frequency stability of ±2PPM. TCXO provides input clock for the clock fan-out buffer.

[0050] The maximum output frequency of the clock fan-out buffer is 350MHz, with a maximum of 4 LVCMOS outputs, one 25MHz clock output to the FPGA baseband signal anti-interference processing circuit, one 25MHz clock output to the Ethernet data (IP) Switch switching circuit, and one 25MHz clock output to the clock generator;

[0051] The maximum output frequency of the clock generator is 1.8GHz, with a maximum of 4 LVPECL outputs and 4 LVDS outputs, of which one 200MHz LVPECL output is given to the D / A digital-to-analog conversion circuit, one 200M LVDS output is given to the A / D analog-to-digital conversion circuit, and one 100M LVDS output is given to the FPGA baseband signal anti-interference processing circuit;

[0052] VCXO is a 3.3V active crystal oscillator, 25MHz LVCMOS output, frequency stability ±30PPM, one 25MHz output to the FPGA baseband signal anti-interference processing circuit as a reference clock, and one 25MHz output to the photoelectric conversion circuit as a working clock;

[0053] Crystal1 is a crystal oscillator with 24MHz output and frequency stability of ±20PPM. Crystal1 provides the working clock for the ARM A8 microprocessor unit circuit;

[0054] Crystal2 is a random crystal oscillator with 32.768KHz output and frequency stability of ±20PPM. Crystal2 provides the RTC clock for the ARM A8 microprocessor unit circuit.

[0055] The core of the A / D analog-to-digital conversion circuit is the ADC chip, which supports dual 11-bit, 200MSPS, parallel LVDS / CMOS output, and 1.8V operating voltage. Among them, 11 LVDS outputs are sent to the FPGA baseband signal anti-interference processing circuit, and 2 I / Q signals are connected to the microwave intermediate frequency interface RX through the filtering circuit.

[0056] The core of the D / A digital-to-analog conversion circuit is the DAC chip, which supports dual-channel 12-bit, 500MSPS, parallel LVDS input, and 1.8V and 3.3V operating voltages. Among them, 12 LVDS data inputs are provided by the FPGA baseband signal anti-interference processing circuit, and 2 differential scalable signals are connected to the microwave intermediate frequency interface TX through the filtering circuit.

[0057] The core of the Ethernet data (IP) Switch switching circuit is the Switch chip, which supports 7 10 / 100 / 1000Mbps ports, 1 SGMII / Serdes interface, and 3 GMII / RGMII / MIIto the MAC. One SGMII interface is connected to the photoelectric conversion circuit; one RGMII interface is connected to the FPGA baseband signal anti-interference processing circuit; and one MII interface is connected to the ARMA8 microprocessor unit circuit.

[0058] The core of the photoelectric conversion circuit is the PHY chip, which supports 4 10 / 100 / 1000BASE-T PHY interfaces, 2 Serial MAC (SerDes) interfaces, 2 MDISerDes interfaces, and 2 recovered clock outputs for synchronous Ethernet. One MDISerDes interface is connected to the 1.25G SFP optical interface; one Serial MAC (SerDes) interface is connected to the Ethernet data (IP) Switch switching circuit; and one recovered clock of synchronous Ethernet is connected to the FPGA baseband signal anti-interference processing circuit.

[0059] The FPGA baseband signal anti-interference processing circuit is the core part of the utility model. It mainly modulates the data sent from the Ethernet data (IP) Switch switching circuit through the RGMII interface and sends it to the D / A digital-to-analog conversion circuit. After the digital-to-analog conversion, the analog zero intermediate frequency signal is sent to the radio frequency unit through the TX of the intermediate frequency interface; the analog zero intermediate frequency signal from the radio frequency unit is sent to the A / D analog-to-digital conversion circuit through the RX of the intermediate frequency interface, and the data is sent to the FPGA after the analog-to-digital conversion. The FPGA performs anti-interference demodulation processing on the analog zero intermediate frequency signal collected by the A / D, and the demodulated signal is sent to the Ethernet data (IP) Switch switching circuit through the RGMII interface. The Ethernet data (IP) Switch switching circuit then forwards it downstream to the photoelectric conversion circuit, and finally sends it out through the 1.25G SFP optical interface. The entire data link can transmit a maximum data capacity of 900Mbps.

[0060] The FPGA baseband signal anti-interference processing circuit has the following characteristics:

[0061] 1.Support multiple modulation modes: QPSK, QAM8, QAM16, QAM32, QAM64, QAM128, QAM256, QAM512, QAM1024.

[0062] Adaptive modulation switching, software programmable profiles.

[0063] Lossless and hitless modulation switching.

[0064] 2. Symbol rate: Software configurable 1.5-100Msym / s, sub-MHz accuracy

[0065] The channel bandwidth supports 3.5MHz-112MHz.

[0066] 3. Adaptive, closed-loop, digital pre-distortion

[0067] Feedback from receiver to transmitter without additional hardware

[0068] 4. Support AD / DA interface: IQ signal with zero intermediate frequency

[0069] 12-bit ADC interface, maximum 200MSPS.

[0070] 12-bit DAC interface, maximum 200MSPS.

[0071] 5.Support various ETSI / FCC different bandwidth standards:

[0072] ETSI: 14, 28, 56, 112MHz.

[0073] FCC: 20, 30, 40, 80MHz.

[0074] 6. Automatically correct the imbalance of IQ amplitude and phase

[0075] Phase ±10 degrees.

[0076] Amplitude ±1.2dB.

[0077] Receive group delay equalizer ±600ps (40ps step)

[0078] 7. Supports improving the fault tolerance of phase noise and phase jump through digital equalization.

[0079] 8.The maximum data link transmission capacity is 900Mbps.

[0080] 9.Support synchronous Ethernet clock transmission.

[0081] Regarding the synchronous Ethernet circuit of the utility model, the following is combined with the attached Figure 2 For further explanation.

[0082] like Figure 2 As shown, the synchronous Ethernet circuit mainly includes the PHY of the photoelectric conversion circuit that recovers the SYNC_E clock and sends it to the FPGA of the FPGA baseband signal anti-interference processing circuit. The FPGA modulates the recovered clock onto the data and sends it to the D / A digital-to-analog conversion circuit. After the digital-to-analog conversion, the zero intermediate frequency signal is sent to the TX of the intermediate frequency interface; the RX of the intermediate frequency interface sends the zero intermediate frequency signal to the A / D analog-to-digital conversion circuit, and after the analog-to-digital conversion, the data is sent to the FPGA. The FPGA demodulates the data and recovers the SYNC_E clock to compare with the reference clock of the FPGA. The output clock of the VCXO is calibrated by giving the control signal to the VCXO to complete the synchronous Ethernet.

[0083] Regarding the network management configuration of the single-channel digital anti-interference baseband circuit unit of the utility model, the following is combined with the attached Figure 3 For further explanation.

[0084] like Figure 3 As shown, the single-channel digital anti-interference baseband circuit of the utility model is connected to the PC through the 1.25SFP interface. Enter 192.168.0.11 in the PC browser to open the network management interface. Enter the user name and password and display Figure 3 Configuration interface, combined with Figure 3 Specific instructions:

[0085] Set Tx Frequency: Set the transmit frequency according to the requirements of the RF unit.

[0086] Output Mode: Set the output mode to IQ mode.

[0087] Channel Bandwidth: According to the requirements of the radio unit, you can set the bandwidth to 3.5, 7, 14, 20, 28, 30, 40, 56, 112 MHz, etc.

[0088] Modulation: According to the requirements of the RF unit, you can set modulation modes such as QPSK, QAM8, QAM16, QAM32, QAM64, QAM128, QAM256, QAM512, and QAM1024.

[0089] Set Tx Power: According to the requirements of the radio unit, the transmit power can be set to 0-27dBm.

[0090] Tx Mute Status: The transmit power can be set to on / off according to the needs of the radio unit.

[0091] The main technical indicators that can be achieved by this utility model are as follows:

[0092]

[0093] The utility model realizes the design of direct current -36V~-75V wide range voltage input, overvoltage and surge protection and multiple low voltage value power conversion circuits, which can meet the power supply characteristic requirements of single-channel digital anti-interference baseband circuits; adopts ARM A8 microprocessor circuit to replace the circuit design of small resource FPGA circuit, and has the advantages of good program portability, easy implementation and maintenance in network management, online program upgrade and other aspects; realizes the storage of application programs and network management programs by large-capacity FLASH chips outside ARM A8 and FPGA plug-in chips, meets the operation of FPGA anti-interference programs, ARM A8 application boot loading, and network management programs; supports QPSK, QAM8, QAM16, QAM32, QAM64, QAM128, QAM256, QAM512 and QAM1024 modulation and demodulation coding methods; supports different ETSI / FCC bandwidth standards, ETSI 3.5 / 7 / 14 / 28 / 56 / 112MHz, FCC 20 / 30 / 40 / 80MHz; supports output of zero intermediate frequency IQ modulated signal, which can be directly converted to microwave frequency band to simplify the design of microwave transceiver module, or converted to intermediate frequency to adapt to traditional microwave transceiver module; zero intermediate frequency analog signal can eliminate the image effect of RF unit.

[0094] The contents not described in detail in this specification belong to the prior art known to professional and technical personnel in the field. Although the embodiments of the utility model have been shown and described, it is understandable to those of ordinary skill in the art that various changes, modifications, substitutions and variations may be made to these embodiments without departing from the principle and spirit of the utility model. The scope of the utility model is defined by the attached claims and their equivalents.

Claims

1. A universal single-channel digital anti-interference baseband circuit, characterized in that: It includes power protection circuit, DC / DC power conversion circuit, power current detection circuit, temperature detection circuit, FPGA baseband signal anti-interference processing circuit, ARM A8 microprocessor unit circuit, A / D analog-to-digital conversion circuit, D / A digital-to-analog conversion circuit, clock signal distribution circuit, Ethernet data (IP) Switch switching circuit, photoelectric conversion circuit, storage circuit, interface circuit and synchronous Ethernet circuit; The power protection circuit is connected to the DC / DC power conversion circuit; the DC / DC power conversion circuit is respectively connected to the FPGA baseband signal anti-interference processing circuit, the ARM A8 microprocessor unit circuit, the A / D analog-to-digital conversion circuit, the D / A digital-to-analog conversion circuit, the clock signal distribution circuit, the Ethernet data (IP) Switch switching circuit, the photoelectric conversion circuit, the storage circuit, the power current detection circuit, the temperature detection circuit, the synchronous Ethernet circuit and the interface circuit; the FPGA baseband signal anti-interference processing circuit is respectively connected to the A / D analog-to-digital conversion circuit, the D / A digital-to-analog conversion circuit, the clock signal distribution circuit, the ARM A8 microprocessor unit circuit, and the Ethernet data (IP) Switch switching circuit; the clock signal distribution circuit is connected to the A / D analog-to-digital conversion circuit, the D / A digital-to-analog conversion circuit, the Ethernet data (IP) Switch switching circuit and the FPGA baseband signal anti-interference processing circuit; the ARM The A8 microprocessor unit circuit is respectively connected to the FPGA baseband signal anti-interference processing circuit, the power supply current detection circuit, the temperature detection circuit, the storage circuit and the Ethernet data (IP) Switch switching circuit; the Ethernet data (IP) Switch switching circuit is connected to the FPGA baseband signal anti-interference processing circuit, the ARM A8 microprocessor unit circuit and the photoelectric conversion circuit; the photoelectric conversion circuit is connected to the Ethernet data (IP) Switch switching circuit, the FPGA baseband signal anti-interference processing circuit and the interface circuit.

2. A universal single-channel digital anti-interference baseband circuit according to claim 1, characterized in that: The chip model of the ARM A8 microprocessor circuit is AM3352.

3. A universal single-channel digital anti-interference baseband circuit according to claim 1, characterized in that: The storage circuit includes two chips, NANDFLASH and SDRAM. The NANDFLASH has a capacity of 2Gb and is connected to the ARM A8 microprocessor circuit and the FPGA baseband signal anti-interference processing circuit through an 8-bit data line. The SDRAM is DDR2 with a capacity of 2Gbit and is connected to the ARM A8 microprocessor circuit through a 16-bit data line, a 14-bit address line and other control signals.

4. A universal single-channel digital anti-interference baseband circuit according to claim 1, characterized in that: The interface circuit includes a microwave intermediate frequency interface RX / TX, an RS232 to USB level interface 1, an RS232 to USB level interface 2, an MMC interface and a 1.25G SFP optical interface, wherein the microwave intermediate frequency interface RX is connected to the A / D analog-to-digital conversion circuit through an RX I / Q signal, the microwave intermediate frequency interface TX is connected to the D / A digital-to-analog conversion circuit through a TX I / Q signal, and the microwave intermediate frequency interface RX is connected to the ARM A8 microprocessor circuit through an SPI signal.

5. A universal single-channel digital anti-interference baseband circuit according to claim 1, characterized in that: The clock signal distribution circuit includes TCXO, VCXO, Crystal, clock fan-out buffer and clock generator, wherein TCXO is a 3.3V active crystal oscillator, with a sine wave output of 25MHz and a frequency stability of ±2PPM, and TCXO provides an input clock for the clock fan-out buffer; the clock fan-out buffer has a maximum output frequency of 350MHz, with a maximum of 4 LVCMOS outputs, of which a 25MHz clock output is given to the FPGA baseband signal anti-interference processing circuit, a 25MHz clock output is given to the Ethernet data (IP) Switch switching circuit, and a 25MHz clock output is given to the clock generator; the clock generator has a maximum output frequency of 1.8GHz, with a maximum of 4 LVPECL outputs and 4 LVDS outputs, of which a 200MHz LVPECL output is given to the D / A digital-to-analog conversion circuit, a 200M LVDS output is given to the A / D analog-to-digital conversion circuit, and a 100M LVDS output is given to the FPGA baseband signal anti-interference processing circuit; the VCXO is a 3.3V active crystal oscillator, with a 25MHz LVCMOS output, frequency stability ±30PPM, one 25MHz output to the FPGA baseband signal anti-interference processing circuit as a reference clock, one 25MHz output to the photoelectric conversion circuit as a working clock; Crystal1 is a random crystal oscillator, 24MHz output, frequency stability ±20PPM, Crystal1 provides the working clock for the ARM A8 microprocessor unit circuit; Crystal2 is a random crystal oscillator, 32.768KHz output, frequency stability ±20PPM, Crystal2 provides the RTC clock for the ARM A8 microprocessor unit circuit.

6. A universal single-channel digital anti-interference baseband circuit according to claim 1, characterized in that: The core of the A / D analog-to-digital conversion circuit is the ADC chip, which supports dual 11 bits, 200MSPS, parallel LVDS / CMOS output, and 1.8V operating voltage. Among them, 11 LVDS outputs are given to the FPGA baseband signal anti-interference processing circuit, and 2 I / Q signals are connected to the microwave intermediate frequency interface RX through the filtering circuit.

7. A universal single-channel digital anti-interference baseband circuit according to claim 1, characterized in that: The core of the D / A digital-to-analog conversion circuit is a DAC chip, which supports dual-channel 12 bits, 500MSPS, parallel LVDS input, and 1.8V and 3.3V operating voltages. The 12-channel LVDS data input is provided by the FPGA baseband signal anti-interference processing circuit, and the 2-channel differential expandable signal is connected to the microwave intermediate frequency interface TX through the filtering circuit.

8. The universal single-channel digital anti-interference baseband circuit according to claim 1, characterized in that: The core of the Ethernet data (IP) Switch switching circuit is a Switch chip, which supports 7 10 / 100 / 1000Mbps ports, 1 SGMII / Serdes interface, and 3 GMII / RGMII / MII to the MAC, wherein one SGMII interface is connected to the photoelectric conversion circuit; one RGMII interface is connected to the FPGA baseband signal anti-interference processing circuit; and one MII interface is connected to the ARM A8 microprocessor unit circuit.

9. A universal single-channel digital anti-interference baseband circuit according to claim 1, characterized in that: The core of the photoelectric conversion circuit is a PHY chip, which supports 4 10 / 100 / 1000BASE-T PHY interfaces, 2 SerialMAC (SerDes) interfaces, 2 MDI SerDes interfaces, and 2 recovered clock outputs for synchronous Ethernet, wherein one MDI SerDes interface is connected to a 1.25G SFP optical interface; one SerialMAC (SerDes) interface is connected to an Ethernet data (IP) Switch switching circuit; and one recovered clock of synchronous Ethernet is connected to an FPGA baseband signal anti-interference processing circuit.

10. A universal single-channel digital anti-interference baseband circuit according to claim 1, characterized in that: The FPGA baseband signal anti-interference processing circuit modulates the data sent from the Ethernet data (IP) Switch switching circuit through the RGMII interface and sends it to the D / A digital-to-analog conversion circuit. After the digital-to-analog conversion, the analog zero intermediate frequency signal is sent to the radio frequency unit through the TX of the intermediate frequency interface; the analog zero intermediate frequency signal from the radio frequency unit is sent to the A / D analog-to-digital conversion circuit through the RX of the intermediate frequency interface, and the data is sent to the FPGA after the analog-to-digital conversion. The FPGA performs anti-interference demodulation processing on the analog zero intermediate frequency signal collected by the A / D, and the demodulated signal is sent to the Ethernet data (IP) Switch switching circuit through the RGMII interface. The Ethernet data (IP) Switch switching circuit then forwards it downstream to the photoelectric conversion circuit, and finally sends it out through the 1.25G SFP optical interface.

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