Semiconductor structure

Abstract

The utility model relates to a semiconductor structure. The semiconductor structure comprises a target layer structure and a conductive structure. The target layer structure comprises at least one dielectric layer, and at least one groove is formed in the dielectric layer. The conductive structure is located in the groove and is in direct contact with the dielectric layer. Wherein the bottom surface, in direct contact with the dielectric layer, of the conductive structure has the maximum surface roughness D1, the side surface, in direct contact with the dielectric layer, of the conductive structure has the maximum surface roughness D2, and the maximum surface roughness D1gt; the maximum surface roughness is D2. The utility model is used for improving the process reliability and the electrical performance of the high-density integrated memory.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure. Background Art

[0002] As a commonly used semiconductor memory device in computers, the memory usually includes an array region (Array Region) composed of multiple memory cells (MemoryCell) and a peripheral area (Peripheral Area) composed of a control circuit. The memory cell can adopt a 1T1C architecture, that is, it includes a transistor and a capacitor, so that the transistor controls the capacitor to store or release charge. The control circuit can address and drive the target memory cell to access data by connecting the word line (Word Line, WL for short) and the bit line (Bit Line, BL for short) of each memory cell. However, with the continuous increase in the storage capacity requirements of the memory, for example, the need to adopt buried word line technology, resulting in higher reliability requirements for the process technology, and it is also easy to affect the electrical performance of the high-density integrated memory due to groove manufacturing defects. Utility Model Content

[0003] Based on this, the embodiments of the present disclosure provide a semiconductor structure that is beneficial to improving process reliability and the electrical performance of high-density integrated memory.

[0004] In order to achieve the above-mentioned purpose, the semiconductor structure provided by the embodiment of the present disclosure includes: a target layer structure and a conductive structure. The target layer structure includes at least one dielectric layer, and at least one groove is provided in the dielectric layer. The conductive structure is located in the groove and is in direct contact with the dielectric layer. The bottom surface of the conductive structure in direct contact with the dielectric layer has a maximum surface roughness D1, and the side surface of the conductive structure in direct contact with the dielectric layer has a maximum surface roughness D2, and the maximum surface roughness D1> the maximum surface roughness D2.

[0005] In some embodiments of the present disclosure, the bottom of the trench has a plurality of pits, and the bottom of the conductive structure has a plurality of protrusions filling the pits.

[0006] In some embodiments of the present disclosure, the distance from any protrusion to the midpoint of the bottom surface of the conductive structure along the first direction is greater than the distance from the protrusion to the edge of the conductive structure; wherein the first direction is perpendicular to the depth direction of the groove, and the first direction is the width direction of the groove.

[0007] In some embodiments of the present disclosure, the bottom surface of the conductive structure includes: a middle region and a peripheral region adjacent to the middle region; wherein the surface roughness of the middle region is smaller than the surface roughness of the peripheral region.

[0008] In some embodiments of the present disclosure, the bottom surface of the conductive structure includes: a first region, a second region, and a third region arranged in sequence and equidistantly along a first direction; wherein the first direction is perpendicular to the depth direction of the groove, and the first direction is the width direction of the groove; the surface roughness of the second region and the third region are both greater than the surface roughness of the first region.

[0009] In some embodiments of the present disclosure, the surface roughness of the second region and the third region are the same or similar; or, the surface roughness of the third region is greater than the surface roughness of the second region.

[0010] In some embodiments of the present disclosure, the semiconductor structure further comprises a substrate. The target layer structure is located on the substrate. The minimum distances from the second region and the third region to the substrate are both greater than the minimum distance from the first region to the substrate.

[0011] In some embodiments of the present disclosure, the target layer structure includes at least two dielectric layers stacked along the depth direction of the trench, and the conductive structure is only filled in the first dielectric layer at the bottom of the trench.

[0012] In some embodiments of the present disclosure, the first dielectric layer includes a silicon oxide layer, a silicon dioxide layer, an undoped silicon glass layer, a doped silicon nitride layer, a tetraethoxysilane layer or a fluorosilicone glass layer. The conductive structure includes a metal conductive layer.

[0013] In some embodiments of the present disclosure, along the depth direction away from the bottom of the groove, the width of the conductive structure in the first direction gradually increases; wherein the first direction is perpendicular to the depth direction of the groove, and the first direction is the width direction of the groove.

[0014] In some embodiments of the present disclosure, the target layer structure includes at least two dielectric layers stacked along the depth direction of the groove. The conductive structure is filled in the groove in each dielectric layer, and the corresponding parts of the conductive structure located in different dielectric layers have different widths in the first direction; wherein the first direction is perpendicular to the depth direction of the groove, and the first direction is the width direction of the groove.

[0015] In some embodiments of the present disclosure, the conductive structure includes: a first metal layer and a second metal layer. The first metal layer conformally covers the bottom and side surfaces of the groove. The second metal layer covers the first metal layer and fills the groove. The maximum surface roughness of the bottom surface of the first metal layer is greater than the maximum surface roughness of the side surface thereof.

[0016] In some embodiments of the present disclosure, a top surface of the second metal layer facing away from the bottom of the trench is lower or higher than a top surface of the first metal layer facing away from the bottom of the trench.

[0017] The embodiments of the present disclosure may or at least have the following advantages:

[0018] The disclosed embodiment forms a groove in the dielectric layer of the target layer structure, and forms a conductive structure in direct contact with the dielectric layer in the groove. The bottom surface and the side surface of the conductive structure can have different surface roughnesses, and specifically, the maximum surface roughness D1 of the bottom surface of the conductive structure is greater than the maximum surface roughness D2 of the side surface of the conductive structure. In this way, in the context of the continuous reduction of component size, the conductive structure formed in the groove and in direct contact with the dielectric layer can ensure the electrical performance of the conductive structure based on the smaller maximum surface roughness of its side surface relative to the bottom surface, and at the same time, the contact performance of the conductive structure and the bottom electric field distribution can be regulated based on the larger maximum surface roughness of its bottom surface relative to the side surface, thereby effectively improving the electrical performance of the groove conductive structure and ensuring its process reliability, which is conducive to improving the electrical performance of high-density integrated memory.

[0019] The details of one or more embodiments of the present disclosure are set forth in the following drawings and description. Other features, objects, and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 is a schematic cross-sectional view of a semiconductor structure provided in some embodiments;

[0022] Figure 2 A characteristic schematic diagram of a surface roughness provided in some embodiments;

[0023] Figure 3 is a cross-sectional schematic diagram of another semiconductor structure provided in some embodiments;

[0024] Figure 4 is a cross-sectional schematic diagram of another semiconductor structure provided in some embodiments;

[0025] Figure 5 A schematic cross-sectional view of another semiconductor structure provided in some embodiments and a partial enlarged view thereof;

[0026] Figure 6 A schematic cross-sectional view of another semiconductor structure provided in some embodiments and a partial enlarged view thereof;

[0027] Figure 7A schematic cross-sectional view of another semiconductor structure provided in some embodiments and a partial enlarged view thereof;

[0028] Figure 8 is a cross-sectional schematic diagram of another semiconductor structure provided in some embodiments;

[0029] Fig. 9 is a cross-sectional schematic diagram of another semiconductor structure provided in some embodiments;

[0030] Fig.10 is a cross-sectional schematic diagram of another semiconductor structure provided in some embodiments;

[0031] Fig.11 is a cross-sectional schematic diagram of another semiconductor structure provided in some embodiments;

[0032] Fig.12 is a cross-sectional schematic diagram of another semiconductor structure provided in some embodiments;

[0033] Fig.13 A scanning electron microscope image of a cross section of a semiconductor structure provided in some embodiments;

[0034] Fig.14 is a cross-sectional schematic diagram of another semiconductor structure provided in some embodiments;

[0035] Fig.15 A schematic flow chart of a method for preparing a semiconductor structure provided in some embodiments.

[0036] Description of reference numerals:

[0037] 1-target layer structure, G-groove, 2-conductive structure, 10-substrate, 11-first dielectric layer, 12-second dielectric layer, 13-third dielectric layer, 14-fourth dielectric layer, 21-bump, 201-first metal layer, 202-second metal layer, 203-gate insulating layer, 204-insulating cap layer, 3-interconnection structure, S d - Bottom surface of the conductive structure, S r - Side of the conductive structure, R C - Middle area, R P - peripheral region, R1 - first region, R2 - second region, R3 - third region. DETAILED DESCRIPTION

[0038] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0040] It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below can be represented as a second element, component, region, layer or part.

[0041] It should be understood that when an element is considered to be "connected" to another element, it can be directly connected to the other element, or connected to the other element through an intermediate element. In addition, the "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if there is transmission of electrical signals or data between the connected objects.

[0042] It should be understood that the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0043] With the continuous increase in the requirements for memory storage capacity, for example, the need to use buried word line technology, the reliability requirements for the process technology are higher, and the electrical performance of high-density integrated memory is easily affected by groove manufacturing defects, especially for the electrical performance of conductive structures (such as buried word lines) prepared by using grooves with a high aspect ratio.

[0044] Based on this, the embodiments of the present disclosure provide a semiconductor structure that is beneficial to improving the process reliability of the trench conductive structure and the electrical performance of a high-density integrated memory.

[0045] See also Figure 1The semiconductor structure provided by the embodiment of the present disclosure includes: a target layer structure 1 and a conductive structure 2. The target layer structure 1 includes at least one dielectric layer, and at least one trench G is provided in the dielectric layer. The conductive structure 2 is located in the trench G and is in direct contact with the dielectric layer. The bottom surface S of the conductive structure 2 in direct contact with the dielectric layer d The side surface S of the conductive structure 2 having the maximum surface roughness D1 and directly contacting the dielectric layer r The surface roughness D2 is greater than the maximum surface roughness D1. The surface roughness D2 is defined as: the size difference between the highest structural feature and the lowest structural feature on the surface. Figure 2 The maximum surface roughness D1 is used to represent the distance 5 between the highest point 4 and the lowest point 3 of the rough surface. In the embodiment of the present disclosure, a groove G is formed in the dielectric layer of the target layer structure 1, and a conductive structure 2 directly in contact with the dielectric layer is formed in the groove G. The bottom surface S of the conductive structure 2 can be made d and side S r They have different surface roughnesses, specifically, the bottom surface S of the conductive structure 2 d The maximum surface roughness D1 is greater than the side surface S of the conductive structure 2. r Thus, in the context of the continuous reduction in the size of components, the conductive structure 2 formed in the trench G and in direct contact with the dielectric layer can be based on its side surface S r Relative to the bottom surface S d The smaller maximum surface roughness D2 corresponds to ensuring the electrical performance of the conductive structure 2, while based on its bottom surface S d Relative to the side S r The larger maximum surface roughness D1 corresponds to regulating the contact performance of the conductive structure 2 and the bottom electric field distribution, thereby effectively improving the electrical performance of the trench conductive structure and ensuring its process reliability, which is beneficial to improving the electrical performance of high-density integrated memory.

[0046] It is worth mentioning that in the embodiment of the present disclosure, the bottom surface S of the conductive structure 2 is d And side S r The control of the surface roughness can be achieved by controlling the morphology of the groove G. For example, see Figure 3 The bottom of the groove G has a plurality of pits. The bottom of the conductive structure 2 has a plurality of protrusions 21 filling the pits. The protrusions can be defined as the surface roughness of the conductive structure 2. dThe surface roughness of the conductive structure 2 can be controlled by the morphology of each protrusion 21 formed at the bottom of the conductive structure 2, and the longitudinal cross-sectional profile of the protrusion 21 can be, for example, in the shape of an arc. The disclosed embodiment does not limit the number, size, and position distribution of the pits in the groove G. The pits at the bottom of the groove G can be formed by directional etching, for example, by a plasma etching process.

[0047] In addition, it should be added that the bottom surface S of the conductive structure 2 d And side S r The specific implementation of the surface roughness can be realized in many different ways.

[0048] In some embodiments of the present disclosure, please refer to Figure 4 , a distance L1 from any protrusion 21 to the midpoint O1 of the bottom surface of the conductive structure 2 along the first direction (for example, the X direction) is greater than a distance L2 from the protrusion 21 to the edge O2 of the conductive structure 2; wherein the first direction (for example, the X direction) is perpendicular to the depth direction of the groove G (for example, the Z direction), and the first direction (for example, the X direction) is the width direction of the groove G.

[0049] In the embodiment of the present disclosure, each protrusion 21 is distributed between the midpoint O1 of the bottom surface of the conductive structure 2 and the edge O2 of the conductive structure 2, avoiding the position of the midpoint O1 of the bottom surface of the conductive structure 2 and the corner position of the edge O2. After making the distance L1 from the protrusion 21 to the midpoint O1 of the bottom surface of the conductive structure 2 along the first direction (for example, the X direction) greater than the distance L2 from the protrusion 21 to the edge O2 of the conductive structure 2, the bottom surface S of the conductive structure 2 can be adjusted by the setting position of each protrusion 21. d surface roughness and contact performance, and balance the bottom electric field distribution of the conductive structure 2.

[0050] For example, the number of the protrusions 21 is an even number, and the protrusions 21 may be symmetrically distributed in a first direction (eg, X direction) with the midpoint O1 of the bottom surface of the conductive structure 2 as the center.

[0051] In some other embodiments of the present disclosure, please refer to Figure 5 , the bottom surface S of the conductive structure 2 d Includes: Middle area R C and near the middle area R C The surrounding area R P ; Among them, the middle area R C The surface roughness is less than that of the surrounding area R C surface roughness.

[0052] In the embodiment of the present disclosure, the middle area R C The area of ​​the conductive structure 2 is not limited, and can be matched to the needs of the bottom surface S d The geometric center is defined according to the preset size.

[0053] In some other embodiments of the present disclosure, please refer to Figure 6 The bottom surface of the conductive structure 2 includes: a first region R1, a second region R2 and a third region R3 which are arranged in sequence and equidistantly along a first direction (for example, the X direction); wherein the first direction (for example, the X direction) is perpendicular to the depth direction (for example, the Z direction) of the groove G, and the first direction (for example, the X direction) is the width direction of the groove (G); the surface roughness of the second region R2 and the third region R3 are both greater than the surface roughness of the first region R1.

[0054] Optionally, the surface roughness of the second region R2 and the third region R3 is the same or similar.

[0055] Optionally, the surface roughness of the third region R3 is greater than the surface roughness of the second region R2.

[0056] In some other embodiments of the present disclosure, please refer to Figure 7 The semiconductor structure further includes a substrate 10. The target layer structure 1 is located on the substrate 10. The minimum distance (eg, L 12 and L 13 ) are greater than the minimum distance L from the first region R1 to the substrate 10 11 That is, the bottom surface of the conductive structure 2 may be tilted relative to the surface of the substrate 10 and extend along a preset direction.

[0057] In some other embodiments of the present disclosure, please refer to Figure 8 The target layer structure 1 includes at least two dielectric layers stacked along the depth direction (eg, Z direction) of the trench G. The conductive structure 2 is only filled in the first dielectric layer 11 at the bottom of the trench G.

[0058] Optionally, the first dielectric layer 11 includes a silicon oxide layer, a silicon dioxide layer, an undoped silicon glass layer (USG), a doped silicon nitride layer (NDC), a tetraethoxysilane layer (TEOS) or a fluorosilicate glass layer (FSG).

[0059] Optionally, the conductive structure 2 includes a metal conductive layer.

[0060] In some examples, such as Figure 8As shown in , the target layer structure 1 includes a first dielectric layer 11, a second dielectric layer 12, a third dielectric layer 13 and a fourth dielectric layer 14 stacked along the depth direction (e.g., Z direction) of the groove G; wherein the first dielectric layer 11 is an undoped silicon glass layer (USG), the second dielectric layer 12 is a doped silicon nitride layer (NDC), the third dielectric layer 13 is a tetraethoxysilane layer (TEOS), and the fourth dielectric layer 14 is a fluorosilicone glass layer (FSG). Accordingly, the conductive structure 2 is only filled in the first dielectric layer 11 at the bottom of the groove G. The portion of the groove G located in the second dielectric layer 12, the third dielectric layer 13 and the fourth dielectric layer 14 can be filled to form an interconnection structure 3. The interconnection structure 3 is connected to the conductive structure 2, and the material of the interconnection structure 3 and the conductive structure 2 can be the same or different.

[0061] In addition, in some other embodiments of the present disclosure, the target layer structure 1 includes at least two dielectric layers stacked along the depth direction of the groove G (for example, the Z direction), and the conductive structure 2 is filled in each dielectric layer corresponding to the groove G, which is also allowed.

[0062] In some embodiments of the present disclosure, please refer to Fig. 9 , along the depth direction (for example, Z direction) away from the bottom of the groove G, the width of the conductive structure 2 in the first direction (for example, X direction) gradually increases; wherein the first direction (for example, X direction) is perpendicular to the depth direction (for example, Z direction) of the groove (G), and the first direction (for example, X direction) is the width direction of the groove (G).

[0063] For example, along the depth direction away from the bottom of the groove G (for example, the Z direction), the bottom width of the conductive structure 2 is W1, the middle width of the conductive structure 2 is W2, and the top width of the conductive structure 2 is W3, wherein the top width W3>the middle width W2>the bottom width W1.

[0064] In some other embodiments of the present disclosure, please refer to Fig.10 , the target layer structure 1 includes at least two dielectric layers stacked along the depth direction (e.g., Z direction) of the groove G; for example, it includes a first dielectric layer 11 and a second dielectric layer 12. The conductive structure 2 is filled in the groove G in each dielectric layer, and the corresponding parts of the conductive structure 2 located in different dielectric layers have different widths in the first direction (e.g., X direction); wherein the first direction (e.g., X direction) is perpendicular to the depth direction (e.g., Z direction) of the groove G, and the first direction (e.g., X direction) is the width direction of the groove G.

[0065] In some other embodiments of the present disclosure, please refer to Fig.11The conductive structure 2 includes: a first metal layer 201 and a second metal layer 202. The first metal layer 201 conformally covers the bottom and side surfaces of the groove G. The second metal layer 202 covers the first metal layer 201 and fills the groove G. The maximum surface roughness of the bottom surface of the first metal layer 201 is greater than the maximum surface roughness of the side surface thereof.

[0066] By way of example, the first metal layer 201 includes, but is not limited to, a titanium nitride layer.

[0067] By way of example, the second metal layer 202 includes, but is not limited to, a tungsten layer.

[0068] In some other embodiments of the present disclosure, please refer to Fig.12 and Fig.13 , the top surface of the second metal layer 202 away from the bottom of the trench G is lower than the top surface of the first metal layer 201 away from the bottom of the trench G.

[0069] In some other embodiments of the present disclosure, please refer to Fig.14 It is also allowed that the top surface of the second metal layer 202 facing away from the bottom of the trench G is higher than the top surface of the first metal layer 201 facing away from the bottom of the trench G.

[0070] It should be noted that the conductive structure 2 provided in the embodiment of the present disclosure can be applied as a sub-micron interlayer damascene interconnection structure, a high aspect ratio intralayer interconnection structure, or a buried word line of a memory. In addition, the target layer structure 1 provided in the embodiment of the present disclosure does not only include the substrate 10 and the film layer stacked on the surface of the substrate 10, but also includes a film layer formed in the substrate 10, such as Fig.14 The shallow trench isolation structure STI shown in FIG.

[0071] For some examples, see Fig.14 , Fig.14 FIG. 1 shows a partial cross-sectional structure of a memory. Fig.14 As shown, a shallow trench isolation structure STI is provided in the substrate 10 of the memory, and the shallow trench isolation structure STI separates a plurality of active areas AA in the substrate 10. A plurality of word line trenches are also provided in the substrate 10 to form buried word lines WL; wherein some of the word line trenches are located in the shallow trench isolation structure STI. Accordingly, the trench G described in some of the aforementioned embodiments may be a word line trench located in the shallow trench isolation structure STI, and the conductive structure 2 may correspond to a buried word line WL.

[0072] By way of example, the buried word line WL includes a gate insulation layer 203, a first metal layer 201, a second metal layer 202 and an insulating cap layer 204 sequentially arranged in a word line trench; wherein the maximum surface roughness of the bottom surface of the buried word line WL in the word line trench in the shallow trench isolation structure STI is greater than the maximum surface roughness of its side surface.

[0073] For example, the shallow trench isolation structure STI may include a single layer or multiple layers of dielectric materials. Suitable dielectric materials may include, for example, silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), nitrogen-doped silicon carbide (NDC), low dielectric constant (low-k) dielectric materials such as fluorosilicate glass (FSG), silicon carbon oxide (SiCOH), spin-on silicon glass (spin-on glass), porous low-k dielectric material (porous low-k dielectric material), organic polymer dielectric material, or a combination of the above materials, but is not limited thereto.

[0074] By way of example, the insulating capping layer 204 and the gate insulating layer 203 may respectively include dielectric materials, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), nitrogen-doped silicon carbide (NDC), or a combination of the above materials, but is not limited thereto.

[0075] In some embodiments, the gate insulating layer 203 may include a high-k constant metal oxide dielectric material, such as hafnium oxide (HfO), hafnium oxide silicate (HfSiO), hafnium oxide nitride (HfSiON), aluminum oxide (AlO), lanthanum oxide (LaO), lanthanum aluminate (LaAlO), tantalum oxide (TaO), zirconium oxide (ZrO), zirconium oxide silicate (ZrSiO), or hafnium zirconate (HfZrO), but is not limited thereto.

[0076] For example, the material of the first metal layer 201 may include an n-type work function metal such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl) or TiAlC (titanium aluminum carbide) or a combination of the above materials, or may include a p-type work function metal such as titanium nitride (TiN), tantalum nitride (TaN) or tantalum carbide (TaC) or a combination of the above materials, but is not limited thereto.

[0077] For example, the second metal layer 202 may include metal materials such as tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), combinations thereof such as compounds, alloys, and / or composite layers, but is not limited thereto.

[0078] In addition, the substrate 10 of the memory may further include other circuit elements and structures, such as a bit line structure and an interconnection structure, which are not shown in the figure for simplicity of illustration.

[0079] Some embodiments of the present disclosure also provide a method for manufacturing a semiconductor structure, which is used to manufacture the semiconductor structure in some of the above embodiments. The technical advantages of the above semiconductor structure are also possessed by the method for manufacturing the semiconductor structure, which will not be described in detail here. In addition, each layer structure involved in the following method embodiments can be implemented in combination with the above-mentioned related records corresponding to the same features.

[0080] See also Fig.15 , the manufacturing method of the semiconductor structure may include the following steps S100 to S300.

[0081] S100, preparing a target layer structure, where the target layer structure includes at least one dielectric layer.

[0082] S200 , forming at least one trench in the dielectric layer.

[0083] S300, forming a conductive structure directly contacting the dielectric layer in the groove; wherein the bottom surface of the conductive structure directly contacting the dielectric layer has a maximum surface roughness D1, and the side surface of the conductive structure directly contacting the dielectric layer has a maximum surface roughness D2, and the maximum surface roughness D1>the maximum surface roughness D2.

[0084] In some embodiments of the present disclosure, step S200 forms at least one trench G in the dielectric layer, and further includes: forming a plurality of pits at the bottom of the trench.

[0085] Accordingly, step S300 forms a conductive structure directly contacting the dielectric layer in the trench, and further includes: forming a plurality of protrusions filling the pits at the bottom of the conductive structure, and the protrusions can define the surface roughness of the conductive structure.

[0086] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0087] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0088] The above-described embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims

1. A semiconductor structure, characterized in that: include: The target layer structure comprises at least one dielectric layer, wherein at least one groove is provided in the dielectric layer; A conductive structure, located in the trench and in direct contact with the dielectric layer; The bottom surface of the conductive structure directly contacting the dielectric layer has a maximum surface roughness D1, and the side surface of the conductive structure directly contacting the dielectric layer has a maximum surface roughness D2, and the maximum surface roughness D1>the maximum surface roughness D2.

2. The semiconductor structure according to claim 1, characterized in that: The bottom of the trench has a plurality of pits; the bottom of the conductive structure has a plurality of protrusions filling the pits.

3. The semiconductor structure according to claim 2, characterized in that: The distance from any one of the protrusions to the midpoint of the bottom surface of the conductive structure along the first direction is greater than the distance from the protrusion to the edge of the conductive structure; wherein the first direction is perpendicular to the depth direction of the groove, and the first direction is the width direction of the groove.

4. The semiconductor structure according to claim 1, characterized in that: The bottom surface of the conductive structure includes: a middle area and a peripheral area adjacent to the middle area; Wherein, the surface roughness of the middle area is smaller than the surface roughness of the peripheral area.

5. The semiconductor structure according to claim 1, characterized in that: The bottom surface of the conductive structure includes: a first region, a second region and a third region which are arranged in sequence and at equal distances along a first direction; The first direction is perpendicular to the depth direction of the groove, and the first direction is the width direction of the groove; the surface roughness of the second region and the third region is greater than the surface roughness of the first region.

6. The semiconductor structure according to claim 5, characterized in that: The surface roughness of the second region and the third region is the same or similar; Alternatively, the surface roughness of the third region is greater than the surface roughness of the second region.

7. The semiconductor structure according to claim 5, characterized in that: Also included is a substrate; The target layer structure is located on the substrate; The minimum distances from the second region and the third region to the substrate are both greater than the minimum distance from the first region to the substrate.

8. The semiconductor structure according to claim 1, characterized in that: The target layer structure includes at least two dielectric layers stacked along the depth direction of the trench; the conductive structure is only filled in the first dielectric layer at the bottom of the trench.

9. The semiconductor structure according to claim 8, characterized in that: The first dielectric layer comprises a silicon oxide layer, a silicon dioxide layer, an undoped silicon glass layer, a doped silicon nitride layer, a tetraethoxysilane layer or a fluorosilicone glass layer; The conductive structure includes a metal conductive layer.

10. The semiconductor structure according to claim 1, wherein: Along the depth direction away from the bottom of the trench, the width of the conductive structure in a first direction gradually increases; wherein the first direction is perpendicular to the depth direction of the trench, and the first direction is the width direction of the trench.

11. The semiconductor structure according to claim 1, characterized in that: The target layer structure includes at least two dielectric layers stacked along the depth direction of the groove; the conductive structure is filled in the groove in each of the dielectric layers, and the corresponding parts of the conductive structure located in different dielectric layers have different widths in the first direction; wherein the first direction is perpendicular to the depth direction of the groove, and the first direction is the width direction of the groove.

12. The semiconductor structure according to claim 1, characterized in that The conductive structure comprises: A first metal layer conformally covers the bottom and side surfaces of the groove; a second metal layer, covering the first metal layer and filling the groove; The maximum surface roughness of the bottom surface of the first metal layer is greater than the maximum surface roughness of the side surface thereof.

13. The semiconductor structure according to claim 12, characterized in that: A top surface of the second metal layer facing away from the bottom of the trench is lower or higher than a top surface of the first metal layer facing away from the bottom of the trench.

Images