Sealing ring structure of chip and chip

Abstract

The utility model provides a sealing ring structure of a chip and the chip, the sealing ring structure surrounds a chip main body and is arranged in a dielectric layer above a substrate, the sealing ring structure comprises an inner sealing ring, the inner sealing ring surrounds the chip main body and comprises a plurality of straight edges, extension lines of adjacent straight edges form a right angle, and a chamfer is formed between adjacent straight edges; the outer sealing ring is arranged around the inner sealing ring, and chamfers are formed between the adjacent straight edges; the right triangle sealing areas are arranged on the periphery of the chamfer of the outer sealing ring on the outermost layer, the bevel edges of the right triangle sealing areas are opposite to the chamfer, and the right-angle edges of the right triangle sealing areas are overlapped with the extension lines of the straight edges of the outer sealing ring on the outermost layer; in the thickness direction of the chip body, the inner sealing ring, the outer sealing ring and the right triangle sealing area comprise a plurality of metal layers, and a plurality of staggered metal strips coupled between every two adjacent metal layers are arranged between the adjacent metal layers. According to the technical scheme, the sealing ring is stable in structure, especially at the corner.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, and in particular to a sealing ring structure and a chip for a chip. Background Art

[0002] Since silicon material is relatively brittle, when cutting a wafer along a scribe line, certain mechanical stresses will be generated on the front and back surfaces of the wafer, which may cause cracks at the edge of the chip. The cracks at the edge of the chip (especially at the four corners) will further expand during subsequent packaging processes or chip usage, resulting in chip breakage and electrical failure of the chip.

[0003] To protect the chip, a sealing ring structure is usually designed around the chip. It can block unnecessary stress expansion and cracking from the scribe line to the chip caused by the above-mentioned wafer cutting process; it can also block the penetration of water vapor into the chip.

[0004] The sealing ring in the prior art has a right-angle structure at the corner. As Figure 1 shown, during cutting, due to the concentrated stress at position M, cracks are also likely to occur, resulting in the failure of the sealing effect. Summary of the Utility Model

[0005] The utility model provides a sealing ring structure and a chip for a chip to solve the problem that cracks are likely to occur at the corner of the sealing ring in the prior art, resulting in the failure of the sealing effect.

[0006] To solve the above technical problems, the utility model is realized through the following technical solutions:

[0007] According to the first aspect of the utility model, a sealing ring structure for a chip is provided. The sealing ring structure is arranged in a dielectric layer above a substrate around a chip body, and it includes:

[0008] An inner sealing ring, which is arranged around the chip body, includes multiple straight edges. The extension lines of adjacent straight edges form a right angle, and a chamfer is formed between adjacent straight edges;

[0009] At least one outer sealing ring, which is arranged around the inner sealing ring, and a chamfer is formed between adjacent straight edges;

[0010] Multiple right-angled triangle sealing regions, which are arranged outside the chamfer of the outermost outer sealing ring. Its hypotenuse faces the chamfer, and the right-angled sides of the right-angled triangle sealing region overlap with the extension lines of the straight edges of the outermost outer sealing ring;

[0011] In the thickness direction of the chip body, the inner sealing ring, the outer sealing ring, and the right-angled triangle sealing area include multiple metal layers, and a number of metal strips are arranged in an interleaved manner between adjacent metal layers and coupled between the two.

[0012] Optionally, the metal strips include a first metal strip, a second metal strip, a third metal strip, and a fourth metal strip;

[0013] The first metal strip is arranged between adjacent metal layers of the inner sealing ring and is distributed in a star-shaped network along the circumferential direction of the inner sealing ring;

[0014] The second metal strip is arranged between adjacent metal layers of the outer sealing ring and is distributed in a cross shape along the circumferential direction of the outer sealing ring;

[0015] The third metal strip and the fourth metal strip are arranged between adjacent metal layers of the right-angled triangle sealing area. The third metal strip is arranged along the circumferential direction of the right-angled triangle sealing area, and the fourth metal strip is orthogonally distributed inside the third metal strip.

[0016] Optionally, between the bottommost metal layer of the inner sealing ring and the substrate, there are multiple metal strips arranged in an interleaved manner and coupled between the two;

[0017] Between the bottommost metal layer of the outer sealing ring and the substrate, there are multiple metal strips arranged in an interleaved manner and coupled between the two;

[0018] Between the bottommost metal layer of the right-angled triangle sealing area and the substrate, there are multiple metal strips arranged in an interleaved manner and coupled between the two.

[0019] Optionally, between the corresponding adjacent metal layers of the inner sealing ring, there are also multiple fifth metal strips coupled between the two; the fifth metal strips are arranged at the corners where the first metal strip is distributed along the circumferential direction of the inner sealing ring and are perpendicular to the circumferential distribution direction, and the corners are located on the edge where the straight side of the inner sealing ring intersects the chamfer.

[0020] Optionally, the fourth metal strips are parallel or orthogonal to each other in pairs.

[0021] Optionally, the distance between two adjacent parallel fourth metal strips is 1 micrometer.

[0022] Optionally, the width of the inner sealing ring is greater than the width of the outer sealing ring.

[0023] Optionally, the width of the inner sealing ring is 5 micrometers; and / or,

[0024] The width of the outer sealing ring is 1.5 micrometers.

[0025] Optionally, the distance between the innermost outer sealing ring and the inner sealing ring is 1 micrometer; and / or,

[0026] When there are multiple outer sealing rings, the distance between adjacent outer sealing rings is 1 micrometer.

[0027] According to a second aspect of the present invention, there is provided a chip, which includes:

[0028] A chip body;

[0029] A sealing ring structure, which is arranged around the chip body; the sealing ring structure is the sealing ring structure described in any one of the above.

[0030] For the sealing ring structure and the chip of the chip provided by the present invention, first, the corner positions of the inner sealing ring and at least one outer sealing ring are set as chamfered structures, which enhances the stability at these positions; secondly, a plurality of right-angled triangle sealing areas are arranged outside the chamfer, making the stability at the corner positions stronger; further, the extension line of the straight edge of the outermost outer sealing ring overlaps with the right-angled side of the right-angled triangle sealing area, and the overall structure looks like a square structure, making the overall structure more stable; in addition, the inner sealing ring, the outer sealing ring and the right-angled triangle sealing area include multiple metal layers, and a number of interleaved metal strips are arranged between adjacent metal layers and coupled between the two. The metal strips are interleaved, making the structure of the sealing ring more stable, and making the contact area between the metal strips and the metal layers larger, with stronger anti-cracking and anti-stress deformation characteristics.

[0031] In an optional solution of the present invention, the metal strips between adjacent metal layers of the inner sealing ring are distributed in a star-shaped network, the metal strips between adjacent metal layers of the outer sealing ring are distributed in a cross shape, and the metal strips between adjacent metal layers of the right-angled triangle sealing area are distributed orthogonally, which can further improve the stability, anti-cracking and anti-deformation properties of the sealing ring structure.

[0032] In an optional solution of the present invention, between the corresponding connected metal layers of the inner sealing ring, there are also a plurality of fifth metal strips coupled between the two, which are arranged at the corners of the first metal strips distributed along the circumferential direction of the inner sealing ring and are perpendicular to the circumferential distribution direction, which can further improve the stability of the sealing ring at the corner positions. Description of the Drawings

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0034] Figure 1 Schematic diagram of a sealing ring of the prior art;

[0035] Figure 2 Top perspective view of the sealing ring structure of a chip according to an embodiment of the present invention;

[0036] Figure 3 Partial perspective view of the sealing ring structure of a chip according to an embodiment of the present invention;

[0037] Figure 4a Partial perspective view of the inner sealing ring and the outer sealing ring according to an embodiment of the present invention;

[0038] Figure 4b According to the present invention along Figure 4a Cross-sectional view taken along the dashed line a in;

[0039] Figure 4c According to the present invention along Figure 4a Cross-sectional view taken along the dashed line b in;

[0040] Figure 5a Perspective view of a right triangle sealing area according to an embodiment of the present invention;

[0041] Figure 5b According to the present invention along Figure 5a Cross-sectional view taken along the dashed line c in;

[0042] Figure 5c According to the present invention along Figure 5a Cross-sectional view taken along the dashed line d in;

[0043] Figure 6 Partial perspective view of the sealing ring structure of a chip according to an embodiment of the present invention;

[0044] Explanation of reference numerals:

[0045] 11 - Inner sealing ring 11,

[0046] 111 - Straight edge,

[0047] 112 - Chamfer,

[0048] 113 - Metal layer,

[0049] 114 - First metal strip,

[0050] 115 - Metal strip,

[0051] 116 - Fifth metal strip;

[0052] 12 - Outer sealing ring,

[0053] 121 - Straight edge,

[0054] 122 - Chamfer,

[0055] 123 - Metal layer,

[0056] 124 - Second metal strip,

[0057] 125 - Metal strip;

[0058] 13 - Right - angled triangle sealing area,

[0059] 131 - Hypotenuse,

[0060] 132 - Metal layer,

[0061] 133 - Third metal strip,

[0062] 134 - Fourth metal strip,

[0063] 135 - Metal strip;

[0064] 21 - Substrate. Detailed implementation manners

[0065] Next, the technical solutions in the embodiments of the present utility model will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all the embodiments. Based on the embodiments in the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present utility model.

[0066] In the description of the specification of the present utility model, it should be understood that the orientation or positional relationship indicated by the terms "upper part", "lower part", "upper end", "lower end", "lower surface", "upper surface", etc. is the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation to the present utility model.

[0067] In the description of the specification of the present utility model, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features.

[0068] In the description of the present utility model, the meaning of "a plurality" is a plurality, such as two, three, four, etc., unless otherwise specifically defined.

[0069] In the description of the specification of the present utility model, unless otherwise clearly defined and limited, terms such as "connection" shall be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral body; it may be a mechanical connection, an electrical connection, or a connection that allows mutual communication; it may be directly connected, or indirectly connected through an intermediate medium, and it may be the communication inside two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.

[0070] The technical solution of the present utility model will be described in detail below with specific embodiments. These specific embodiments can be combined with each other, and for the same or similar concepts or processes, they may not be repeated in some embodiments.

[0071] In one embodiment, a sealing ring structure for a chip is provided, which is disposed in a dielectric layer above a substrate around a chip body. Please refer to Figure 2 , the sealing ring structure includes: an inner sealing ring 11, at least one outer sealing ring 12, and a plurality of right triangle sealing regions 13. Among them, the inner sealing ring 11 is disposed around the chip body (not shown in the figure), the outer sealing ring 12 is disposed around the inner sealing ring 11; the right triangle sealing region 13 is disposed outside the outermost outer sealing ring 12. Specifically, when there is one outer sealing ring, the right triangle sealing region is disposed outside this outer sealing ring; when there are multiple outer sealing rings, the right triangle sealing region is disposed outside the outermost outer sealing ring.

[0072] Implementably, a chamfer 112 is formed between adjacent straight sides 111 of the inner sealing ring 11. Please refer to Figure 3 . The chip body is generally a square structure (such as a square), correspondingly, the sealing ring structure can also be a square structure, that is, the extension lines of adjacent straight sides of the inner sealing ring are at right angles, and at this time, there are four chamfers 112. As Figures 4a - 4c shown, along the thickness direction of the chip body, the inner sealing ring includes multiple metal layers 113. Please refer to Figure 4b , 4c . Between adjacent metal layers 113 corresponding to the inner sealing ring, there are a number of first metal strips 114 that are staggeredly distributed and coupled between the two. Please refer to Figure 3 , Figure 4a . Among them, the first metal strips 114 are disposed along the circumferential direction of the inner sealing ring.

[0073] Preferably, a number of first metal strips 114 are distributed in a star-shaped network. Please refer to Figure 3 , Figure 4a , and the star-shaped network distribution structure is more stable, with better anti-rupture and anti-deformation properties.

[0074] Implementably, a chamfer 122 is formed between adjacent straight edges 121 of the outer sealing ring 12. Please refer to Figure 3 . Similarly, when the extended lines of the adjacent straight edges of the outer sealing ring form a right angle, there are four chamfers 122. As Figures 4a - 4c shown, along the thickness direction of the chip body, the outer sealing ring includes multiple metal layers 123. Please refer to Figure 4b 、 4c . Between the adjacent metal layers 123 corresponding to the outer sealing ring, there are several second metal strips 124 distributed alternately and coupled between the two. Please refer to Figure 3 、 Figure 4a . Among them, the second metal strips 124 are arranged along the circumferential direction of the outer sealing ring.

[0075] Preferably, several second metal strips 124 are orthogonally distributed. Please refer to Figure 3 、 Figure 4a . The orthogonally distributed structure is more stable, with better anti - cracking and anti - deformation properties.

[0076] Implementably, the hypotenuse 131 of the right - triangle sealing region 13 faces the chamfer 122 of the outermost outer sealing ring, and the extended line of the straight edge of the outermost outer sealing ring overlaps with the right - angle side of the right - triangle sealing region, that is, it looks like a square structure as a whole. Please refer to Figure 2 、 Figure 3 shown. Along the thickness direction of the chip body, the right - triangle sealing region 13 includes multiple metal layers 132. Please refer to Figure 5b 、 Figure 5c ; between the adjacent metal layers 132 corresponding to the right - triangle sealing region, there are third metal strips 133 and multiple fourth metal strips 134 distributed alternately and coupled between the two. Among them, the third metal strips 133 are arranged along the circumferential direction of the right - triangle sealing region, and the fourth metal strips 134 are located inside the third metal strips 133. Please refer to Figure 3 、 Figure 5a . By arranging multiple metal strips to cross - connect in the right - triangle sealing region, the four top corners of the entire chip sealing ring are more resistant to cracking and deformation, preventing the chip sealing ring from breaking during the chip cutting process and damaging the chip.

[0077] In summary, for a chip sealing ring structure proposed by the present utility model, by arranging an inner sealing ring, at least one outer sealing ring, and multiple right - triangle sealing regions around the chip, and arranging multiple intersecting metal strips in each metal layer of the inner sealing ring, outer sealing ring, and right - triangle sealing region, the stability of the sealing ring structure is improved, especially the stability at the corners.

[0078] Each metal layer of the sealing ring of the chip and the metal strips between adjacent metal layers are fabricated synchronously with the metal interconnect layer (metal layers and metal wires) in the chip region. The metal interconnect layer of the chip includes contact holes between the device layer and the bottommost metal layer in addition to metal wires and multiple metal layers. Therefore, there are also metal contact holes between the bottommost metal layer of the sealing ring and the substrate. To ensure the stability of the sealing ring, in one embodiment, between the bottommost metal layer 113 of the inner sealing ring 11 and the substrate 21, there are multiple metal strips 115 distributed in a staggered manner and coupled between the two. Please refer to Figure 4b 、 Figure 4c 。The metal strips 115 are metal contact holes, and the staggered distribution can enhance the stability of the inner sealing ring. The distribution of the metal strips 115 can be the same as the distribution of the metal strips between the adjacent metal layer above it, that is, it can be distributed in a star-shaped network, and the stability is better.

[0079] Between the bottommost metal layer 123 of the outer sealing ring 12 and the substrate 21, there are multiple metal strips 125 distributed in a staggered manner and coupled between the two. Please refer to Figure 4b 、 Figure 4c 。The metal strips 125 are contact holes, and the staggered distribution can enhance the stability of the outer sealing ring. The distribution of the metal strips 125 can be the same as the distribution of the metal strips between the adjacent metal layer above it, that is, it can be distributed orthogonally, and the stability is better.

[0080] Between the bottommost metal layer 132 of the right-angled triangle sealing region 13 and the substrate 21, there are multiple metal strips 135 distributed in a staggered manner and coupled between the two. Please refer to Figure 5b 、 5c 。The metal strips 135 are contact holes, and the staggered distribution can enhance the stability of the right-angled triangle sealing region. The distribution of the metal strips 135 can be the same as the distribution of the metal strips between the adjacent metal layer above it.

[0081] Since there is a chamfer in the inner sealing ring, the first metal strip 114 distributed along the circumferential direction will have a corner due to the chamfer. To strengthen the stability of the first metal strip 114 and improve the stability of the inner sealing ring, in one embodiment, between the adjacent metal layers corresponding to the inner sealing ring, there are also multiple fifth metal strips 116 coupled between the two. Please refer to Figure 6 ,The fifth metal strips 116 are arranged at the corners of the first metal strip 114 distributed along the circumferential direction of the inner sealing ring and are perpendicular to the circumferential distribution direction. The corner is located on the edge where the straight side of the inner sealing ring intersects with the chamfer. The arrangement of the fifth metal strips further strengthens the stability of the inner sealing ring at the corner position.

[0082] In one embodiment, the fourth metal strips 134 in the right-angled triangle sealing region are parallel or orthogonal to each other. Please refer to Figure 5a。The orthogonally distributed metal strips have stronger stability. A right-angled triangle sealing area with orthogonally distributed metal strips is provided at the four corners of the sealing ring, making the entire sealing ring more resistant to cracking and deformation.

[0083] In one embodiment, the interval D between two adjacent parallel fourth metal strips 134 is 1 micrometer. Please refer to Figure 5a 。The lengths of different fourth metal strips have a gradient difference, and the distances between two adjacent parallel fourth metal strips are all kept the same, further enhancing the stability of the right-angled triangle sealing area.

[0084] In one embodiment, the width of the inner sealing ring can be greater than the width of the outer sealing ring. Please refer to Figure 3 。The inner sealing ring is closer to the chip body. Designing its width to be wider provides better protection for the chip body.

[0085] Preferably, the ratio of the width of the inner sealing ring to the width of the outer sealing ring can be 10 / 3. For example, the width W1 of the inner sealing ring can be 5 micrometers, and the width W2 of the outer sealing ring can be 1.5 micrometers. Please refer to Figure 3 。

[0086] To further improve the stability of the sealing ring, the spacing between adjacent sealing rings can be less than the width of each sealing ring itself. For example: when the width of the inner sealing ring is 5 micrometers and the width of the outer sealing ring is 1.5 micrometers, the spacing R1 between the outermost inner sealing ring and the inner sealing ring can be 1 micrometer; when there are multiple outer sealing rings, the spacing R2 between adjacent outer sealing rings can also be 1 micrometer. Please refer to Figure 3 。The spacing between the sealing rings is relatively small, less than the width of each sealing ring itself, and the gap is relatively small, thus improving the stability of the sealing ring and making the protection effect of the sealing ring on the chip body better.

[0087] In the above illustrations, two outer sealing rings are taken as an example. In different embodiments, the outer sealing ring can also include one; or it can also include more than two. Those skilled in the art can select the number of outer sealing rings according to specific situations, and no limitation is made here.

[0088] In one embodiment, a chip is further provided, which includes:

[0089] A chip body;

[0090] A sealing ring structure is provided around the chip body; the sealing ring structure can be the sealing ring structure described in any of the above embodiments. The corner positions of the inner sealing ring and at least one outer sealing ring are provided with a chamfered structure, which enhances the stability at this position; a right-angled triangle sealing area is provided outside the chamfer of the outermost sealing ring, making the stability at the corner position stronger; the extension line of the straight edge of the outermost outer sealing ring overlaps with the right-angled side of the right-angled triangle sealing area, and the sealing ring structure forms a square structure, making the overall structure more stable; the inner sealing ring, the outer sealing ring and the right-angled triangle sealing area include multiple metal layers, and a number of staggered metal strips are arranged between adjacent metal layers and coupled between the two. The staggered distribution of the metal strips makes the structure of the sealing ring more stable, and makes the contact area between the metal strips and the metal layers larger, with stronger anti-cracking and anti-stress deformation characteristics.

[0091] In the description of this specification, the descriptions with reference to terms such as "an implementation manner", "an embodiment", "specific implementation process", "an example", etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0092] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A sealing ring structure for a chip, the sealing ring structure being disposed in a dielectric layer above a substrate around a chip body, characterized in that, Comprising: An inner sealing ring, which is arranged around the chip body and includes a plurality of straight edges. The extension lines of adjacent straight edges form a right angle, and a chamfer is formed between adjacent straight edges; At least one outer sealing ring, which is arranged around the inner sealing ring, and a chamfer is formed between adjacent straight edges; A plurality of right-angled triangle sealing regions, which are arranged outside the chamfer of the outermost outer sealing ring. The hypotenuse of the right-angled triangle sealing region faces the chamfer, and the right-angled sides of the right-angled triangle sealing region overlap with the extension lines of the straight edges of the outermost outer sealing ring; Along the thickness direction of the chip body, the inner sealing ring, the outer sealing ring and the right-angled triangle sealing region include multiple metal layers, and a number of staggered metal strips are arranged between adjacent metal layers and coupled between the two; 2. The seal ring structure according to claim 1, wherein The metal strips include first metal strips, second metal strips, third metal strips and fourth metal strips; The first metal strips are arranged between adjacent metal layers of the inner sealing ring and are distributed circumferentially along the inner sealing ring in a star-shaped network; The second metal strips are arranged between adjacent metal layers of the outer sealing ring and are distributed circumferentially along the outer sealing ring in a cross shape; The third metal strips and the fourth metal strips are arranged between adjacent metal layers of the right-angled triangle sealing region. The third metal strips are arranged circumferentially along the right-angled triangle sealing region, and the fourth metal strips are orthogonally distributed inside the third metal strips; 3. The sealing ring structure according to claim 1, wherein Between the bottommost metal layer of the inner sealing ring and the substrate, there are a plurality of staggered metal strips coupled between the two; Between the bottommost metal layer of the outer sealing ring and the substrate, there are a plurality of staggered metal strips coupled between the two; Between the bottommost metal layer of the right-angled triangle sealing region and the substrate, there are a plurality of staggered metal strips coupled between the two; 4. The seal ring structure according to claim 2, characterized in that, Between the corresponding adjacent metal layers of the inner sealing ring, there are also a plurality of fifth metal strips coupled between the two; the fifth metal strips are arranged at the corners where the first metal strips are distributed circumferentially along the inner sealing ring and are perpendicular to the circumferential distribution direction, and the corners are located on the edges where the straight edges of the inner sealing ring intersect with the chamfer; 5. The sealing ring structure according to claim 2, characterized in that, The fourth metal strips are parallel or orthogonal to each other in pairs; 6. The seal ring structure according to claim 5, wherein The interval between two adjacent parallel fourth metal strips is 1 micron; 7. The seal ring structure according to any one of claims 1 to 6, characterized in that, The width of the inner sealing ring is greater than the width of the outer sealing ring; 8. The seal ring structure according to claim 7, characterized in that, The width of the inner sealing ring is 5 microns; and / or, The width of the outer sealing ring is 1.5 microns; 9. The seal ring structure according to claim 8, characterized in that, The distance between the innermost outer sealing ring and the inner sealing ring is 1 micron; and / or, When there are multiple outer sealing rings, the distance between adjacent outer sealing rings is 1 micron; 10. A chip, characterized in that, Comprising: A chip body; A sealing ring structure, which is arranged around the chip body; the sealing ring structure is the sealing ring structure according to any one of claims 1 to 9.

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