Battery charging and discharging current switching control circuit
The battery charging and discharging control circuit designed with NOT gate logic circuits and transistor diodes solves the problem that charging and discharging cannot be performed simultaneously and the control is slow in the existing technology. It realizes instantaneous switching and synchronous control of battery charging and discharging, and improves the speed and reliability of control.
Patent Information
- Application Number
- CN202423204848.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-25
- Publication Date
- 2026-01-30
- Estimated Expiration
- 2034-12-25
AI Technical Summary
In existing battery charging and discharging designs, charging and discharging cannot be performed simultaneously, and the control action is slow. Mechanical relays are prone to damage, and charging and discharging can easily become uncontrolled when the battery is powered on or off.
The battery charging and discharging is controlled by NOT gate logic circuits. The instantaneous switching between charging and discharging is achieved through NOT gate logic circuits. Combined with transistor and diode design, the switching states of the charging and discharging power modules are controlled respectively, and the current signal is collected through A/D conversion.
It achieves instantaneous switching and synchronous control of battery charging and discharging, avoiding damage to mechanical relays and uncontrolled charging and discharging, and improving the speed and reliability of control.
Smart Images
Figure CN223858886U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to a battery charging and discharging current switching control circuit. BACKGROUND
[0002] In the design of battery charging and discharging, charging and discharging never happen at the same time, so generally adopt relay or contactor to realize, its defect because mechanical, control action is slow, and contact point is damaged because of contact instantaneous electric spark, and when the equipment is powered on or shutdown, if charging uses a relay, discharging uses a relay, will act simultaneously, causes charging and discharging simultaneously, causes charging to lose control. If it is to use the same relay, will act frequently when power on and shutdown, cause contact point to be damaged.
[0003] Therefore, provide a battery charging and discharging current switching control circuit. UTILITY MODEL CONTENTS
[0004] The utility model discloses a battery charging and discharging current switching control circuit that overcomes the defects of the prior art, and guarantees instantaneous switching of charging and discharging.
[0005] The technical scheme for achieving the above-mentioned object is as follows:
[0006] A battery charging and discharging current switching control circuit, comprising: a charging control signal and a discharging control signal,
[0007] The charging control signal is connected to the input end of the first NAND gate and the first NAND gate, respectively;
[0008] The output end of the first NAND gate is connected to the input end of the second NAND gate and the third NAND gate, respectively;
[0009] The discharging control signal is connected to the input end of the second NAND gate, another input end of the second NAND gate and the third NAND gate, respectively;
[0010] The output end of the second NAND gate is connected to another input end of the first NAND gate;
[0011] The output end of the first NAND gate is connected to the base of the first triode through a first resistor;
[0012] The collector of the first triode is connected to a charging power module, and the emitter is connected to the anode of the first diode;
[0013] The output end of the second NAND gate is connected to the base of the second triode through a second resistor;
[0014] The collector of the second triode is connected to a discharging power module, and the emitter is connected to the anode of the second diode;
[0015] The cathodes of the first diode and the second diode are grounded.
[0016] The output of the third NAND gate is connected to the input of the third NOT gate.
[0017] Preferably, the charging current A / D (analog-to-digital) conversion control signal is acquired through the output terminal of the third NAND gate, and the charging current is sampled when the level is high.
[0018] Preferably, the discharge current A / D conversion control signal is acquired through the output terminal of the third NOT gate, and the discharge current is sampled when the level is high.
[0019] The beneficial effects of this invention are as follows: When the input charging control signal CTLA is high and the discharge control signal CTLB is low, the charging control signal CTLC is output as low through the first NOT gate, the second NOT gate, and the first NAND gate, controlling the collector of the first transistor to be at a high potential. Simultaneously, the discharge control signal CTLF is output as high through the first NOT gate, the second NOT gate, and the second NAND gate, controlling the collector of the second transistor to be at a low potential, thereby disabling the discharge power module. Correspondingly, when the input charging control signal CTLA is low and the discharge control signal CTLB is high… The discharge control signal CTLF is output as low by the first NOT gate, the second NOT gate, and the second NAND gate, controlling the collector of the second transistor to be at a high potential. Similarly, the charging control signal CTLC is output as high by the first NOT gate, the second NOT gate, and the first NAND gate, controlling the collector of the first transistor to be at a low potential, thereby disabling the charging power module. In the discharge state, when the input charging control signal CTLA is low and the discharge control signal CTLB is high, the discharge current A / D conversion control signal CTDF is high. At this time, the discharge current is sampled, thereby achieving the purpose of synchronizing control and sampling. Attached Figure Description
[0020] Figure 1 This is a circuit diagram of a battery charging and discharging current switching control circuit according to the present invention. Detailed Implementation
[0021] The technical solution of this utility model will now be clearly and completely described in conjunction with the accompanying drawings. In the description of this utility model, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing this utility model and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0022] The utility model will be further described below with reference to the drawings.
[0023] As Figure 1 As shown in a kind of battery charging and discharging current switching control circuit, comprising: charging control signal CTLA and discharging control signal CTLB, charging control signal CTLA is connected respectively the input end of first NAND gate U1 and first NAND gate U3;The output end of first NAND gate U1 is connected respectively the input end of second NAND gate U4 and third NAND gate U5;Discharging control signal CTLB is connected respectively the input end of second NAND gate U2, another input end of second NAND gate U4 and third NAND gate U5;The output end of second NAND gate U2 is connected another input end of first NAND gate U3;The output end of first NAND gate U3 is connected the base of first triode Q1 by first resistance R1;The collector of first triode Q1 is connected charging power module, emitter is connected the anode of first diode D1;The output end of second NAND gate U4 is connected the base of second triode Q2 by second resistance R2;The collector of second triode Q2 is connected discharging power module, emitter is connected the anode of second diode D2;The cathode of first diode D1 and second diode D2 is all grounded;The output end of third NAND gate U5 is connected the input end of third NAND gate U6.
[0024] In the embodiment, the charging current A / D conversion control signal CTDC is collected by the output end of third NAND gate U5, and the charging current sampling is carried out when high level is carried out.
[0025] In the embodiment, the discharging current A / D conversion control signal CTDF is collected by the output end of third NAND gate U6, and the discharging current sampling is carried out when high level is carried out.
[0026]
[0027] Table 1
[0028] From Table 1, the CTLC low level controls charging, the CTLF low level controls discharging, the CTDC high level controls charging current sampling, the CTDF high level controls discharging current sampling; when the input charging control signal CTLA is high level and the discharging control signal CTLB is low level, the first NAND gate U1, the second NAND gate U2 and the first NAND gate U3 output the charging control signal CTLC as low level to control the collector of the first transistor Q1 as high potential, at the same time, the first NAND gate U1, the second NAND gate U2 and the second NAND gate U4 output the discharging control signal CTLF as high level to control the collector of the second transistor Q2 as low potential, thereby prohibiting the discharging power module from working; correspondingly, when the input charging control signal CTLA is low level and the discharging control signal CTLB is high level, the first NAND gate U1, the second NAND gate U2 and the second NAND gate U4 output the discharging control signal CTLF as low level to control the collector of the second transistor Q2 as high potential, as above, the first NAND gate U1, the second NAND gate U2 and the first NAND gate U3 output the charging control signal CTLC as high level to control the collector of the first transistor Q1 as low potential, thereby prohibiting the charging power module from working; from Figure 1 As can be seen from Table 1, only in the discharging state, that is, the input charging control signal CTLA is low level and the discharging control signal CTLB is high level, the discharging current A / D conversion control signal CTDF is high level, at this time, the discharging current is sampled, thereby achieving the purpose of synchronous control and sampling.
[0029] The above embodiments are only used to illustrate the technical solutions of the present application, but not limit the present application; although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions recorded in the above embodiments can be modified, or some or all of the technical features can be replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A battery charge-discharge current switching control circuit characterized by comprising: The application relates to a charging and discharging control circuit, comprising: a charging control signal (CTLA) and a discharging control signal (CTLB), the charging control signal (CTLA) is connected to the input end of a first NAND gate (U1) and a first NAND gate (U3) respectively; the output end of the first NAND gate (U1) is connected to the input end of a second NAND gate (U4) and a third NAND gate (U5) respectively; the discharging control signal (CTLB) is connected to the input end of a second NAND gate (U2), the other input end of the second NAND gate (U4) and the third NAND gate (U5) respectively; the output end of the second NAND gate (U2) is connected to the other input end of the first NAND gate (U3); the output end of the first NAND gate (U3) is connected to the base of a first triode (Q1) through a first resistor (R1); the collector of the first triode (Q1) is connected to a charging power module, and the emitter is connected to the anode of a first diode (D1); the output end of the second NAND gate (U4) is connected to the base of a second triode (Q2) through a second resistor (R2); the collector of the second triode (Q2) is connected to a discharging power module, and the emitter is connected to the anode of a second diode (D2); the cathodes of the first diode (D1) and the second diode (D2) are grounded; the output end of the third NAND gate (U5) is connected to the input end of a third NAND gate (U6).
2. The battery charge-discharge current switching control circuit according to claim 1, wherein The charging current A / D conversion control signal (CTDC) is collected through the output end of the third NAND gate (U5) to sample the charging current when the high level is carried out.
3. The battery charge-discharge current switching control circuit according to claim 1, wherein The discharging current A / D conversion control signal (CTDF) is collected through the output end of the third NAND gate (U6) to sample the discharging current when the high level is carried out.