Shield gate trench MOSFET layout and device

Abstract

The utility model provides a shield gate trench MOSFET layout and device, and the layout and device are characterized in that the edge position of a vapor deposition silicon oxide mask region is changed, a trench is staggered from a source polysilicon mask, and when the vapor deposition silicon oxide mask is used for etching, a hole can appear in a first trench of a cellular region, so that terminal polysilicon is connected with a contact hole, and the reliability of the mask region is improved. Therefore, not only can electric leakage of the source gate be avoided, but also the performance of avalanche energy (EAS for short) can be improved.

Description

Technical Field

[0001] This application relates to various embodiments in the field of semiconductor technology, and particularly to a shielded gate trench MOSFET layout and device. Background Technology

[0002] In the layout design of shielded gate power MOSFETs, the source polysilicon electrode, gate, and source need to be connected separately, and the source polysilicon electrode needs to be isolated from the gate. Before design optimization, such as Figure 1 As shown, since the edges of the source polysilicon mask 8 and the vapor-deposited silicon oxide mask 9 are at the same position, when etching the vapor-deposited oxide, the first terminal polysilicon near the cell region will form a void due to the side-cutting. When the gate polysilicon is filled later, it will also fill this void. If this terminal polysilicon near the cell region is connected to a contact hole, it will cause a gate-source short circuit and leakage. If it is not connected to a contact hole, the terminal source polysilicon release hole can only be in the upper and lower sections of the wafer, and it is impossible to make contact holes all around. This will result in uneven current, which may lead to avalanche energy (EAS) failure. Summary of the Invention

[0003] To address or mitigate the problems in the prior art, this application modifies the edge position of the vapor-deposited silicon oxide mask area, offsetting it from the source polysilicon mask by a trench. During etching with the vapor-deposited silicon oxide mask, voids appear in the first trench of the cell region. This prevents the terminal polysilicon connection contact hole from contacting the gate polysilicon, thus avoiding source-gate leakage and improving avalanche energy (EAS) performance.

[0004] In a first aspect, embodiments of this application provide a shielded gate trench MOSFET layout, including: a termination region and a cell region;

[0005] The terminal area is located on the periphery of the cell region;

[0006] The terminal area includes a plurality of spaced-apart first groove areas, and each first groove area is provided with a terminal contact hole area;

[0007] The cell region includes a plurality of spaced second trench regions, each of which is provided with a gate polysilicon contact hole region; source polysilicon contact hole regions and source contact hole regions are spaced apart between the second trench regions;

[0008] The cell region is provided with an active polycrystalline silicon film area and a vapor-deposited silicon oxide mask area;

[0009] The cross-section of the source polycrystalline silicon film area is larger than the cross-section of the vapor-deposited silicon oxide mask area;

[0010] The edge of the vapor-deposited silicon oxide mask near the terminal area is separated from the source polycrystalline silicon film area by a second trench;

[0011] A terminal contact hole area is provided in the first trench area adjacent to the cell area.

[0012] In a preferred embodiment of this application, the edge of the vapor-deposited silicon oxide mask area near the terminal area is disposed between adjacent second trench areas;

[0013] The edge of the source polycrystalline silicon film area near the terminal area is positioned between the adjacent first trench area and the second trench area.

[0014] Compared with the prior art, the present application provides a layout of a shielded gate trench MOSFET, which mainly avoids source-gate leakage and improves avalanche energy (EAS) performance by changing the mask position of the vapor-deposited silicon oxide between the source polysilicon and the gate polysilicon, as well as the position of the contact hole in the termination region.

[0015] Secondly, embodiments of this application also provide a shielded gate trench MOSFET device, fabricated using the layout described in the first aspect.

[0016] Compared with the prior art, the beneficial effects of the shielded gate trench MOSFET provided in this application are the same as those of the technical solution provided in the first aspect, and will not be repeated here. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. Some specific embodiments of this application will be described in detail below with reference to the accompanying drawings in an exemplary and non-limiting manner. The same reference numerals in the drawings designate the same or similar parts or components. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings:

[0018] Figure 1 This is a schematic diagram of a shielded gate trench MOSFET provided by existing technology;

[0019] Figure 2 This is a schematic diagram of a shielded gate trench MOSFET provided in this application. Detailed Implementation

[0020] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some, not all, of the embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort should fall within the scope of protection of the present application.

[0021] Firstly, such as Figure 2 As shown, this application embodiment provides a shielded gate trench MOSFET layout, including: a terminal region 1 and a cell region 2;

[0022] The terminal region 1 is located on the periphery of the cell region 2;

[0023] The terminal area 1 includes a plurality of spaced first groove areas 3, and each first groove area 3 is provided with a terminal contact hole area 5;

[0024] The cell region 2 includes a plurality of spaced second trench regions 4, each of which is provided with a gate polysilicon contact hole region 7; source polysilicon contact hole regions and source contact hole region terminal regions 10 are spaced apart between the second trench regions 4.

[0025] The cell region 2 is provided with an active polysilicon mask region 8 and a vapor-deposited silicon oxide mask region 9;

[0026] The cross-section of the source polycrystalline silicon mask region 8 is larger than the cross-section of the vapor-deposited silicon oxide mask region 9;

[0027] The edge of the vapor-deposited silicon oxide mask area 9 near the terminal area 1 is separated from the source polysilicon mask area 8 by a second trench area 4.

[0028] A terminal contact hole area 5 is provided in the first trench area 3 adjacent to the cell area 2.

[0029] This application modifies the edge position of the vapor-deposited silicon oxide mask region 9 to offset it from the source polysilicon mask by a trench. When the vapor-deposited silicon oxide mask is etched, voids will appear in the first and second trenches of the cell region 2. In this way, the terminal polysilicon connection contact hole will not come into contact with the gate polysilicon, which can avoid source-gate leakage and improve avalanche energy (EAS) performance.

[0030] Secondly, embodiments of this application also provide a shielded gate trench MOSFET, fabricated using the layout described in the first aspect.

[0031] Compared with the prior art, the beneficial effects of the shielded gate trench MOSFET provided in this application are the same as those of the technical solution provided in the first aspect, and will not be repeated here.

[0032] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A shielded gate trench MOSFET layout, characterized by, Comprising: a terminal region and a cell region; the terminal region is disposed at the periphery of the cell region; the terminal region comprises a plurality of first trench regions disposed at intervals, each of the first trench regions is provided with a terminal contact hole region; the cell region comprises a plurality of second trench regions disposed at intervals, each of the second trench regions is provided with a gate polysilicon contact hole region; and the second trench regions are provided with source polysilicon contact hole regions and source contact hole regions at intervals; the cell region is provided with a source polysilicon film region and a vapor deposition silicon oxide mask region; the cross section of the source polysilicon film region is larger than the cross section of the vapor deposition silicon oxide mask region; the edge of the vapor deposition silicon oxide mask region close to the terminal region is spaced apart from the source polysilicon film region by a second trench; the terminal contact hole region is disposed in the first trench region adjacent to the cell region.

2. A shielded gate trench MOSFET layout as described in claim 1, wherein, the edge of the vapor deposition silicon oxide mask region close to the terminal region is disposed between adjacent second trench regions; the edge of the source polysilicon film region close to the terminal region is disposed between adjacent first trench regions and second trench regions.

3. A shielded gate trench MOSFET device characterized by, A layout is prepared according to claim 1 or 2.

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