A detection system for back drilling depth and offset of a PCB board

Abstract

The utility model relates to a detection system for back -drilling depth and offset degree of PCB board, including setting on the gradient copper -avoiding ring test module of the PCB board of measurement, the gradient copper -avoiding ring test module includes setting on the PCB circuit board of at least 6 layers multiple PTH hole, copper -avoiding ring, back -drilling hole, test point and test hole, the equidistance arrangement n+1 test points and n PTH hole are provided on the first layer circuit board, and the adjacent two test points are equipped with 6 test holes, and 6 test holes form a regular hexagon with PTH hole as center, the cross line is set up on the second layer circuit board, the n copper -avoiding rings of copper -avoiding amount gradient increasing are set up on the third layer circuit board, and the one -line circuit is set up on the fourth layer circuit board, the same PTH hole, test point and test hole are set up on the uppermost layer circuit board with the first layer circuit board. The utility model discloses through setting test back -drilling hole and detection module, has realized non -destructive, fast, accurate detection.

Description

Technical Field

[0001] This utility model relates to the field of printed circuit board manufacturing technology, and in particular to a detection system for back drilling depth and offset of PCB boards. Background Technology

[0002] Back drilling is an important technique in the production of printed circuit boards (PCBs). Back drilling removes copper from vias that do not serve any connection or transmission function, preventing signal distortion caused by residual copper. However, in quality control of back drilling, the drilling depth is a key factor affecting signal integrity. Currently, metallographic section analysis is commonly used for PCB back drilling quality monitoring. The specific process involves: physically cutting the back-drilled sample during the first-article verification stage, observing the cross-sectional morphology using a metallographic microscope, manually measuring the drilling depth (STUB value), and estimating the average drilling depth using multiple cross-sectional samples.

[0003] However, this solution has the following drawbacks:

[0004] (1) Destructive testing: The slicing process is irreversible, resulting in a high loss of qualified products;

[0005] (2) Poor timeliness: Each test takes a long time, about 1-2 hours, which cannot meet the needs of rapid line replacement;

[0006] (3) Missing spatial dimension: Traditional slicing can only obtain single-point two-dimensional data, which cannot track the borehole axis offset. Since the X / Y direction deviation ≥0.05mm will affect the signal integrity, the offset detection is also important.

[0007] (4) Process control blind spot: Only the first piece can be confirmed, and real-time quality feedback in continuous production cannot be achieved.

[0008] Therefore, this utility model proposes a detection system for back drilling depth and offset of PCB boards to overcome the above problems. Utility Model Content

[0009] The purpose of this invention is to overcome the above-mentioned shortcomings and provide a detection system for back-drilling depth and offset of PCB boards. By setting test back-drilling holes and detection modules in the edge area of ​​the printed circuit board, non-destructive, fast and accurate detection is achieved.

[0010] The purpose of this utility model is achieved as follows:

[0011] A detection system for back-drilling depth and offset of PCB board includes a gradient copper avoidance ring test module disposed on the PCB board to be tested. The gradient copper avoidance ring test module includes multiple PTH holes, copper avoidance rings, back-drilling holes, test points and test holes disposed on a PCB board with at least 6 layers.

[0012] The first layer circuit board is provided with n+1 test points and n PTH holes arranged at equal intervals. A PTH hole is set at the center position between two adjacent test points, that is, a test point is set on both the left and right sides of each PTH hole.

[0013] There are 6 test holes between two adjacent test points. These 6 test holes are arranged equidistantly around the PTH hole between the two test points, forming a regular hexagon centered on the PTH hole. The test hole at the upper left of the PTH hole is test hole 1, the test hole at the lower left of the PTH hole is test hole 4, the test hole at the upper right of the PTH hole is test hole 3, the test hole at the lower right of the PTH hole is test hole 2, the test hole directly above the PTH hole is test hole 5, and the test hole directly below the PTH hole is test hole 6.

[0014] The second layer circuit board is provided with cross-shaped lines, and a back-drilled hole is provided on the PTH hole. The diameter D of the back-drilled hole is larger than the diameter of the PTH hole. A connecting line passing through the back-drilled hole is provided between test hole 1 and test hole 2, and a connecting line passing through the back-drilled hole is provided between test hole 3 and test hole 4, thereby forming a cross-shaped line.

[0015] The third layer circuit board is provided with n copper avoidance rings with increasing copper avoidance gradient. Each back drill hole is provided with a copper avoidance ring. The copper avoidance rings are set between two test points and form a copper avoidance ring unit between two adjacent test points.

[0016] A straight line is provided on the fourth layer circuit board, and a connecting line is provided between the fifth test hole and the sixth test hole, thereby forming a straight line.

[0017] The top layer circuit board has the same PTH holes, test points and test holes as the first layer circuit board, and back-drilled holes are set on the PTH holes.

[0018] Furthermore, the copper avoidance amount on one side of the copper avoidance ring increases incrementally in 12.7 μm radius increments to achieve micrometer-level offset detection, i.e., the copper avoidance amount on one side of the nth copper avoidance ring = initial copper avoidance ring radius r1 + ( n- 1)×12.7 μm .

[0019] Furthermore, the diameter D1 of the copper-avoiding ring is dynamically bound to the diameter D of the back-drilled hole, and the diameter D1 of the copper-avoiding ring = DBack drilling + 2 × single-sided copper avoidance amount.

[0020] Furthermore, the line width of the copper-avoiding ring is equal to the diameter tolerance of the back-drilled hole × 1.2.

[0021] Furthermore, the spacing between the copper-avoiding rings is ≥2 × the line width of the copper-avoiding rings.

[0022] Furthermore, the six test holes include two short-circuit test holes and four open-circuit test holes. The two short-circuit test holes and the two open-circuit test holes form a connected loop with the lines on the PCB layer, and their solder rings are at least 0.1 mm larger than one side of the test hole.

[0023] Compared with the prior art, the beneficial effects of this utility model are:

[0024] This invention provides a system for detecting the back-drilling depth and offset of PCB boards, including a gradient copper avoidance ring design system and a daisy-chain topology test hole design system. It effectively overcomes the shortcomings of existing technologies and improves production efficiency and product quality. It has the following advantages:

[0025] (1) Non-destructive testing: avoids the loss of qualified product rate due to physical cutting and improves production efficiency.

[0026] (2) Rapid detection: The detection and analysis results are fast, which can meet the needs of rapid line change and improve production efficiency.

[0027] (3) Multi-dimensional detection: It can track the borehole axis offset and provide more comprehensive detection data.

[0028] (4) Real-time quality feedback: It can provide real-time feedback on quality information during continuous production, and promptly identify and correct problems in the production process. Attached Figure Description

[0029] Figure 1 This is a top view of the gradient copper avoidance ring test module of this utility model.

[0030] Figure 2 This is a schematic diagram of the first layer of the circuit board of this utility model.

[0031] Figure 3 This is a schematic diagram of the second layer of the circuit board of this utility model.

[0032] Figure 4 This is a schematic diagram of the third layer of the circuit board of this utility model.

[0033] Figure 5 This is a schematic diagram of the fourth layer of the circuit board of this utility model.

[0034] Figure 6 This is a schematic diagram of the sixth layer of the circuit board of this utility model.

[0035] Figure 7 This is a schematic diagram of the back drilling depth requirement structure of Embodiment 1 of this utility model.

[0036] in:

[0037] PTH hole 1, copper avoidance ring 2, back drill hole 3, test point 4, test hole 5. Detailed Implementation

[0038] To better understand the technical solution of this utility model, a detailed description will be provided below in conjunction with relevant illustrations. It should be understood that the specific embodiments described below are not intended to limit the specific implementation of the technical solution of this utility model, but are merely possible implementations of the technical solution of this utility model. It should be noted that the descriptions of the positional relationships of the components herein, such as component A being located above component B, are based on the relative positions of the components in the illustrations and are not intended to limit the actual positional relationships of the components. Example 1

[0039] See Figures 1-7 , Figure 1 A top view of the gradient copper avoidance ring test module of this utility model is shown. As shown in the figure, the detection system for back drilling depth and offset of PCB board according to this utility model includes a gradient copper avoidance ring test module disposed on the PCB board to be tested. The gradient copper avoidance ring test module includes multiple PTH holes 1, copper avoidance rings 2, back drilling holes 3, test points 4 and test holes 5 disposed on a 6-layer PCB circuit board.

[0040] The first layer circuit board is provided with n+1 test points 4 and n PTH holes 1 arranged at equal intervals. A PTH hole 1 is set at the center position between two adjacent test points 4, that is, a test point 4 is set on both the left and right sides of each PTH hole 1.

[0041] Six test holes 5 are provided between two adjacent test points 4. These six test holes 5 are arranged equidistantly around the PTH hole 1 between the two test points 4, forming a regular hexagon centered on the PTH hole 1. The test hole at the upper left of the PTH hole 1 is test hole 1 (i.e., endpoint 1), the test hole at the lower left of the PTH hole 1 is test hole 4, the test hole at the upper right of the PTH hole 1 is test hole 3, the test hole at the lower right of the PTH hole 1 is test hole 2, the test hole directly above the PTH hole 1 is test hole 5, and the test hole directly below the PTH hole 1 is test hole 6.

[0042] The second layer circuit board is provided with cross-shaped lines. A back-drilled hole 3 is provided on the PTH hole 1. The diameter D of the back-drilled hole 3 is larger than the diameter of the PTH hole 1. A connecting line passing through the back-drilled hole 3 is provided between the test hole 1 and the test hole 2. A connecting line passing through the back-drilled hole 3 is provided between the test hole 3 and the test hole 4, thereby forming a cross-shaped line.

[0043] The third layer circuit board is provided with n copper avoidance rings 2 with increasing copper avoidance gradient. Each back drill hole 3 is provided with a copper avoidance ring 2 outside. The copper avoidance ring 2 is set between two test points 4 in front and behind, and a copper avoidance ring unit is formed between two adjacent test points 4.

[0044] The first copper avoidance ring (copper avoidance ring No. 1) is the copper avoidance ring outside the back drill hole between the first and second test points. The second copper avoidance ring (copper avoidance ring No. 2) is the copper avoidance ring outside the back drill hole between the second and third test points. The third copper avoidance ring (copper avoidance ring No. 3) is the copper avoidance ring outside the back drill hole between the third and fourth test points, and so on. The nth copper avoidance ring (copper avoidance ring No. n) is the copper avoidance ring outside the back drill hole between the nth test point and the (n+1)th test point.

[0045] A straight line is provided on the fourth layer circuit board, and a connecting line is provided between the fifth test hole and the sixth test hole, thereby forming a straight line.

[0046] The sixth layer circuit board is provided with the same PTH hole 1, test point 4 and test hole 5 as the first layer circuit board, and a back drill hole 3 is provided on the PTH hole 1.

[0047] Therefore, see Figure 1 The six-layer circuit boards are stacked to form a daisy-chain topology network, with the following connection architecture:

[0048] Test point → Copper avoidance ring 1 → Test point 1 → Copper avoidance ring 2 → ... → Copper avoidance ring N → Test point N.

[0049] Radius step size algorithm: Based on the theoretical hole diameter of back drilling, the copper avoidance amount on one side increases incrementally in 0.5mil (12.7μm) radius increments to achieve micron-level offset detection; the copper avoidance amount on one side of the nth ring = initial copper avoidance radius r1 + ( n- 1)×12.7 μm .

[0050] Diameter-related design: To ensure that the design parameters are directly related to the production process, the diameter D1 of the copper-avoiding ring 2 is dynamically linked to the diameter D of the back-drilled hole 3 (hereinafter referred to as the back-drilled hole diameter). The diameter D1 of the copper-avoiding ring = D Back drilling + 2 × single-sided copper avoidance amount.

[0051] Tolerance coverage:

[0052] Back-drilling diameter fluctuation: During the drilling process, the actual hole diameter will fluctuate within the tolerance range (e.g., ±15μm) due to factors such as drill bit wear and mechanical vibration.

[0053] Risk of copper avoidance ring failure: If the line width of the copper avoidance ring is designed only according to the theoretical value (such as 15μm in this embodiment), when the back-drilled hole diameter exceeds the tolerance in the positive direction (+15μm), it may lead to: the copper avoidance ring being drilled through (falsely judged as excessive offset) and bridging between adjacent copper avoidance rings (false short circuit alarm). Therefore, in this embodiment, the hole diameter tolerance is compensated by a coefficient of 1.2 to ensure that the copper avoidance ring can still maintain its complete function even if the back-drilled hole diameter exceeds the tolerance.

[0054] Copper avoidance ring line width = back drill hole diameter tolerance × 1.2. In this embodiment: tolerance ±15μm → line width ≥18μm.

[0055] Ring spacing design: Ring spacing ≥ 2 × copper avoidance ring line width. In this embodiment: 18μm line width → 36μm spacing.

[0056] Specific implementation data:

[0057] 1. Back-drilled hole diameter D=500μm, initial single-sided copper avoidance amount=30μm (diameter increment 60μm);

[0058] 2. Copper avoidance amount on one side of the third ring = 30 + 2 × 12.7 = 55.4 μm

[0059] → Diameter of the copper-avoiding ring = 500 + 2 × 55.4 = 610.8 μm;

[0060] 3. Copper avoidance ring linewidth: 15 μm × 1.2 = 18 μm ⇒ Tolerable aperture positive deviation up to +18 μm;

[0061] 4. Copper avoidance ring spacing design: Line width = 18μm, ring spacing = 30μm (2 times line width).

[0062] This embodiment 1 provides a method for detecting back-drilling depth, based on the aforementioned gradient copper avoidance ring test module, and includes the following:

[0063] S1. Set up the back drill module;

[0064] A back-drilling module is set on the edge area of ​​the printed circuit board (PCB), and a test back-drilling hole with the same depth as the back-drilling hole to be tested is drilled on the back-drilling module.

[0065] S2. Determine the back-drilling depth range and test layer;

[0066] When determining the back-drilling depth range, the number of circuit board layers required to reach the back-drilling depth is used as the test layers, and three adjacent layers of the corresponding depth are set.

[0067] Determine the back-drilling depth range. Based on the required number of circuit board layers (2-4 layers) for the back-drilling depth, set the 2nd to 4th circuit layers as test layers.

[0068] S3. Set up the gradient copper avoidance ring test module;

[0069] S3.1. Six test holes are set around the PTH hole: the test holes include two short-circuit test holes and four open-circuit test holes. Each layer of the board has a circuit. The two short-circuit test holes and the two open-circuit test holes form a connected loop with the circuit. The solder ring is at least 0.1 mm larger than one side of the test hole.

[0070] S3.2. Set up copper avoidance rings according to the gradient;

[0071] S4, Depth Testing;

[0072] Test the continuity between each group of test holes. If there is a continuity between the test holes in a group, it means that the test layers corresponding to the test holes in that group are connected and the back drilling depth has not reached that layer. Conversely, if there is an open circuit between the test holes in a group, it means that the test layers corresponding to the test holes in that group are disconnected and the back drilling depth has reached that layer.

[0073] Specific implementation data:

[0074] 1. See Figure 7 Taking a 6-layer board as an example:

[0075] Layer 2 (protective layer): Horizontal straight line, 5mil wide, with the end connected to the PTH hole;

[0076] Layer 4 (requires a break): Cross-shaped lines, 3mil wide, with endpoints connected to PTH holes.

[0077] Electrical logic:

[0078] Layer 2 terminals 5-6 are on;

[0079] The 1-2 and 3-4 endpoints of Layer 4 are open-circuited;

[0080] Test results: Back drill depth is qualified (L4 is interrupted but L2 is not damaged).

[0081] 2. Taking an 8-layer board as an example:

[0082] Layer 2 (requires a break): Cross-shaped lines, 3mil wide, with endpoints connected to PTH holes;

[0083] Layer 4 (protective layer): horizontal straight line, 5mil wide, with the end connected to the PTH hole.

[0084] Electrical logic:

[0085] Layer 2 endpoints 1-2 and 3-4 are open-circuited:

[0086] The circuit connecting the test hole in the L2 layer of the PCB board is powered on for testing. If the test result is an open circuit, it is determined that the back drill hole has passed through the L2 layer board.

[0087] Laye4's 5-6 endpoints are conducting:

[0088] The circuit connecting the test hole in the L4 layer of the PCB board is powered on for testing. If the test result is a continuity test, it is determined that the back drill hole did not break the L4 layer board.

[0089] Test results: Back drill depth is qualified (L2 is interrupted but L4 is not damaged).

[0090] This embodiment 1 provides a method for detecting back-drill offset, based on the aforementioned gradient copper avoidance ring test module, and includes the following:

[0091] S1, Normal state: When the copper avoidance rings are not in contact with the back drill, IN-OUT is conductive;

[0092] S2, Offset Trigger: When the back drill offset touches a copper avoidance hole ring, IN → that ring → open circuit;

[0093] S3. Precise positioning: Determine the specific trigger ring number through independent test points (test point 1 - test point n) and calculate the offset based on the copper avoidance ring number. If test point 3 is conducting, the offset is ≤55.4μm.

[0094] Working principle:

[0095] This utility model provides a system for detecting the back drilling depth and offset of PCB boards. The core innovations are as follows:

[0096] (1) Gradient copper avoidance ring design system:

[0097] Radius step size algorithm: Based on the theoretical hole diameter of back drilling, the copper avoidance amount on one side is gradually increased in a radius increment of 0.5mil (12.7μm) to achieve micron-level offset detection.

[0098] Diameter-related design: The diameter of the copper avoidance ring is dynamically linked to the back drill hole diameter to ensure that the design parameters are directly related to the production process.

[0099] Tolerance Coverage: By compensating for the hole diameter tolerance with a factor of 1.2, the copper avoidance ring can still maintain its full functionality even if the back-drilled hole diameter is out of tolerance.

[0100] Ring spacing design: Ring spacing ≥ 2 × copper avoidance ring width.

[0101] (2) Daisy chain topology network (to achieve precise positioning of back drill offset through daisy chain topology network):

[0102] Connection architecture: Test point → Copper avoidance ring 1 → Test point 1 → Copper avoidance ring 2 → ... → Copper avoidance ring N → Test point N.

[0103] Detection mechanism: Under normal conditions, IN-OUT is conductive; when the back drill offset touches a copper avoidance ring, the specific trigger ring number is determined by an independent test point, thereby determining the offset amount.

[0104] (3) Depth determination target design (the back drill depth is determined by the design of the depth determination target):

[0105] Test holes: including 2 short-circuit test holes and 4 open-circuit test holes. Each layer of the board has a circuit. The test holes and the circuit form a connected loop. The solder ring is at least 0.1 mm larger than one side of the test hole.

[0106] Test layer: Based on the required number of circuit board layers for back-drilling depth, three adjacent layers of corresponding depth are set as test layers.

[0107] Back-drilling module: A back-drilling module is set up on the edge area of ​​the printed circuit board (PCB), and a test back-drilling hole with the same depth as the back-drilling hole to be tested is drilled on the back-drilling module.

[0108] Test logic: Test the continuity between each group of test holes. If there is a continuity between the test holes in a group, it means that the test layers corresponding to the test holes in that group are connected and the back drilling depth has not reached that layer. Conversely, if there is an open circuit between the test holes in a group, it means that the test layers corresponding to the test holes are disconnected and the back drilling depth has reached that layer.

[0109] The above are merely specific application examples of this utility model and do not constitute any limitation on the scope of protection of this utility model. All technical solutions formed by equivalent transformations or equivalent substitutions fall within the scope of protection of this utility model.

Claims

1. A system for detecting back drill depth and offset for PCB boards, characterized in that: The test module includes a gradient copper avoidance ring test module installed on the PCB board under test. The gradient copper avoidance ring test module includes multiple PTH holes, copper avoidance rings, back drill holes, test points and test holes installed on the PCB board with at least 6 layers. The PCB board with at least 6 layers includes the first layer, the second layer, the third layer, the fourth layer and the top layer arranged from bottom to top. The first layer circuit board is provided with n+1 test points and n PTH holes arranged at equal intervals. A PTH hole is set at the center position between two adjacent test points, that is, a test point is set on both the left and right sides of each PTH hole. There are 6 test holes between two adjacent test points. These 6 test holes are arranged equidistantly around the PTH hole between the two test points, forming a regular hexagon centered on the PTH hole. The test hole at the upper left of the PTH hole is test hole 1, the test hole at the lower left of the PTH hole is test hole 4, the test hole at the upper right of the PTH hole is test hole 3, the test hole at the lower right of the PTH hole is test hole 2, the test hole directly above the PTH hole is test hole 5, and the test hole directly below the PTH hole is test hole 6. The second layer circuit board is provided with cross-shaped lines, and a back-drilled hole is provided on the PTH hole. The diameter D of the back-drilled hole is larger than the diameter of the PTH hole. A connecting line passing through the back-drilled hole is provided between test hole 1 and test hole 2, and a connecting line passing through the back-drilled hole is provided between test hole 3 and test hole 4, thereby forming a cross-shaped line. The third layer circuit board is provided with n copper avoidance rings with increasing copper avoidance gradient. Each back drill hole is provided with a copper avoidance ring. The copper avoidance rings are set between two test points and form a copper avoidance ring unit between two adjacent test points. A straight line is provided on the fourth layer circuit board, and a connecting line is provided between the fifth test hole and the sixth test hole, thereby forming a straight line. The top layer circuit board has the same PTH holes, test points and test holes as the first layer circuit board, and back-drilled holes are set on the PTH holes.

2. The detection system for back drilling depth and offset of PCB boards according to claim 1, characterized in that: The single-side copper-avoiding amount of the copper-avoiding ring is gradually increased by 12.7 μm radius increment, micron-level offset detection is realized, and the single-side copper-avoiding amount of the nth copper-avoiding ring = initial copper-avoiding ring radius .

3. The detection system for back drilling depth and offset of PCB boards according to claim 1, characterized in that: The diameter D1 of the copper-avoiding ring is dynamically bound to the diameter D of the back-drilled hole, and the diameter D1 of the copper-avoiding ring = D Back drilling + 2 × single-sided copper avoidance amount.

4. The detection system for back drilling depth and offset of PCB boards according to claim 1, characterized in that: The line width of the copper-avoiding ring is equal to the diameter tolerance of the back-drilled hole × 1.

2.

5. The detection system for back drilling depth and offset of PCB boards according to claim 1, characterized in that: The spacing between the copper-avoiding rings is ≥2 × the line width of the copper-avoiding rings.

6. The detection system for back drilling depth and offset of PCB boards according to claim 1, characterized in that: The six test holes include two short-circuit test holes and four open-circuit test holes. The two short-circuit test holes and the two open-circuit test holes form a continuous loop with the traces on the PCB layer, and the solder rings are at least 0.1 mm larger than one side of the test hole.

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